Commit graph

64722 commits

Author SHA1 Message Date
Kristian Høgsberg
388f02729b i965: Move pre-draw resolve buffers to dd::UpdateState
No functional change except for glBegin/glEnd style rendering, where we now
do the resolves at glBegin time instead of FLUSH_VERTICES time.  This is also
the reason for this change, so that when we later switch fast clear resolve to
use meta, we won't be doing meta operations in the middle of a begin/end
sequence.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Kristian Høgsberg
cf89b29d2f i965: Provide a context flag to let us enable fast clear
GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle.  To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Kristian Høgsberg
1a05dcb349 i965: Disable clipping when rendering 3DPRIM_RECTLIST primitives
The clipper doesn't support clipping 3DPRIM_RECTLIST primitives and must
be turned off when we use them.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Kristian Høgsberg
3f0f2c7f7d i965: Add a mechanism for sending native primitives into the driver
The brw_draw_prims() function is the draw entry point into the driver,
and takes struct _mesa_prim for input.  We want to be able to feed
native primitives into the driver, and to that end we introduce
BRW_PRIM_OFFSET, which lets use describe geometry using the native
GEN primitive types.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Kristian Høgsberg
ff7a2fc322 i965: Add context flag to disable the viewport transform
This lets us disable the viewport transform, which will be useful for
emitting 3DPRIM_RECTLIST.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Kristian Høgsberg
1effbf6898 i965: Add an option to not generate the SIMD8 fragment shader
For now, this can only be triggered with a new 'no8' INTEL_DEBUG option
and a new context flag.  We'll use the context flag later, but introducing
it now lets us bisect to this commit if it breaks something.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 10:33:41 -07:00
Emil Velikov
0267c6d7ee docs/autoconf: explicitly mention PKG_CONFIG_PATH for cross/multilib builds
... and squash a couple of typos.

Suggested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 18:00:37 +01:00
Emil Velikov
5fe400d82a st/dri: Add __DRI2rendererQueryExtension support
The final step to get GLX_MESA_query_renderer working with gallium
drivers.

v2: Remove __DRI2_RENDERER_PREFERRED_PROFILE handling. It's already
handled in dri/common. Spotted by Marek.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
89f80c2185 gallium/softpipe/llvmpipe: handle query_renderer caps
Both report 0xffffffff as both vendor and device id, and the maximum
amount of system memory as video memory.

v2: Use aux helper os_get_total_physical_memory().

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
3a6b68b113 gallium/svga: handle query_rendered caps
All the values are are currently hardcoded. One could use
some heuristics to determine the amount of video memory if
a callback to the host is not available.

Do we what to advertise the driver as hardwar accelerated ?

Cc: Brian Paul <brianp@vmware.com>
Cc: José Fonseca <jose.r.fonseca@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
2b5f3956be gallium/nouveau: handle query_renderer caps
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
0b67d5d4ce gallium/vc4: handle query_renderer caps
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
de01443753 gallium/r300/r600/radeonsi: handle query_renderer caps
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
cc313b3ffe gallium/ilo: handle query_renderer caps
Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:47 +01:00
Emil Velikov
5b9cb13295 gallium/i915: handle query_renderer caps
Implementation based on the classic driver with the following
changes:
 - Use auxiliarry function os_get_total_physical_memory to get the
total amount of memory.
 - Move the libdrm_intel specific get_aperture_size to the winsys.

Cc: Stephane Marchesin <stephane.marchesin@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:42:46 +01:00
Emil Velikov
e9c43b1f01 gallium/freedreno: handle query_renderer caps
Provide the real vendor and and hardcode the device id as
0xffffffff as the devices currently using freedreno are non-pci.
The device features UMA.

Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-08-15 17:42:43 +01:00
Emil Velikov
8d2745703c auxiliary/os: introduce os_get_total_physical_memory helper function
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:41:57 +01:00
Emil Velikov
139751403c gallium: add GLX_MESA_query_renderer caps
Namely vendor/device id, accelerated and UMA, which will be used to describe
the underlying renderer.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 17:41:34 +01:00
Emil Velikov
64b1dc4449 dri/swrast: add GLX_MESA_query_renderer support
v2:
 - Drop __DRI2_RENDERER_PREFERRED_PROFILE case.
 - Cleanup return statements.

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:38 +01:00
Emil Velikov
9c65361457 dri/radeon: add GLX_MESA_query_renderer support
- Create radeon{Vendor,GetRenderer}String helpers.
 - Drop __DRI2_RENDERER_PREFERRED_PROFILE case.
 - Cleanup return statements.

To be used by the upcomming GLX_MESA_query_renderer implementation.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:38 +01:00
Emil Velikov
55d1251d41 dri/radeon: don't print TCL status on glGetString(GL_RENDERER)
Printing the TCL involves that context is available at the time of
query. The GLX_MESA_query_renderer states that glGetString(GL_RENDERER)
and glXQueryRendererStringMESA(GLX_RENDERER_DEVICE_ID_MESA) will have
the same format, thus removing the context dependenicy will help us
achieve that.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:37 +01:00
Emil Velikov
76f07362ea dri/nouveau: add GLX_MESA_query_renderer support
- Create nouveau_{vendor,get_renderer}_string helpers.
 - Set correct max_gl*version.
 - Query the device PCIID via libdrm_nouveau/nouveau_getparam.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:37 +01:00
Emil Velikov
87d3ae0b45 dri/common: Move __DRI2_RENDERER_PREFFERED_PROFILE handling to driQueryRendererIntegerCommon
Essentially all drivers would like to use to opengl core profile if
available, so avoid duplication by moving the code to a common fallback
within driQueryRendererIntegerCommon.

If a driver uses different approach they can handle it separately.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:37 +01:00
Emil Velikov
679c2ef8a0 glx/drisw: add support for DRI2rendererQueryExtension
The extension is used by GLX_MESA_query_renderer, which
can be provided for by hardware and software drivers.

v2: Use designated initializers.
v3: Move drisw_query_renderer_*() to dri2_query_renderer.c

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:37 +01:00
Emil Velikov
1bccf99c30 glx/dri2: use mapping table for dri2_convert_glx_query_renderer_attribs()
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:37 +01:00
Emil Velikov
d10ba8b7c0 glx/drisw: Move private structure declarations to a header file
v2: Reff the correct file wrt copyright, spotted by Chia-I

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-15 17:35:36 +01:00
Brian Paul
ffb8e884f7 mesa: check if GL_ARB_copy_image is enabled in _mesa_CopyImageSubData()
Generate a GL error and return rather than crashing on a null
ctx->Driver.CopyImageSubData pointer (gallium).  This allows apitraces
with glCopyImageSubData() calls to continue rather than crash.

Plus, fix a comment typo.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-08-15 08:35:17 -06:00
Neil Roberts
aa9d4f9d1a i965/blorp_clear: Use memcpy instead of assignment to copy clear value
Similar to the problem described in 2c50212b14, if we copy the clear
value through a regular assignment via a floating point value, then if an
integer clear value is being used that happens to contain a signalling NaN
value then it would get converted to a quiet NaN when stored via the x87
floating-point registers. This would corrupt the integer value. Instead we
should use a memcpy to ensure the exact bit representation is preserved.

This bug can be triggered on 32-bit builds with optimisations by using an
integer clear color with a value like 0x7f817f81.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 12:35:40 +01:00
Glenn Kennard
afa7df9b78 r600g: Implement ARB_derivative_control
Requires Evergreen/Cayman

marek: update release notes

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-15 12:23:06 +02:00
Chris Forbes
f1370fed2c docs: Update relnotes for ARB_gpu_shader5
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 19:25:10 +12:00
Chris Forbes
139f127aac docs: Mark off ARB_gpu_shader5 for i965
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 19:25:07 +12:00
Chris Forbes
4a3667993e i965: Enable ARB_gpu_shader5 on Gen7
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-15 19:24:56 +12:00
Chris Forbes
abedd05bcd i965/fs: Add support for nonconst sampler indexing in FS visitor
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:33 +12:00
Chris Forbes
fbfcd671a1 i965/fs: Add support for non-const sampler indices in generator
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes
4ba5171f30 i965/fs: Refactor generate_tex in prep for nonconst sampler indexing
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes
2b1204aa96 i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:13:32 +12:00
Chris Forbes
2cd6169e92 i965/vec4: Add support for nonconst sampler indexing in VS visitor
V2: Set force_writemask_all on ADD; this *is* necessary in the VS case
too.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:12:45 +12:00
Chris Forbes
301b71557b i965/vec4: Add support for non-const sampler indices in generator
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:32 +12:00
Chris Forbes
86dc34a0b0 i965: Generalize sampler state pointer mangling for non-const
For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:29 +12:00
Chris Forbes
f7146d1a94 i965/vec4: Refactor generate_tex in prep for non-const samplers
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:28 +12:00
Chris Forbes
8ce3fa8e91 i965: Extract helper function for surface state pointer adjustment
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 19:10:19 +12:00
Chris Forbes
ceaf823e23 docs: Mark off ARB_gpu_shader5 UBO array indexing for i965
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes
70354ca668 i965/vec4: Add visitor support for nonconst ubo block indexing
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes
a55eae9b6d i965/vec4: Generate indirect sends for nonconstant UBO array access
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes
ad9fce6811 i965/fs: Add visitor support for nonconstant UBO indices
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:48 +12:00
Chris Forbes
3fd359b10d i965/fs: Generate indirect sends for nonconstant UBO array accesses
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Chris Forbes
17e0fa9a06 i965: Adjust set_message_descriptor to handle non-sends
We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.

Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Chris Forbes
3512c79789 i965: Add low-level support for indirect sends
This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-15 18:53:47 +12:00
Kenneth Graunke
35ca288165 i965/fs: Add pass to rename registers to break live ranges.
The pass breaks live ranges of virtual registers by allocating new
registers when it sees an assignment to a virtual GRF it's already seen
written.

total instructions in shared programs: 4337879 -> 4335014 (-0.07%)
instructions in affected programs:     343865 -> 341000 (-0.83%)
GAINED:                                46
LOST:                                  1

[mattst88]: Make pass not break in presence of control flow.
            invalidate_live_intervals() only if progress.
            Fix up delta_x/delta_y.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2014-08-14 23:50:12 -07:00
Kenneth Graunke
650c331378 i965: Fix INTDIV math assertions on Broadwell.
Commit c66d928f2c ("i965: Enable INTDIV
in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV
into two SIMD8 operations.

generate_math_gen6 takes two registers - for unary operations, we pass
ARF null for the second operand.  Prior to Broadwell, real operands were
always GRF.  But now they can be IMM as well.

So, check for != ARF instead of == GRF.

+12 piglits.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-14 23:21:34 -07:00