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i965: Enable INTDIV in SIMD16 mode.

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All we need to do is decompose this to two SIMD8 instructions, like we
do in many other cases.  We even already have code for that.

I apparently just botched this last time I tried, and it was easy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2014-07-17 14:33:15 -07:00
parent 24878f31c4
commit c66d928f2c
2 changed files with 2 additions and 14 deletions
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12
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -1404,18 +1404,6 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
int base_mrf = 2;
fs_inst *inst;
switch (opcode) {
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
if (brw->gen >= 7)
no16("SIMD16 INTDIV unsupported\n");
break;
case SHADER_OPCODE_POW:
break;
default:
unreachable("not reached: unsupported binary math opcode.");
}
if (brw->gen >= 8) {
inst = emit(opcode, dst, src0, src1);
} else if (brw->gen >= 6) {

4
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -1620,9 +1620,9 @@ fs_generator::generate_code(exec_list *instructions)
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
assert(brw->gen < 6 || inst->mlen == 0);
if (brw->gen >= 7) {
if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
} else if (brw->gen == 6) {
} else if (brw->gen >= 6) {
generate_math_gen6(inst, dst, src[0], src[1]);
} else {
generate_math_gen4(inst, dst, src[0]);