Commit graph

80360 commits

Author SHA1 Message Date
Michel Dänzer
95eb5e4eed cso: Make sanitize_hash safe for samplers
Remove currently bound sampler states from the hash table before pruning
entries from the hash table, so they cannot accidentally be deleted by
the pruning.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19 17:51:34 +09:00
Michel Dänzer
745e2eaaec cso: Store hash key in struct cso_sampler
Preparation for following changes, no functional change intended.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19 17:51:31 +09:00
Michel Dänzer
9e14238647 cso: Optimize cso_save/restore_fragment_samplers
Only copy/memset the pointers that actually need to be.

v2:
* Cast info->nr_samplers to int for calculating delta (Nicolai)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19 17:50:21 +09:00
Michel Dänzer
5e70f80c99 cso: Store pointers to struct cso_sampler in struct sampler_info
Preparation for following changes, no functional change intended.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19 17:50:17 +09:00
Michel Dänzer
3d661a12be cso: Don't restore nr_samplers in cso_restore_fragment_samplers
If info->nr_samplers > ctx->nr_fragment_samplers_saved, the assignment
would prevent cso_single_sampler_done from unbinding the no longer used
samplers from the driver, which could result in use-after-free. This is
probably unlikely to happen in practice though.

Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19 17:50:08 +09:00
Liu Zhiquan
e2610bf165 EGL/android: Enhance pbuffer implementation
Some dri drivers will pass multiple bits in buffer_mask parameter
to droid_image_get_buffer(), more than the actual supported buffer
type combination. For such case, will go through all the bits, and
will not return error when unsupported buffer is requested, only
return error when the allocation for supported buffer failed.

v2: coding style and log changes
v3: coding style changes and update patch format

Signed-off-by: Liu Zhiquan <zhiquan.liu@intel.com>
Signed-off-by: Long, Zhifang <zhifang.long@intel.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2016-12-19 08:26:32 +02:00
Bas Nieuwenhuizen
1d529cba02 radv: Use correct workgroup size limits.
Not sure where the 16k comes from, but pretty sure 2k is the max.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 22:18:14 +01:00
Dave Airlie
6229994ab7 radv: expose the compute queue
v2: Don't expose the SDMA queue and use the CIK check also in the
    second if. (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:55 +01:00
Bas Nieuwenhuizen
442735d35d radv: Only emit PFP ME syncs for DMA on the GFX queue.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:51 +01:00
Bas Nieuwenhuizen
f2523ebf52 radv: Create an empty CS per ring type.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:47 +01:00
Bas Nieuwenhuizen
accc5fc026 radv: Don't enable CMASK on compute queues.
We can't fast clear on compute queues.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:41 +01:00
Bas Nieuwenhuizen
bfee9866ea radv: Use RELEASE_MEM packet for MEC timestamp query.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:37 +01:00
Bas Nieuwenhuizen
9b0efc98ba radv: Implement indirect dispatch for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:33 +01:00
Bas Nieuwenhuizen
3a559029e2 radv: update vkCmdUpdateBuffer for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:29 +01:00
Bas Nieuwenhuizen
b3499557a2 radv: Implement cache flushing for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:26 +01:00
Dave Airlie
72aaa83f4b radv: add semaphore support
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:26 +01:00
Dave Airlie
d270b5fac3 radv: pass queue index into winsys submission
This is so we can submit on separate queues if needed

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:26 +01:00
Dave Airlie
d0e6fb0574 radv: init compute queue and avoid initing transfer queues
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:26 +01:00
Bas Nieuwenhuizen
71dabe1c16 radv/winsys: Make WaitIdle queue aware.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:20 +01:00
Dave Airlie
d028bd7b55 radv/meta: update header info
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Dave Airlie
4bd666a319 radv: hook compute clears into clear image api.
These aren't used yet but we will want to use them when we
implement a separate compute queue.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Dave Airlie
f11ea8779d radv: clear image implementation for compute queue
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Dave Airlie
9839ce282b radv/meta: split clear image out into a separate layer clear function
This will make it easier to add support for clears on compute queues.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Dave Airlie
ef5f59c9a9 radv: implement image->image copies using compute shader
This is required for having a separate compute queue, we
probably can't use this on GFX queue due to DCC.

v2: Set coord_components = 2 for itoi texture fetch. (Bas)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Dave Airlie
983af3a6d1 radv: add a compute shader implementation for buffer to image
This implements the reverse of the current buffer->image path
and can be used when we need to do image transfer on compute queues

This just adds the code turned off as we don't support separate
computes queues yet, and we don't want to use this path on the GFX
queues for DCC reasons.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:20 +01:00
Bas Nieuwenhuizen
35cf08ef64 radv: Use correct pitch for views with different block size.
Needed when accessing a comrpessed texture as R32G32B32A32 from a shader. This
was not encountered previously, as we used the CB for the reinterpretation, which
does not use this pitch.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:15 +01:00
Dave Airlie
94a7434bbc radv: Store queue family in command buffers.
v2: Added helper (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:15 +01:00
Dave Airlie
c20701f4be radv: start fixing up queue allocate for multiple queues
v2: Fix error handling  and zero init the device (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:15 +01:00
Dave Airlie
59c9a131f4 radv/winsys: start adding support for DMA/compute queue
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18 20:52:15 +01:00
Bas Nieuwenhuizen
86cb418bd4 radv/winsys: Expose number of compute/dma rings.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18 20:52:08 +01:00
Rob Clark
2c0dfd48f0 freedreno/a5xx: border color support
Not 100% sure it works if you have border color in VS.. but it might be
right.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:49:45 -05:00
Rob Clark
939486d3d3 freedreno/a5xx: use MRT0 to import linear zs
A bit of a hack, but we need to do this until we can do tiled zs in
sysmem (and associated tile/until blits for transfer_map).

Fixes xonotic and glmark2 "refract", when reorder wasn't enabled.
(reorder would paper over the issue by avoiding the extra round-
trip to system memory and back to gmem.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:48:10 -05:00
Rob Clark
bea8602e5b freedreno: fdN_gmem_restore_format() is not gen specific
Refactor out into a common helper, since this is the same across
generations when we need equiv z/s gmem restore format.

Next patch needs this in a5xx, rather than creating yet another
helper push this into core.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:48:03 -05:00
Rob Clark
6f93c75a47 freedreno/a5xx: cargo-cult end-batch sequence more faithfully
Fixes some issues at least with GMEM bypass mode, where we'd sometimes
end up with some FS quads not hitting memory.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:54 -05:00
Rob Clark
d35022f24d freedreno/a5xx: misc fix
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:47 -05:00
Rob Clark
651f2655a8 freedreno/a5xx: fix (at least some) vtx formats
Swap/component-order doesn't seem to be quite what that is.  At least
blob was always setting it to XYZW ('11') but we weren't.  Causing
problems w/ formats like sint16..  Hard-coding this instead at least
seems to get glamor working.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:38 -05:00
Rob Clark
2540226f66 freedreno/a5xx: more formats
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:31 -05:00
Rob Clark
c768461c1f freedreno/a5xx: fixup caps
Might not be 100% accurate, mostly just copy from a4xx to get started.

We are defn lying about occlusion query at this point (not implemented
yet) but need it to expose anything higher than gl1.4 (glamor needs
gl2.1)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:18 -05:00
Rob Clark
abcf8f5b58 freedreno/a5xx: fix random faults on first sysmem draw
Not sure what this event is, but blob writes it.. and it seems to solve
random write faults at mystery address that would sometimes happen on
first BYPASS draw.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:08 -05:00
Rob Clark
54537fa1dc freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:47:00 -05:00
Rob Clark
5e632b3a83 freedreno/a5xx: fix stride/size for mem->gmem blits
<brownpaperbag>these should be the in-GMEM dimensions</brownpaperbag>

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18 13:46:48 -05:00
Dave Airlie
0f2e9a8986 radv/winsys: consolidate request->fence code
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-17 16:30:16 +01:00
Dave Airlie
7ad1c24e2a radv: handle fence allocation failing
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-17 16:29:57 +01:00
Bas Nieuwenhuizen
b2b4f7248b radv: Don't bail out on pipeline create failure.
The spec says we have to try to create all, and only set failed
pipelines to VK_NULL_HANDLE. If one of them fails, we have to return
an error, but as far as I can see, the spec does not care which of
the suberrors.

Fixes
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline
dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-17 11:41:53 +01:00
Ilia Mirkin
6493b4f4dd spirv/nir: add support for ImageGatherExtended
The strategy is to do the same thing that the GLSL lower_offset_arrays
pass does - create 4 separate texture gather ops, one per offset, and
read in the results from each gather's w component to recreate the
desired result.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-16 20:27:37 -05:00
Francisco Jerez
79d08ed3d2 anv: Fix uniform and storage buffer offset alignment limits.
This fixes a regression in a bunch of image store vulkan CTS tests
from commit ad38ba1134, which started
using OWORD block read messages to implement UBO loads.  The reason
for the failure is that we were giving bogus buffer alignment limits
to the application (1B), so the CTS would happily come back with
descriptor sets pointing at not even word-aligned uniform buffer
addresses.

Surprisingly the sampler messages used to fetch pull constants before
that commit were able to cope with the non-texel aligned addresses,
but the dataport messages used to fetch pull constants after that
commit and the ones used to access storage buffers (before and after
the same commit) aren't as permissive with unaligned addresses.

Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-16 14:12:54 -08:00
Thomas Helland
a66818830a nir: Remove nir_array from lower_locals_to_regs
We do nothing but initialize it, add to it, and delete it.
This is a fallout from removing constant initializer support.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-16 12:02:28 -08:00
Bruce Cherniak
79b66ec05e swr: Implement fence attached work queues for deferred deletion.
Work can now be added to fences and triggered by fence completion. This
allows for deferred resource deletion, and other asynchronous tasks.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
2016-12-16 11:29:02 -06:00
Timothy Arceri
3421b3f5a3 nir: Turn imov/fmov of undef into undef
Reverting the previous attempt at this a5502a721f resulted in
the following Vulkan test failing.

dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex

This time we use the num_components from the alu dest rather than
num_inputs to the op to determine the size of the undef.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99100
2016-12-16 20:32:59 +11:00
Eric Engestrom
08fc74663b egl/x11: cleanup init code
No functional change, just rewriting it in an easier-to-understand way.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-12-15 11:48:31 +00:00