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radv/winsys: Make WaitIdle queue aware.

Browse source 
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen 2016-12-17 19:10:35 +01:00
parent d028bd7b55
commit 71dabe1c16
5 changed files with 38 additions and 21 deletions
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10
src/amd/vulkan/radv_device.c
View file

@ -879,7 +879,9 @@ VkResult radv_QueueWaitIdle(
{
RADV_FROM_HANDLE(radv_queue, queue, _queue);
queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
radv_queue_family_to_ring(queue->queue_family_index),
queue->queue_idx);
return VK_SUCCESS;
}
@ -888,7 +890,11 @@ VkResult radv_DeviceWaitIdle(
{
RADV_FROM_HANDLE(radv_device, device, _device);
device->ws->ctx_wait_idle(device->hw_ctx);
for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
for (unsigned q = 0; q < device->queue_count[i]; q++) {
radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
}
}
return VK_SUCCESS;
}

3
src/amd/vulkan/radv_radeon_winsys.h
View file

@ -286,7 +286,8 @@ struct radeon_winsys {
struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx);
bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
enum ring_type ring_type, int ring_index);
struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
enum ring_type ring_type);

34
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -501,6 +501,14 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
return r;
}
static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
struct amdgpu_cs_request *request)
{
radv_amdgpu_request_to_fence(ctx,
&ctx->last_submission[request->ip_type][request->ring],
request);
}
static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
@ -560,7 +568,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
ctx->last_seq_no = request.seq_no;
radv_assign_last_submit(ctx, &request);
return r;
}
@ -625,7 +633,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
ctx->last_seq_no = request.seq_no;
radv_assign_last_submit(ctx, &request);
return 0;
}
@ -715,7 +723,9 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
}
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
ctx->last_seq_no = request.seq_no;
radv_assign_last_submit(ctx, &request);
return 0;
}
@ -765,22 +775,16 @@ static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
FREE(ctx);
}
static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx)
static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
enum ring_type ring_type, int ring_index)
{
struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
int ip_type = ring_to_hw_ip(ring_type);
if (ctx->last_seq_no) {
if (ctx->last_submission[ip_type][ring_index].fence) {
uint32_t expired;
struct amdgpu_cs_fence fence;
fence.context = ctx->ctx;
fence.ip_type = AMDGPU_HW_IP_GFX;
fence.ip_instance = 0;
fence.ring = 0;
fence.fence = ctx->last_seq_no;
int ret = amdgpu_cs_query_fence_status(&fence, 1000000000ull, 0,
&expired);
int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index],
1000000000ull, 0, &expired);
if (ret || !expired)
return false;

6
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
View file

@ -38,10 +38,14 @@
#include "radv_radeon_winsys.h"
#include "radv_amdgpu_winsys.h"
enum {
MAX_RINGS_PER_TYPE = 8
};
struct radv_amdgpu_ctx {
struct radv_amdgpu_winsys *ws;
amdgpu_context_handle ctx;
uint64_t last_seq_no;
struct amdgpu_cs_fence last_submission[AMDGPU_HW_IP_DMA + 1][MAX_RINGS_PER_TYPE];
};
static inline struct radv_amdgpu_ctx *

6
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
View file

@ -301,8 +301,10 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
ws->info.has_virtual_memory = TRUE;
ws->info.sdma_rings = util_bitcount(dma.available_rings);
ws->info.compute_rings = util_bitcount(compute.available_rings);
ws->info.sdma_rings = MIN2(util_bitcount(dma.available_rings),
MAX_RINGS_PER_TYPE);
ws->info.compute_rings = MIN2(util_bitcount(compute.available_rings),
MAX_RINGS_PER_TYPE);
/* Get the number of good compute units. */
ws->info.num_good_compute_units = 0;