Commit graph

32509 commits

Author SHA1 Message Date
Dylan Baker
6a9ad20b7c meson: build llvmpipe
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
de24d61765 meson: build softpipe
This doesn't include llvmpipe.

v2: - Fix inconsistent use of with_gallium_swrast and
      with_gallium_softpipe.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
813b4b09f9 meson: build nouveau (gallium) driver
Tested with a GK107.

v2: - Add target for nouveau standalone compiler. This target is not
      built by default.
v3: - Add nouveau to list of drivers built by default

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
b154b44ae3 meson: build radeonsi gallium driver
This hooks up the bits necessary to build gallium dri drivers, with
radeonSI as the first example driver. This isn't tested yet.

v4: - drop radeonsi generated header from sources.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
66c94b9313 meson: build gallium winsys for dri, null, and wrapper
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
66f97f6640 meson: build radeonsi
This builds the radeonsi (and radeon) window system bits and gallium
driver bits.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
f3d03a2cf7 meson: Build gallium dri state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
4d701ee969 meson: build gallium helper drivers
This builds ddebug, noop, rbug, and trace drivers.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
2017-10-16 16:32:43 -07:00
Dylan Baker
d451a11b21 meson: Build gallium pipe-loader
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
2017-10-16 16:32:43 -07:00
Dylan Baker
b1b65397d0 meson: Build gallium auxiliary
v2: - guard gallivm files with "with_llvm" instead of "dep_llvm.found()"

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
2017-10-16 16:32:43 -07:00
Eric Engestrom
b05820621d svga: format the version string like the rest of mesa
All 4 other version strings do it like this.
((Also, double parentheses just look confusing))

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-16 18:52:41 +01:00
Brian Paul
4542a63254 svga: fix format_conversion_table breakage
The new A1B5G5R5_UNORM, X1B5G5R5_UNORM formats were added in the
wrong place in commit ef874ee450.

Fixes: ef874ee450 "gallium: Add support for 5551 with the 1-bit field in the low bit."

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-16 10:58:02 -06:00
Ilia Mirkin
790b5c4a38 a2xx: add support for a few 16-bit color rendering formats
The rest should be possible too, just needs some additional
investigation. Passes fbo-*-formats piglit tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-15 12:09:21 -04:00
Wladimir J. van der Laan
d3af7f5153 freedreno/a20x: Enable rendering to RGBA/RGBX
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-10-15 12:09:14 -04:00
Wladimir J. van der Laan
c10eeb454d freedreno/a20x: Fix rendering to BGRX
Make sure that BGRX rendering is swapped the correct way around.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-10-15 12:09:03 -04:00
Lucas Stach
4daee6733f etnaviv: rework TS enable to be a derived state
Draw operations should not use the TS if the TS buffer content is invalid,
as this leads to wrong rendering or even GPU hangs. As the TS valid status
can change between draws (clear operations changing it to valid, blits using
the RS to the color or ZS buffer changing it to invalid), the TS_MEM_CONFIG
must be updated before each draw if the status has changed.

This fixes the remaining TS related piglit failures (regressions of a
standard run against a piglit run with TS completely disabled).

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-14 16:40:08 +02:00
Lucas Stach
34360ac6ed etnaviv: skip unused vertex attributes when assigning VS inputs
When not all of the vertex attributes are actually used in the shader,
we end up with some inputs without an assigned reg. Those are marked
as invalid and must be skipped when assigning the inputs, as those would
overwrite other valid inputs otherwise.

Fixes piglit drawpixels and a bunch of other tests using the st_draw path.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-10-14 16:39:46 +02:00
Mark Thompson
e7f24859ca st/dri: Add definitions to allow importing 16-bit surfaces
Necessary to support P010/P016 surfaces for video.

Signed-off-by: Mark Thompson <sw@jkqxz.net>
Acked-by: Leo Liu <leo.liu@amd.com>
2017-10-13 08:11:47 -04:00
Eric Anholt
dbf9e4fbf8 broadcom/vc5: Remove the u_resource_vtbl usage.
Like for vc4, this was just a wasted indirection.
2017-10-12 12:44:27 -07:00
Marek Olšák
f536f45250 radeonsi: implement sync_file import/export
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:07:48 +02:00
Marek Olšák
162502370c winsys/amdgpu: implement sync_file import/export
syncobj is used internally for interactions with command submission.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:07:41 +02:00
Marek Olšák
11adea4b24 ac: add radeon_info::has_sync_file
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 21:04:56 +02:00
Marek Olšák
255573996c st/dri: implement __DRIimageExtension::validateUsage properly
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Marek Olšák
07fdc0a09c gallium: add pipe_screen::check_resource_capability
This is optional (and no CAP).

Implemented by radeonsi, ddebug, rbug, trace.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Wladimir J. van der Laan
78ade65956 etnaviv: Do GC3000 resolve-in-place when possible
If an RS blit is done with source exactly the same as destination, and
the hardware supports this, do an in-place resolve. This only fills in
tiles that have not been rendered to using information from the TS.

This is the same as the blob does and potentially saves significant
bandwidth when doing i.MX6qp scanout using PRE, and when rendering to
textures (though here using sampler TS would be even better).

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-10-12 16:03:26 +02:00
Nicolai Hähnle
bc2d874101 radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM
Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-12 08:42:55 +02:00
Nicolai Hähnle
9f55da130e gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formats
This is a left-over from my version of adding the new format
after rebasing on Eric's version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-10-12 08:42:55 +02:00
Tim Rowley
e484805352 swr: simd16 shaders work in progress
Start building vertex shaders as simd16.

Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-10-11 14:35:23 -05:00
Tim Rowley
9cad9cbaf8 gallium: allow 512-bit vectors
Increase the max allowed vector size from 256 to 512.

No piglit llvmpipe regressions running on avx2.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-10-11 14:34:31 -05:00
Ilia Mirkin
b20bccbcac nv50,nvc0: fix push hint logic in presence of a start offset
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.

This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.

Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-11 08:18:16 -04:00
Rob Herring
e5e93c727f Android: fix build break from r600/radeon split
Commit 06bfb2d28f ("r600: fork and import gallium/radeon") broke the
Android build:

external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~~

Update the Android makefiles so that drivers/radeon is only built when
radeonsi (and therefore LLVM) is enabled.

Fixes: 06bfb2d28f (r600: fork and import gallium/radeon)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-10-10 21:37:19 -05:00
Dave Airlie
96e85709df r600: cleanup llvm ir target selection.
Only r600 target used now for compute IR.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:40:04 +10:00
Dave Airlie
ce0ee31890 r600: drop tc_L2_dirty bit, this was SI only.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:39:32 +10:00
Dave Airlie
80bbdb1483 radeonsi: lower ffma in nir to mad.
This lowers ffma to a * b + c.

This seems like it should keep Marek happiest, so
we'd never get to the fma instruction emission code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-11 07:33:32 +10:00
Eric Anholt
2687183a34 broadcom/vc5: Fix handling of 5551 textures using the new gallium format.
Like vc4, we have the alpha in the low bit.  Fixes a bunch of piglit
texwrap failures.
2017-10-10 11:42:06 -07:00
Eric Anholt
f4b5158874 broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state. 2017-10-10 11:42:06 -07:00
Eric Anholt
ae9a56db6a braodcom/vc5: Set up clear color for higher-bpp formats.
Fixes arb_color_buffer_float-clear
2017-10-10 11:42:06 -07:00
Eric Anholt
c0561808c0 broadcom/vc5: Set up per-MRT clear colors.
Fixes fbo-mrt-alphatest.
2017-10-10 11:42:06 -07:00
Eric Anholt
5208d2889e broadcom/vc5: Fix blendfactor zero handling.
I cut the line out to move it up to the top, when putting "0" in the
switch made the compiler complain that that wasn't a valid enum.
2017-10-10 11:42:06 -07:00
Eric Anholt
4b7de2a360 broadcom/vc5: Add support for f32 render targets.
The TLB write code is getting ugly and needs a refactoring (that will
hopefully handle TLBU uniform coalescing as well).
2017-10-10 11:42:06 -07:00
Eric Anholt
f2e6e1bbc3 broadcom/vc5: Fix color masks for non-independent blending.
This gets fbo-mrt-alphatest working except for the second RT's clear color.
2017-10-10 11:42:06 -07:00
Eric Anholt
476db7e66b broadcom/vc5: Make the BCL's number of render targets setup match the RCL. 2017-10-10 11:42:06 -07:00
Eric Anholt
8b4c00a7b2 braodcom/vc5: Fix tile size setup for MRTs.
We need to divide the TLB in two for the 2nd color buffer, and again if
the 3rd or 4th are present.
2017-10-10 11:42:06 -07:00
Eric Anholt
dc25a83a7a broadcom/vc5: Start hooking up multiple render targets support.
We now emit as many TLB color writes as there are color buffers.
2017-10-10 11:42:05 -07:00
Eric Anholt
f0ee7d6ba8 broadcom/vc5: Add support for GL_EXT_provoking_vertex.
The bit was missing from the spec, but it's there in the simulator.  Fixes
the piglit clipflat test.
2017-10-10 11:42:05 -07:00
Eric Anholt
f4133865d1 braodcom/vc5: Find the actual first TF output for our TF spec.
This doesn't yet support PSIZ, but gets us at least some of TF working.
2017-10-10 11:42:05 -07:00
Eric Anholt
bd94f6821e broadcom/vc5: Fix translation of transform feedback's output_register field.
It's a NIR driver_location, not a slot offset.
2017-10-10 11:42:05 -07:00
Eric Anholt
d8bc9c71df broadcom/vc5: Mark our primitives as needing TF processing.
The TF enable state appears to stick around until the next TF enable
packet is sent, so we only want to request TF when the shader is using it.
2017-10-10 11:42:05 -07:00
Eric Anholt
28105560f7 broadcom/vc5: Fix setup of TF dword output count.
I missed the "- 1" when reading the spec.
2017-10-10 11:42:05 -07:00
Eric Anholt
3ac8a2a4ba broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup. 2017-10-10 11:42:05 -07:00