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r600: drop tc_L2_dirty bit, this was SI only.

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-10-10 06:27:10 +10:00
parent 80bbdb1483
commit ce0ee31890
3 changed files with 0 additions and 15 deletions
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2
src/gallium/drivers/r600/r600_buffer_common.c
View file

@ -234,7 +234,6 @@ bool r600_alloc_resource(struct r600_common_screen *rscreen,
pb_reference(&old_buf, NULL);
util_range_set_empty(&res->valid_buffer_range);
res->TC_L2_dirty = false;
/* Print debug information. */
if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
@ -607,7 +606,6 @@ r600_alloc_buffer_struct(struct pipe_screen *screen,
rbuffer->buf = NULL;
rbuffer->bind_history = 0;
rbuffer->TC_L2_dirty = false;
util_range_init(&rbuffer->valid_buffer_range);
return rbuffer;
}

12
src/gallium/drivers/r600/r600_pipe_common.h
View file

@ -165,18 +165,6 @@ struct r600_resource {
*/
struct util_range valid_buffer_range;
/* For buffers only. This indicates that a write operation has been
* performed by TC L2, but the cache hasn't been flushed.
* Any hw block which doesn't use or bypasses TC L2 should check this
* flag and flush the cache before using the buffer.
*
* For example, TC L2 must be flushed if a buffer which has been
* modified by a shader store instruction is about to be used as
* an index buffer. The reason is that VGT DMA index fetching doesn't
* use TC L2.
*/
bool TC_L2_dirty;
/* Whether the resource has been exported via resource_get_handle. */
unsigned external_usage; /* PIPE_HANDLE_USAGE_* */

1
src/gallium/drivers/r600/r600_query.c
View file

@ -1739,7 +1739,6 @@ static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
ssbo[2].buffer_offset = offset;
ssbo[2].buffer_size = 8;
((struct r600_resource *)resource)->TC_L2_dirty = true;
}
rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);