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braodcom/vc5: Set up clear color for higher-bpp formats.

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Fixes arb_color_buffer_float-clear
This commit is contained in:
Eric Anholt 2017-10-05 15:50:59 -07:00
parent c0561808c0
commit ae9a56db6a
2 changed files with 45 additions and 4 deletions
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20
src/broadcom/cle/v3d_packet_v33.xml
View file

@ -580,6 +580,26 @@
<field name="sub-id" size="4" start="0" type="uint" default="4"/>
</packet>
<packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part2)" cl="R">
<!-- Express this as a 56-bit field? -->
<field name="Clear Color mid-high 24 bits" size="24" start="40" type="uint"/>
<field name="Clear Color mid-low 32 bits" size="32" start="8" type="uint"/>
<field name="Render Target number" size="4" start="4" type="uint"/>
<field name="sub-id" size="4" start="0" type="uint" default="5"/>
</packet>
<packet code="121" name="Tile Rendering Mode Configuration (Clear Colors Part3)" cl="R">
<field name="pad" size="11" start="53" type="uint"/>
<field name="UIF padded height in UIF blocks" size="13" start="40" type="uint"/>
<!-- image height is for Y flipping -->
<field name="Raster Row Stride or Image Height in Pixels" size="16" start="24" type="uint"/>
<field name="Clear Color high 16 bits" size="16" start="8" type="uint"/>
<field name="Render Target number" size="4" start="4" type="uint"/>
<field name="sub-id" size="4" start="0" type="uint" default="6"/>
</packet>
<packet code="124" name="Tile Coordinates">
<field name="tile row number" size="12" start="12" type="uint"/>
<field name="tile column number" size="12" start="0" type="uint"/>

29
src/gallium/drivers/vc5/vc5_rcl.c
View file

@ -130,11 +130,11 @@ vc5_emit_rcl(struct vc5_job *job)
}
for (int i = 0; i < nr_cbufs; i++) {
cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
struct pipe_surface *psurf = job->cbufs[i];
if (!psurf)
continue;
struct pipe_surface *psurf = job->cbufs[i];
if (!psurf)
continue;
cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
struct vc5_surface *surf = vc5_surface(psurf);
struct vc5_resource *rsc = vc5_resource(psurf->texture);
rt.address = cl_address(rsc->bo, surf->offset);
@ -154,6 +154,27 @@ vc5_emit_rcl(struct vc5_job *job)
clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
clear.render_target_number = i;
};
if (util_format_get_blocksize(psurf->format) > 7) {
cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
clear) {
clear.clear_color_mid_low_32_bits =
((job->clear_color[i][1] >> 24) |
(job->clear_color[i][2] << 8));
clear.clear_color_mid_high_24_bits =
((job->clear_color[i][2] >> 24) |
((job->clear_color[i][3] & 0xffff) << 8));
clear.render_target_number = i;
};
}
if (util_format_get_blocksize(psurf->format) > 14) {
cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
clear) {
clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
clear.render_target_number = i;
};
}
}
/* TODO: Don't bother emitting if we don't load/clear Z/S. */