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119 commits

Author SHA1 Message Date
Timur Kristóf
3223650bad radv: Reuse TCS offchip layout between TCS and TES. 
Using the same SGPR bitfield in TCS and TES will simplify driver
code and make RADV consistent with RadeonSI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
 2024-04-02 16:54:09 +00:00
Timur Kristóf
2a76f821af radv: Change number of patches in TCS offchip layout to match RadeonSI. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
 2024-04-02 16:54:09 +00:00
Timur Kristóf
820370ca08 radv: Change input patch size in TCS offchip layout to match RadeonSI. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
 2024-04-02 16:54:08 +00:00
Timur Kristóf
d116272689 radv: Add number of LS and HS outputs to tcs_offchip_layout. 
And calculate the LS-HS per-vertex stride in shader code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
 2024-04-02 16:54:08 +00:00
Samuel Pitoiset
b35b2718be radv: remove radv_physical_device::instance 
Get the instance object using the base object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
 2024-04-01 16:35:09 +00:00
Samuel Pitoiset
e2c29c9bb6 radv: remove radv_device::instance 
Use the physical device to access the instance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
 2024-04-01 16:35:09 +00:00
Samuel Pitoiset
896c9cf486 radv: remove radv_device::physical_device 
Get the logical device object using the base object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
 2024-04-01 16:35:09 +00:00
Samuel Pitoiset
310597cab6 radv: rename radv_physical_device::rad_info to info 
The extra rad_ prefix isn't necessary and it's longer to type.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
 2024-04-01 16:35:09 +00:00
Samuel Pitoiset
2686cd59df radv: rename radeon_info variables to gpu_info everywhere 
Sometimes we might have other info struct, so renaming to gpu_info
removes the confusion.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28500>
 2024-04-01 16:35:09 +00:00
Timur Kristóf
96ee0d6711 ac/nir/tess: Remove dead code that was meant for epilogs. 
We no longer need to emit store_output intrinsics at the
end of the shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:51 +01:00
Timur Kristóf
e421923692 radv: Completely delete TCS epilogs. 
TCS epilogs are not needed anymore because the TCS can implement
dynamic states by itself now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
 2024-03-28 23:44:03 +00:00
Timur Kristóf
508f293b14 ac/nir/tess: Emit tess factor stores based on new intrinsics. 
This allows the TCS to read the primitive mode and whether
TES reads the tess factors, from an SGPR arg, which lets it
decide how to store them at runtime.

For linked shaders, the conditions will be constant and
NIR optimizations can delete the dead CF.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
 2024-03-28 23:44:03 +00:00
Timur Kristóf
315cacddbd radv: Implement new tess intrinsics. 
For linked shaders, the information is available as constant,
while for unlinked shaders, the info is in a SGPR arg.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
 2024-03-28 23:44:03 +00:00
Timur Kristóf
53ab164234 radv: Always pass tess factors to epilogs in registers. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28371>
 2024-03-28 09:41:08 +00:00
Timur Kristóf
96998b448c ac/nir/tess: Emit tess factor output independently of whether it can be passed by registers. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28371>
 2024-03-28 09:41:08 +00:00
Konstantin Seurer
6095b70f85 radv/rt: Use 32-bit offsets for load_sbt_entry 
Totals from 82 (18.06% of 454) affected shaders:
MaxWaves: 820 -> 821 (+0.12%)
Instrs: 2765694 -> 2766338 (+0.02%); split: -0.08%, +0.10%
CodeSize: 14751988 -> 14735464 (-0.11%); split: -0.13%, +0.01%
VGPRs: 8464 -> 8448 (-0.19%)
SpillSGPRs: 454 -> 512 (+12.78%)
Latency: 19368679 -> 19344967 (-0.12%); split: -0.21%, +0.09%
InvThroughput: 5354427 -> 5346317 (-0.15%); split: -0.24%, +0.08%
VClause: 100183 -> 100331 (+0.15%); split: -0.02%, +0.17%
SClause: 66584 -> 66590 (+0.01%); split: -0.02%, +0.03%
Copies: 237008 -> 238684 (+0.71%); split: -0.53%, +1.23%
Branches: 113344 -> 113386 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 6141 -> 6194 (+0.86%)
PreVGPRs: 7916 -> 7880 (-0.45%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27725>
 2024-03-19 17:03:28 +00:00
Timur Kristóf
8f3cc3cb29 radv: Use mapped driver locations for determining I/O strides. 
This will allow us to more accurately determine the
input and output strides, because the I/O locations mapped
by RADV don't match the locations in NIR.
As a result, ESO will use less LDS.

It also fixes the per-patch output stride of tess control
shaders, because previously we omitted tess factors from them.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
 2024-03-19 15:01:19 +00:00
Alyssa Rosenzweig
a6123a80da nir/opt_shrink_vectors: shrink some intrinsics from start 
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.

v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.

RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)

AGX:

total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)

total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)

total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)

total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)

total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
 2024-03-12 18:17:17 +00:00
Konstantin Seurer
0e8f2eca9e radv/rt: Inline constant information about ray flags 
Totals from 4 (1.06% of 379) affected shaders:
Instrs: 2868 -> 2588 (-9.76%)
CodeSize: 15184 -> 13544 (-10.80%)
Latency: 69280 -> 86922 (+25.46%)
InvThroughput: 11546 -> 14486 (+25.46%)
Copies: 680 -> 592 (-12.94%)
Branches: 148 -> 128 (-13.51%)
PreSGPRs: 216 -> 172 (-20.37%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
 2024-03-07 20:07:07 +00:00
Konstantin Seurer
b4735a944a radv/rt: Inline constant trace_ray srcs into the traversal shader 
Totals from 4 (1.06% of 379) affected shaders:
Instrs: 2864 -> 2868 (+0.14%)
CodeSize: 15232 -> 15184 (-0.32%)
Latency: 69074 -> 69280 (+0.30%)
InvThroughput: 11512 -> 11546 (+0.30%)
VClause: 124 -> 116 (-6.45%)
Copies: 676 -> 680 (+0.59%)
PreVGPRs: 316 -> 312 (-1.27%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
 2024-03-07 20:07:07 +00:00
Konstantin Seurer
843d19a995 radv/rt: Avoid passing unused data to the next stage 
We can gather the args used by all other stages and use that to optimize
the traversal shader.

Totals from 4 (1.06% of 379) affected shaders:
Instrs: 2912 -> 2864 (-1.65%)
CodeSize: 15424 -> 15232 (-1.24%)
Latency: 69342 -> 69074 (-0.39%)
InvThroughput: 11558 -> 11512 (-0.40%)
Copies: 712 -> 676 (-5.06%)
Branches: 152 -> 148 (-2.63%)
PreVGPRs: 324 -> 316 (-2.47%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
 2024-03-07 20:07:07 +00:00
Konstantin Seurer
348d13f06e radv/rt: Fixup constant args 
They are fixed up automatically right now, which will change in the next
patch.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
 2024-03-07 20:07:07 +00:00
Timur Kristóf
a6f270c160 radv: Lower mesh shader draw ID to zero when they have a task shader. 
This prevents potential app bugs causing GPU hangs and other issues.
Note that the draw ID is undefined in mesh shaders when also
using a task shader.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27879>
 2024-03-07 17:07:24 +00:00
Friedrich Vock
7792ee1c15 radv/rt: Fix frontface culling with emulated RT 
We need to preserve the divisor's sign for front/backface detection to
work correctly.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28034>
 2024-03-07 10:34:52 +00:00
Samuel Pitoiset
85d682b318 radv: lower lds_ngg_{gs_out_vertex_base,_scratch_base} with ESO 
These values will be computed at draw time when both shaders are known
in case it's VS+GS or TES+GS as NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27724>
 2024-03-01 14:45:05 +00:00
Samuel Pitoiset
482dbacdeb radv/nir: lower esgs_vertex_stride for GS compiled separately on GFX9+ 
The ESGS vertex stride would be emitted at draw time using the number
of VS/TES outputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27388>
 2024-02-08 13:33:34 +00:00
Konstantin Seurer
b10ee44308 radv/rra: Implement ahit/isec counters 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25548>
 2024-02-03 12:59:47 +01:00
Konstantin Seurer
767f628079 radv/rra: Dump basic ray history tokens 
This only dumps the begin tokens. Tokens are written to a buffer
containing a 12 byte header at the beginning.

We use an intermediate format for the ray history tokens because the RRA
format is very inefficient.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25548>
 2024-02-03 12:59:47 +01:00
Konstantin Seurer
c925b6019d radv/rt: Lower ray payloads like hit attribs 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27051>
 2024-02-02 16:36:15 +00:00
Konstantin Seurer
f27a973283 radv/rt: Use doubles inside intersect_ray_amd_software_tri 
Increasing precision lets us avoid duplicate hits on shared edges. The
previous biasing WA made a bunch of tests fail.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27243>
 2024-01-30 10:26:43 +01:00
Tatsuyuki Ishi
70b0c5909b radv: Add radv_spirv_to_nir_options that summarize early gfx states. 
radv_shader_spirv_to_nir now takes a more minimal struct instead of gfx
states. This struct will be used for NIR cache hashing in the future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26696>
 2024-01-26 11:46:18 +00:00
Samuel Pitoiset
df3fbe3b33 radv: promote VK_EXT_line_rasterization to KHR 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27262>
 2024-01-26 10:00:48 +00:00
Samuel Pitoiset
853298edb1 radv/rt: cleanup radv_parse_rt_stage() 
To avoid calling radv_pipeline_stage_init() twice.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27036>
 2024-01-17 07:25:49 +00:00
Samuel Pitoiset
082c524f86 radv: pass radv_shader_stage_key to radv_pipeline_stage_init() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27036>
 2024-01-17 07:25:49 +00:00
Samuel Pitoiset
b555f9451c radv: introduce radv_graphics_state_key 
This struct only contains graphics related state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
f2f87d0872 radv: re-organize radv_pipeline_key 
Rename and regroup fields per PSO basically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
fb80421a62 radv: stop passing the pipeline key when compiling compute/rt shaders 
The pipeline key now essentially contains graphics state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
6e7018e74d radv: remove unused lower_rt_instruction_monolithic_state::key 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
28e330c245 radv: add radv_shader_stage_key to radv_shader_stage 
For storing the per-stage key information like robustness etc. This
will fit well with ESO as well.

For pipelines, they are copied from radv_pipeline_key, similarly to
the radv_pipeline_layout/radv_shader_layout pair.

This will also allow us to kill radv_pipeline_key for compute/rt
pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
138ce72860 radv/nir: remove useless struct for nir_shader typedef 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
18349692d0 radv/nir: pass radv_shader_stage to some radv_nir_xxx() functions 
Instead of passing separate parameters for args, layout, info etc.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
 2024-01-15 11:49:04 +00:00
Samuel Pitoiset
59c05b9cfa Revert "radv/rt: Lower ray payloads to registers" 
This causes GPU hangs with vkd3d-proton in CI.

This reverts commit 658ce711d5.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26983>
 2024-01-10 18:12:55 +00:00
Samuel Pitoiset
58d2a78dba radv: move dri options to radv_instance::drirc 
To make it clearer that such an option is a per-application option.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26946>
 2024-01-10 10:07:40 +00:00
Konstantin Seurer
658ce711d5 radv/rt: Lower ray payloads to registers 
This should allow for cross stage optimizations and it reduces latency
caused by scratch access.

Totals from 44 (9.69% of 454) affected shaders:
MaxWaves: 432 -> 436 (+0.93%)
Instrs: 2740662 -> 1610327 (-41.24%); split: -41.24%, +0.00%
CodeSize: 14616932 -> 8573620 (-41.34%)
VGPRs: 4880 -> 4816 (-1.31%)
SpillSGPRs: 464 -> 294 (-36.64%)
Latency: 18548886 -> 11465281 (-38.19%); split: -38.19%, +0.00%
InvThroughput: 5195964 -> 3066729 (-40.98%); split: -40.98%, +0.00%
VClause: 99672 -> 55611 (-44.21%)
SClause: 65827 -> 38697 (-41.21%)
Copies: 231231 -> 137676 (-40.46%); split: -40.47%, +0.01%
Branches: 111379 -> 65865 (-40.86%); split: -40.87%, +0.00%
PreSGPRs: 3854 -> 3812 (-1.09%); split: -1.19%, +0.10%
PreVGPRs: 4518 -> 4439 (-1.75%); split: -1.84%, +0.09%

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26431>
 2024-01-09 13:02:11 +00:00
Konstantin Seurer
c511b8968a radv: Implement VK_KHR_ray_tracing_position_fetch 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26895>
 2024-01-05 18:20:20 +00:00
Samuel Pitoiset
f30fa9dec8 radv: move radv_rt_{common,shader} files to nir/ 
These files contains NIR lowering code for RT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26851>
 2024-01-03 09:40:29 +00:00
Bas Nieuwenhuizen
07ad6fd34a radv: Use correct writemask for cooperative matrix ordering. 
Not expecting this to actually fix anything externally visible,
but reduces some invalid usage when the resulting vector is
not 16 elements long (e.g. the C/result matrix).

Fixes: 9df4703fbb ("radv: Add cooperative matrix lowering.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26768>
 2023-12-20 11:02:30 +00:00
Rhys Perry
4d2a3b9573 radv: add radv_disable_trunc_coord option 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911>
 2023-11-17 15:15:27 +00:00
Konstantin Seurer
ba8d3afa56 radv/nir: Handle boolean hit attribs 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24271>
 2023-11-02 15:48:36 +00:00
Konstantin Seurer
3a69424e09 radv/nir: Add radv_nir_lower_hit_attrib_derefs 
Move out the pass so it can be unit tested.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24271>
 2023-11-02 15:48:36 +00:00