Commit graph

174560 commits

Author SHA1 Message Date
Nanley Chery
2d7fc325d6 crocus: Delete modifier with aux code
Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
5568970d63 iris: Reduce accesses of mod_info->aux_usage
This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
569f80f2df anv: Reduce accesses of isl_mod_info->aux_usage
This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
f2dab434d8 anv: Handle explicit surface layout of DG2_RC_CCS
We're going to enable the DG2 modifier. Account for the reduced plane
count that exists with it.

Also add an assert to make it clearer that the aux in use is CCS.
Otherwise, it may not be obvious because of the generic compression
names being used here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
47565d31e1 intel: Add and use isl_drm_modifier_get_plane_count
We're going to enable the DG2_RC_CCS modifier in anv. Add and use this
function to prepare for the new plane count that comes with that
modifier.

iris is left alone for now because it supports more modifiers than
isl_drm_modifier_get_score is aware of.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
e50af52e3d anv: Don't support ASTC images with modifiers
Before this change, anv_get_image_format_features2 reported support for
ASTC formats with any modifier (even those not supported by anv). But,
we didn't intend to support that compressed image format with modifiers.

With this change, the format feature function reports no support for
modifiers on ASTC-formatted images.

This prevents the next patch from causing assertion failures due to
unsupported modifiers.

Fixes: 355f318843 ("anv: Allow transfer-only linear ASTC images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
c042eb653d iris: Remap DRM_FORMAT_MOD_INVALID more often during import
We'd eventually like to use an ISL helper that doesn't support
DRM_FORMAT_MOD_INVALID. Prepare for this by replacing the invalid value
with the modifier associated with the BO's tiling in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Rohan Garg
ba071ee81c anv: use the correct GFX_VERx10 macro for WA
Fixes: 60b0d2c2cb ("add required invalidate/flush for Wa_14014427904")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>
2023-07-20 20:25:12 +00:00
Rohan Garg
097f3b4a98 anv: use the WA infrastructure where possible when generating state
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>
2023-07-20 20:25:12 +00:00
Marek Olšák
54f18b5000 radeonsi: fix a CDNA regression breaking compute
reported internally

Fixes: 315231b5a5 - radeonsi: eliminate redundant compute SH register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24169>
2023-07-20 18:42:56 +00:00
Christian Gmeiner
019e5cbd39 nir/print: print instr pass_flags
From time to time it can be helpful to "see" the pass_flags.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24234>
2023-07-20 18:03:47 +00:00
Yiwei Zhang
a89752d630 turnip: flush cache for dstBuffer in vkCmdCopyQueryPoolResults
There can be other writes to the dstBuffer gated by proper barriers
beforehand.

TEST=dEQP-VK.pipeline.*.timestamp.* with Venus on Turnip

Fixes: 487aa807bd ("tu: Rewrite flushing to use barriers")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24245>
2023-07-20 16:28:17 +00:00
Alyssa Rosenzweig
950a0b6a63 ir2: Switch to nir_legacy
Addresses a2xx portion of #9051.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24118>
2023-07-20 15:50:54 +00:00
Alyssa Rosenzweig
ad214fcaf7 asahi: Advertise Z16_UNORM
This works (on the downstream kernel, anyway).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0197d46b34 asahi: Execute preambles for background programs
This will be useful when spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
9fbe2fdea0 asahi: Offset clear colour uniform by 4
Frees up u0_u1 for a bindless base address which will make render target
spilling easier to implement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0597c100cc asahi: Ignore spilled render targets for background load
Nothing to reload.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
ef5a5e170f asahi: Permit meta shaders to use preambles
Preambles are occassionally useful with background programs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
5f167c9f72 asahi: Lower multisample image stores
These will be used for spilling multisampled render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
ff16397912 asahi: Lower tilebuffer access for spilled RTs
Conceptually similar, we just don't have the tilebuffer available this time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
66e8afe7c9 asahi: Extract some tilebuffer lowering code
In prep for spilling. No functional change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
46b5406483 asahi: Ignore spilled render targets with partial renders
Partial renders exist to the spill the tilebuffer to memory, there's nothing to
do if it's already spilled (and would just waste memory bandwidth and create a
feedback loop).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
dc38f24de3 asahi: Ignore spilled render targets in EOT shaders
Regardless whether we implement Apple-style eMRT or something simpler, the EOT
shader isn't involved here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
73fb1543fd asahi: Do not support masking with spilled RTs
Extra complexity for this interaction, not worth it until we have an actual use
case IMHO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
fa0e671b7b asahi: Add agx_tilebuffer_spills query
We can skip various work in the driver if we're not spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
6bc42054d1 asahi: Introduce concept of spilled render targets
To accommodate framebuffers which exceed tilebuffer limits, we'll need to spill
render targets to main memory. In effect, we need to emulate an immediate-mode
renderer for some render targets. This decision is made on a per-render target
basis. In our tilebuffer layout calculation, rather than asserting that all
render targets fit, introduce a notion of spilling.

This doesn't actually implement spilling -- it just pushes the assert failure
down to the users. But it's progress.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
17e10499b9 asahi: Extract sampler_view_for_surface
We'll reuse this logic for the spilled RT case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
10fc9e3d59 agx: Plumb in coverage mask
This is internally used by the hardware when writing to the tilebuffer. We need
to use it externally to spill multisample render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
56bb3dcc21 agx: Require tag writes with side effects
Otherwise the fragment shader might be skipped entirely. (Possibly this is the
wrong approach to this though...)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
46bb0037ce agx: Add simple image fencing pass
Minimum needed to pass CTS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
7ed2596fe7 agx: Implement fence_*_to_tex_agx intrinsics
We need these fencing intrinsics because our image caches aren't coherent with
memory. Furthermore, we need some sync intrinsics for imageblocks (which are
spicy images). These are a stub of what the final fragment shader interlock
implementation will look like, or what a real Metal-grade imageblock
implementation needs, but this is good enough for handling the sync requirements
with spilled render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
c1afe26be6 agx: Don't emit silly barriers
Trust in the scoped_barrier.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
b618ba9330 agx: Emit global memory barriers for images
This is part of image atomics, since those go through the regular memory path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
93f26abe49 agx: Implement image_load
Texture loads can be reordered freely but image loads can't be (since there
could be writes). Implement image_load natively to avoid subtle problems with
CSE and scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
e5f37ac5cb agx: Extract texture write mask handling
image_load will share the logic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
34c759467c agx: Add image_load opcode
This is equivalent to texture_load but cannot be reordered, since it might be
writeable.

It also sets bit 43. This needs more investigation, but it fixes
KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs. Some sort of cache
control bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
02b1ddeca6 asahi,agx: Fix txf sampler
Bizarrely, the clamps/wrap modes are respected so we need to set them
appropriately for correct out-of-bounds behaviour (returning all zero). That in
turn means we can't use whatever sampler is already there, instead we need to
allocate a dedicated sampler just for txf. Good news is we have an extra sampler
state register available for the purpose.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
1106e2499e agx: Lower buffer images
Similar to buffer reads, we need to implement buffer images as 2D images with
fixed width and some lowering code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
15915f021a agx: Lower image atomics
Lower image atomics to texel address loads, and lower texel address loads to
arithmetic and descriptor reads. This implements image atomics.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
c09089025d agx: Extract texture_descriptor_ptr_for_* helpers
For implementing image_texel_address, when there's no point in creating an
internal texture instruction just to lower immediately.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
a43141f3b5 agx: Extract coords_for_buffer_texture helper
The mapping of 1D -> 2D coordinates for indexing into buffer textures (lowered
to fixed-width 2D images) will be shared between both texture load and image
store code paths, so pull it out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
e2cfd2a228 agx: Add interleave opcode
We'll use it for texture atomics.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
a6ed776a13 agx: Handle early_fragment_tests
Simply doing nothing fixes
dEQP-GLES31.functional.image_load_store.early_fragment_tests.*. However, we need
to actually insert the sample_mask instruction to make sure the shader runs at
all (I think), doing that fixes:

   KHR-GLES31.core.shader_image_load_store.basic-glsl-earlyFragTests

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
76641762ce agx: Implement image barriers
Or cache flushes or whatever these actually are. Probably could be optimized
once we understand what the 4 individual instructions are actually doing. Fixes
dEQP-GLES31.functional.image_load_store.2d.qualifiers.*.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
ad456a683c agx: Wait for outstanding stores before barriers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
5b3635a197 agx: Handle frag side effects without render targets
We still need to insert our lowering code, though this case could probably be
optimized somehow. Fixes a massive number of KHR-GLES3 and KHR-GLES31 tests,
including
KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-draw-calls2 and lots
of PBO tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
4ef89e71ba agx: Translate image_store from NIR
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
13bb1209e2 agx: Translate texture bindless handles
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
bb21160a19 agx: Pack bindless textures
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
34a9582091 agx: Handle bindless properly for txs lowering
When I wrote this pass I mostly guessed what our bindless handles would look
like. Now that we know we can do it right.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00