Commit graph

93443 commits

Author SHA1 Message Date
Eric Engestrom
2b237ff64c anv: use Mesa's u_atomic.h header
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-26 18:21:22 +01:00
Eric Engestrom
a2ae2d1fb0 radv: use Mesa's u_atomic.h header
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-26 18:21:22 +01:00
Bruce Cherniak
6fafba0e67 swr: set an explicit clear_rect if scissor is not enabled.
Fix regression of "no rendering" on simple apps like glxgears by
setting an explicit full surface clear_rect when scissor is not
enabled.

This regressed with commit 00173d91 "st/mesa: don't set 16
scissors and 16 viewports if they're unused" due to an assumption
that a default scissor rect is always set, which was the case prior
to this optimization.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-06-26 11:30:08 -05:00
Tim Rowley
0e1e5a2b14 swr/rast: adjust std::string usage to fix build
Some combinations of c++ compilers and standard libraries had problems
with the string::replace code we were using previously.

This should fix the travis-ci system.

Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-26 11:29:27 -05:00
Eric Engestrom
3c7c82cef0 travis: add missing libs: xdamage + xfixes
> configure: error: Package requirements (x11 xext xdamage >= 1.1 xfixes
> x11-xcb xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8) were not met:
> No package 'xdamage' found
> No package 'xfixes' found

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-26 15:44:37 +01:00
Nicolai Hähnle
f17d78becc radeonsi: support indirect indexing in INTERP_* opcodes
The hardware doesn't support it, so we just interpolate all array elements
and then use indirect indexing on the resulting vector.

Clearly, this is not very efficient. There is an argument to be had for
adding if/else, or perhaps even pulling the data out of LDS directly.
Both don't really seem worth the effort, considering that it seems nobody
actually uses this feature.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-26 14:02:06 +02:00
Ben Crocker
162c42f8ed egl_dri2: swrastGetDrawableInfo: set *x, *y [v2]
In swrastGetDrawableInfo, set *x and *y, not just *w and *h;
this fixes a crash later in drisw_update_tex_buffer when the
(formerly) uninitialized x and y values are used to construct
an address in a call to llvmpipe_transfer_map.

Fixes crash in Piglit test
"spec@egl 1.4@eglcreatepbuffersurface and then glclear"
(<piglit dir>/bin/egl-create-pbuffer-surface -auto)
that occurred intermittently, e.g. when the uninitialized x and y in
drisw_update_tex_buffer just happened to contain absurd non-zero values.

v2: Initialize in case if function succeeds or fails, just like *w/*h.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-26 12:48:19 +01:00
Emil Velikov
c58af5cbb2 egl: fold _eglError() + return EGL_FALSE
The function _eglError() already explicitly returns EGL_FALSE,
explicitly to simplify the callers. Make use of it.

While EGL_FALSE is numerically identical to false, NULL, EGL_NO_FOO,
storage is not the same so we cannot use it for "everything".

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-06-26 12:41:00 +01:00
Emil Velikov
d42b09580a egl: drop _eglInitImage() return type
Function cannot fail and always returns true.

v2: Inline the one line function in the header

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-06-26 12:40:22 +01:00
Juan A. Suarez Romero
860919a3b2 glsl: do not call link_xfb_stride_layout_qualifiers() for fragment shaders
xfb only applies to the latest stage before the fragment shader, so
there is no need to invoke it in the fragment shader.

Fixes:
KHR-GL45.enhanced_layouts.xfb_stride_of_empty_list
KHR-GL45.enhanced_layouts.xfb_stride_of_empty_list_and_api

v2: do reset only if shaders provide an explicit stride

v3: do not call link_xfb_stride_layout_qualifiers() for fragment shaders
(Timothy)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-06-26 12:00:22 +02:00
Constantine Charlamov
abc7b110b6 r600g: fix crash when file in R600_TRACE doesn't exist
…and print error in such case. Which probably is not a rare event btw
because fopen doesn't expand ~ to $HOME.

Also get rid of unused "bool ret" variable.

Signed-off-by: Constantine Kharlamov <Hi-Angel@yandex.ru>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 17:39:54 +10:00
Constantine Charlamov
3d466f3e9f r600g: take into account offset to system inputs at tgsi_interp_egcm()
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=100785

v2: I was too much twiddling whether to initialize nsys_inputs at the beginning of shader initialization or for allocation of system values, and by the time I decided to go with the first one, I forgot to change it back.

Signed-off-by: Constantine Kharlamov <Hi-Angel@yandex.ru>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:32:36 +10:00
Constantine Charlamov
469e2ed473 r600g: get rid of trailing whitespace
Signed-off-by: Constantine Kharlamov <Hi-Angel@yandex.ru>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:30:10 +10:00
Dave Airlie
27380d6b3e r600/asm: add support for other GDS operations.
This adds support for the GDS operations needed to do atomic
counters.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:27:51 +10:00
Dave Airlie
ccab3f7e1b r600: don't merge GDS into VTX
We don't want vtx/tex instructions ending up in GDS sections.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:23:21 +10:00
Dave Airlie
043f16eba1 r600: for memory instructions dump index gpr for read indirects also.
This just makes sure we can see the index gpr in the asm dumps.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:23:21 +10:00
Dave Airlie
ac8fb9800a r600: add support for vertex fetches via texture cache
On evergreen we can route vertex fetches via the texture cache,
and this is required for some images support. So add support
to the asm builder for it.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:23:20 +10:00
Dave Airlie
b050b91e33 r600: route indirect address register correctly for vtx fetches.
This was found during writing the images code, we need to
make sure we route the correct index register.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 16:23:20 +10:00
Dave Airlie
4a34f3244a radv/meta: don't need vertex info for resolve shader.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 01:24:10 +01:00
Marek Olšák
0715b3c2ee drirc: whitelist glthread for a few games
Performance deltas:
    Alien Isolation: +17% (it varies depending on the location)
    Borderlands 2: +50% (it varies depending on the location)
    BioShock Infinite: +76% (benchmark)
    Civilization 6: +20% (benchmark)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
4f38b48e05 mesa/glthread: decrease the batch size for better perf scaling
This is the key to better performance.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
09f6915bf8 gallium/hud: add glthread counters
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
8f4bc8a324 gallium/hud: add API-thread-busy for monitoring the thread load
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
11cf079b67 gallium/hud: add hud_pane::hud pointer
for later use

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
5fa69be3c8 mesa/glthread: add glthread "perf" counters and pass them to gallium HUD
for HUD integration in following commits. This valuable profiling data
will allow us to see on the HUD how well glthread is able to utilize
parallelism. This is better than benchmarking, because you can see
exactly what's happening and you don't have to be CPU-bound.

u_threaded_context has the same counters.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
833f3c1c31 gallium/hud: move struct hud_context to hud_private.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
7492201c4e gallium/hud: rename API-thread-busy to main-thread-busy
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
d1513edaa0 mesa/glthread: switch to u_queue and redesign the batch management
This mirrors exactly how u_threaded_context works.
If you understand this, you also understand u_threaded_context.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
1e37a5054b mesa/glthread: remove HAVE_PTHREAD guards
we are switching to util_queue.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Marek Olšák
6884c95ab4 util: move pipe_thread_is_self from gallium to src/util
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 02:17:03 +02:00
Bas Nieuwenhuizen
78bef01da2 radv: Remove unused args of radv_image_view_init.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-26 01:24:50 +02:00
Bas Nieuwenhuizen
789f480029 radv: Use correct image layout for blit based copies.
v2: Don't pass layout to image view usage mask.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 0628580eff "radv: Specify semantics of HTILE layout helpers."
2017-06-26 01:24:29 +02:00
Grigori Goronzy
95fb1c187a mesa/marshal: add custom marshalling for glNamedBuffer(Sub)Data
These entry points are used by Alien Isolation and caused
synchronization with glthread. The async marshalling implementation
is similar to glBuffer(Sub)Data. However unlike Buffer(Sub)Data
we don't need to worry about EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD,
as this isn't applicable to these DSA variants.

Results in an approximately 6x drop in glthread synchronizations and a
~30% FPS jump in Alien Isolation (Medium preset, Athlon 860K, RX 480).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-26 09:06:23 +10:00
Dave Airlie
6a68170c83 radv: handle primitive id input into fragment shader with no geom shader
Fixes:
dEQP-VK.pipeline.framebuffer_attachment.no_attachments
dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 08:45:30 +10:00
Dave Airlie
2a87ddbdcb radv: compile fragment shader first.
This reorders things as we need something from the fs for the vs key.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 08:45:26 +10:00
Dave Airlie
a563f611c3 radv: set prim_id for geometry shaders
Noticed in passing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 08:45:22 +10:00
Dave Airlie
4042892cee radv: set use_prim_id for tess shaders correctly.
Just noticed in passing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-26 08:45:14 +10:00
Pierre Moreau
afb8f2d4a3 nv50/ir: Properly fold constants in SPLIT operation
Fixes: b7d9677d ("nv50/ir: constant fold OP_SPLIT")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-06-25 15:23:46 +02:00
Marek Olšák
e25950808f radeonsi/gfx9: don't overallocate shader binaries
It's not needed. The hw doesn't fetch ahead over page boundaries.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-24 23:04:37 +02:00
Lucas Stach
d6b9ba36a4 st/dri2: implement image offset query
This trivially adds support for the image offset query, which is needed
for the zwp_linux_dmabuf based EGL platform wayland implementation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-06-24 16:57:55 +01:00
Samuel Pitoiset
cb577e379e mesa: only flush vertices when the viewport is different
This prevents glViewport() and friends to always flush and
trigger _NEW_VIEWPORT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-24 16:47:43 +02:00
Samuel Pitoiset
4178cea06d mesa: remove useless comments in the viewport code path
No need to explain why calling a driver callback is needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-24 16:47:38 +02:00
Roland Scheidegger
8bfe451ed3 llvmpipe: initialize default fb correctly in setup
If lp_setup_bind_framebuffer() is never called, then setup fb x1/y1 was not
correctly initialized. This can happen if there's never a fb set - both
cso and llvmpipe would consider setting this with no cbufs and no zsbuf a
redundant change and therefore it would never get set.
We rely on this setup fb rect being initialized correctly for the tri intersect
tests, throwing away tris which don't intersect. Not initializing it meant
we'd then say it intersected, and we'd try to bin that despite that we have
no actual tiles to bin it to, leading to assertion failures (pretty harmless
since tile 0/0 always exists nevertheless as tiles are statically allocated,
albeit that should change at some point).
(Note probably not an issue with gl state tracker)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-06-24 00:18:43 +02:00
Jason Ekstrand
f7f2fa8eb1 i965/miptree: Rework aux enabling
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.

This commit makes functional changes.  One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a6669 around a year ago.  Fixing this
improves the SynMark v7 DeferredAA test by around ~3% on some gen9
hardware.  This commit also gets us closer to enabling CCS_E for
window-system buffers which are Y-tiled.

Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-23 12:30:24 -07:00
Jason Ekstrand
f1fa4be871 i965: Clamp clear colors to the representable range
Starting with Sky Lake, we can clear to arbitrary floats or integers.
Unfortunately, the hardware isn't particularly smart when it comes
sampling from that clear color.  If the clear color is out of range for
the surface format, it will happily return whatever we put in the
surface state packet unmodified.  In order to avoid returning bogus
values for surfaces with a limited range, we need to do some clamping.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-06-23 12:30:24 -07:00
Jason Ekstrand
793b312b4a i965: Don't bother with HiZ in renderbuffer_move_to_temp
This function is only used on gen4-5 which don't support HiZ.

Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-06-23 12:30:24 -07:00
Jason Ekstrand
764cce442e i965/miptree: Rename the non_msrt_mcs functions to _ccs
While we're here, we also make the two support checks static since there
are no users outside intel_mipmap_tree.c.

Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-06-23 12:30:24 -07:00
Jason Ekstrand
a7059a764e i965/miptree: Delete the layered rendering resolve
We never fast-clear more than the base slice (LOD 0, layer 0) anyway, so
layered rendering without a resolve is always perfectly safe.  Should
this ever change in the future, we'll have to put some sort of resolve
back in but we can cross that bridge when we come to it.

Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-06-23 12:30:24 -07:00
Anuj Phogat
7896dee349 anv/cnl: Don't write to Cache Mode Register 1 on gen10+
For PartialResolveDisableInVC field recommendation is to
always set this to 0 and that's the default value of the bit.
So, we have nothing left to write to CACHE_MODE_1.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-23 11:16:00 -07:00
Anuj Phogat
b980553309 i965/cnl: Don't write to Cache Mode Register 1 on gen10+
With below optimizations gone in gen10+ we have nothing left out to
write to CACHE_MODE_1:
Float Blend Optimization Enable: This bit have been removed in gen10+
Partial Resolve Disable in VC: Recommendation is to always set this
field to 0 in gen10+ and that's the default value of the bit.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-23 11:16:00 -07:00