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anv/cnl: Don't write to Cache Mode Register 1 on gen10+

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For PartialResolveDisableInVC field recommendation is to
always set this to 0 and that's the default value of the bit.
So, we have nothing left to write to CACHE_MODE_1.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Anuj Phogat 2017-06-13 17:01:16 -07:00
parent b980553309
commit 7896dee349
1 changed files with 1 additions and 3 deletions
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4
src/intel/vulkan/genX_state.c
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@ -52,13 +52,11 @@ genX(init_device_state)(struct anv_device *device)
ps.PipelineSelection = _3D;
}
#if GEN_GEN >= 9
#if GEN_GEN == 9
uint32_t cache_mode_1;
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
#if GEN_GEN == 9
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true,
#endif
.PartialResolveDisableInVC = true,
.PartialResolveDisableInVCMask = true);