Commit graph

27608 commits

Author SHA1 Message Date
Rob Clark
d2fcd0ce38 freedreno/a3xx: remove unused fxn
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 17:10:14 -04:00
Rob Clark
8fe2076243 freedreno/ir3: convert over to ralloc
The home-grown heap scheme (which is ultra-simple but probably not good
to always allocate and memset such a chunk of memory up front) was a
remnant of fdre (where the ir originally came from).  But since we have
ralloc in mesa, lets just use that instead.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 17:09:09 -04:00
Rob Clark
2c8674f5a9 freedreno: honor handle->offset
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:22 -04:00
Rob Clark
dfd23abdcc freedreno: disallow cat4 immed src
Normally this would never happen (constant-propagation in NIR would
eliminate the instruction), except it does happen for 'undef' which
we turn into immed 0.0 for bookkeeping purposes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
76c6cdd36a freedreno/a4xx: add render-target formats
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
7add166a5c freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
edcc6ce75d freedreno: reduce line width for deqp further
See a7eb12d0.. but that wasn't restrictive enough.  Fixes
dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and
similar

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
4610e5ef28 freedreno/ir3: fix sin/cos
We seem to need range reduction to get sane results.  Fixes glmark2
jellyfish bench, and a whole bunch of
dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.*

v2: squashed in android build fixes from Rob Herring

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Charmaine Lee
c4cb879f00 svga: eliminiate unnecessary constant buffer updates
Currently if the texture binding is changed, emit_fs_consts()
is triggered to update texture scaling factor for
rectangle texture or texture buffer size in the constant buffer.
But the update is only relevant if the texture binding includes
a rectangle texture or a texture buffer.

To eliminate the unnecessary constant buffer updates due to other texture
binding changes, a new flag SVGA_NEW_TEXTURE_CONSTS will be used
to trigger fragment shader constant buffer update when a rectangle texture
or a texture buffer is bound.

With this patch, the number of constant buffer updates in Lightsmark2008
reduces from hundreds per frame to about 28 per frame.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
686cd3c606 svga: mark the texture dirty for write transfer map only
Instead of unconditionally mark the texture subresource dirty at transfer map,
we'll set the dirty bit for write transfer only.

Tested with lightsmark2008 and glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
676931640f svga: fix assert with PIPE_QUERY_OCCLUSION_PREDICATE for non-vgpu10
With this patch, when running in hardware version 11, we'll use
SVGA3D_QUERYTYPE_OCCLUSION query type for PIPE_QUERY_OCCLUSION_PREDICATE
and return TRUE if samples-passed count is greater than 0.

Fixes glretrace/solidworks2012_viewport running in hardware version 11.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
d7a6c1a476 svga: minimize surface flush
Currently, we always do a surface flush when we try to establish
a synchronized write transfer map. But if the subresource has not
been modified, we can skip the surface flush. In other words,
we only need to do a surface flush if the to-be-mapped subresource
has been modified in this command buffer.

With this patch, lightsmark2008 shows about 15% performance improvement.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
63df017fda util/blitter: use ARRAY_SIZE macro
And remove local definition of Elements() macro.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-25 12:59:29 -06:00
Brian Paul
e0184b3995 svga: s/Elements/ARRAY_SIZE/
Standardize on the later macro rather than a mix of both.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
77e4b41671 svga: whitespace and formatting fixes in svga_pipe_rasterizer.c 2016-04-25 12:59:29 -06:00
Brian Paul
25e0d3659f svga: whitespace and formatting fixes in svga_pipe_depthstencil.c 2016-04-25 12:59:29 -06:00
Brian Paul
595fbc8dee svga: whitespace and formatting fixes in svga_pipe_sampler.c 2016-04-25 12:59:29 -06:00
Brian Paul
1db8313168 gallium/util: initialize pipe_framebuffer_state to zeros
To silence a valgrind uninitialized memory warning.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94955
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
1e990978ee util/cache: add comments, fix formatting 2016-04-25 12:59:29 -06:00
Brian Paul
464d6080c6 svga: separate HUD counters for state objects
Count depth/stencil, blend, sampler, etc. state objects separately
but just report the sum for the HUD.  This change lets us use gdb to
see the breakdown of state objects in more detail.

Also, count sampler views too.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-04-25 09:45:16 -06:00
Robert Foss
b87856d25d st/omx: Fix resource leak on OMX_ErrorNone
Avoid leaking buffer allocated for task if an error has occured.

Coverity id: 1213929
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 15:09:37 +01:00
Grazvydas Ignotas
dc732a8ef2 gallium: use unreachable instead of asserts
Avoids warnings in release builds.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:34 +02:00
Grazvydas Ignotas
cbb0d4ad75 gallium: fix warnings in release build
Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:21 +02:00
Hans de Goede
787a53988c nouveau: codegen: combineLd/St do not combine indirect loads
combineLd/St would combine, i.e. :

st  u32 # g[$r2+0x0] $r2
st  u32 # g[$r2+0x4] $r3

into:

st  u64 # g[$r2+0x0] $r2d

But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders

This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-25 11:45:07 +02:00
Rob Clark
0831eb94b9 freedreno/ir3: relax restriction in grouping
Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw

Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
36c9ea6e79 freedreno/ir3: fix small memory leak
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
610837fb98 freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always.  For
example, in a sam(w) which only writes the 4th component.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
adf795432f freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions.  But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures.  Work around this
setting up a second texture state and using that to sample alpha
separately.

This way, srgb->linear conversion happens in hw *prior* to
interpolation.

This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
a148300b13 Revert "freedreno/a4xx: lower srgb in shader for astc textures"
Better workaround in the following patch.

This reverts commit 899bd63ace.
2016-04-24 13:40:57 -04:00
Rob Clark
19118e6f47 freedreno/a4xx: blend state no longer depends on fb state
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Marek Olšák
c0c6ca40a2 Revert "st/dri: add 32-bit RGBX/RGBA formats"
This reverts commit ccdcf91104.

It breaks most KDE apps, because DRI doesn't support the RGBA component
ordering.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95071
2016-04-24 15:16:07 +02:00
Tom Stellard
9f110a9e10 radeonsi: Implement ddx/ddy on VI using ds_bpermute
The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads.  These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.

DDX BEFORE:                        |  DDX AFTER:
                                   |
v_mbcnt_lo_u32_b32_e64 v2, -1, 0   |  v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2  |  v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2        |  v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2           |  v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2        |  ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1                   |  ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0                |  s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0)               |
v_or_b32_e32 v0, 1, v2             |
v_lshlrev_b32_e32 v0, 2, v0        |
ds_read_b32 v1, v3                 |
ds_read_b32 v0, v0                 |
s_waitcnt lgkmcnt(0)               |
                                   |
LDS: 1 blocks                      |  LDS: 0 blocks

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:43 +00:00
Tom Stellard
128267d781 radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid
We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.

v2:
  - Only do this with LLVM 3.8 and newer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:43 +00:00
Tom Stellard
d3427412a3 radeonsi: Set range metadata on calls to llvm.SI.tid
The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:41 +00:00
Tom Stellard
b31422d970 radeonsi: Create a helper function for computing the thread id
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:45:34 +00:00
Tim Rowley
ec089cd987 swr: [rasterizer memory] Constify load tiles
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:49:20 -05:00
Tim Rowley
6facf4b74a swr: [rasterizer core] CompleteDrawContext changes for gcc
Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:49:04 -05:00
Tim Rowley
0487377dce swr: [rasterizer] Small cleanups
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:56 -05:00
Tim Rowley
2c4c3c9c71 swr: [rasterizer scripts] Knob scripts tweaks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:47 -05:00
Tim Rowley
ef293ee9c0 swr: [rasterizer] Interpolation utility functions
v2: use _mm_cmpunord_ps for vIsNaN

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:38 -05:00
Tim Rowley
27cc5924ea swr: [rasterizer core] TemplateArgUnroller
Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.

This allows the template argument unroller to easily be extended to enums.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:29 -05:00
Tim Rowley
46a448d161 swr: [rasterizer core] Arena: make most allocated blocks the same size
Reduces sorting cost

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:20 -05:00
Tim Rowley
794be41f91 swr: [rasterizer core] Fix global arena allocator bug
- Plus some minor code refactoring

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:11 -05:00
Tim Rowley
e42f00ee39 swr: [rasterizer core] Fix thread binding for 32-bit windows
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:59 -05:00
Tim Rowley
cd21f90ecf swr: [rasterizer fetch] Add support for fetching non-uniform component formats
For example, R10G10B10A2_UNORM.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:48 -05:00
Tim Rowley
244ae7af1b swr: [rasterizer core] Use CS spill/fill size in core
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:02 -05:00
Tim Rowley
ee9621e2f5 swr: fix memory leaks from vs/fs compilation
v2: varient -> variant

Reviewed by: George Kyriazis <George.Kyriazis@intel.com>
2016-04-22 18:05:02 -05:00
Tim Rowley
5815c8b3d3 swr: fix clang warnings
v2: use alternate logic version in swr_check_render_cond

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:03:41 -05:00
Rob Clark
e85bef8b12 freedreno/a4xx: fix encoding of blend color state
Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now
they all pass)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-22 15:00:34 -04:00
Rob Clark
23abc41d2b freedreno: update generated headers
Pull in RB_BLEND_* fixes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-22 15:00:34 -04:00