Commit graph

220083 commits

Author SHA1 Message Date
Eric Engestrom
276c8b721b Revert "meson: Fix build break on f43, gentoo, etc"
This reverts commit 4fc7a26aed.

This is no longer needed after the previous commits in this MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40514>
2026-03-20 16:29:14 +00:00
Eric Engestrom
dbbc7800c5 meson: move yaml lib check inside python check
This avoids picking a version of python that doesn't have pyyaml installed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40514>
2026-03-20 16:29:14 +00:00
Eric Engestrom
9d6774ba8f meson: move mako lib check inside python check
This avoids picking a version of python that doesn't have mako installed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40514>
2026-03-20 16:29:14 +00:00
Eric Engestrom
d787eb6048 meson: flip python check to avoid nesting conditions in the next commits
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40514>
2026-03-20 16:29:13 +00:00
Mike Blumenkrantz
929eb9a021 mesa/renderbuffer: always add PIPE_BIND_SAMPLER_VIEW to rendering textures
this fixes expectations around e.g., using u_blitter to copy textures

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40444>
2026-03-20 15:15:32 +00:00
Arjob Mukherjee
3df9ec7ae3 pvr: Fixup for deqp-vk.api 2d.optimal.* conformance
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Its no longer an error for depth and stencil formats to have invalid
accumulator format.

Fixes the following tests:
* dEQP-VK.api.info.image_format_properties.2d.optimal.d16_unorm
* dEQP-VK.api.info.image_format_properties.2d.optimal.d24_unorm_s8_uint
* dEQP-VK.api.info.image_format_properties.2d.optimal.d32_sfloat
* dEQP-VK.api.info.image_format_properties.2d.optimal.d32_sfloat_s8_uint
* dEQP-VK.api.info.image_format_properties.2d.optimal.s8_uint
* dEQP-VK.api.info.image_format_properties.2d.optimal.x8_d24_unorm_pack3

Signed-off-by: Nick Hamilton <nick.hamilton@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40456>
2026-03-20 14:57:21 +00:00
Nick Hamilton
96cfb1cb7f pvr: Fix for multiple attachments being assigned to the same tile buffer.
When the first attachment is assigned to a tile buffer, the buffer
alloc mask was not been updated. This means when a second attachment
is added to the same tile buffer it will be assigned the same offset
as the first which will lead to incorrect behaviour.

Fixes for depq-vk:
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.suballocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.dedicated_allocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.suballocation.attachment.4.568
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.dedicated_allocation.attachment.4.568

Fixes: a7de9dae6b ("pvr: Add routine for filling out usc_mrt_setup from dynamic rendering state")

Signed-off-by: Nick Hamilton <nick.hamilton@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40456>
2026-03-20 14:57:21 +00:00
Luigi Santivetti
5473ca3be3 pvr: keep compiler resources in sync with attachments
Do not assume that the application always provides images for backing
attachments. The app can provide a super set of attachments of which
only some are actually backed with images.

We want to filter-out attachments that aren't meaningful for rendering
or sampling, and create compiler resources only for relevant ones.

Fix assert in CTS:
  pvr_arch_mrt.c:215: pvr_rogue_init_usc_mrt_setup: Assertion `att_format != VK_FORMAT_UNDEFINED' failed.

Seen in pipeline monolithic, for instance:
  dEQP-VK.pipeline.monolithic.multisample.misc.dynamic_rendering.multi_renderpass.r8g8b8a8_unorm_r16g16b16a16_sfloat_r16g16b16a16_sint_d32_sfloat_s8_uint.random_127

Fixes: d549c1d045 ("pvr: add pipeline handling to use dynamic rendering info")
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40456>
2026-03-20 14:57:21 +00:00
Luigi Santivetti
6b0fea938b pvr: expose partial usc mrt init routine
Expose the routine in preperation for a later commit.

Backport-to: 26.0

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40456>
2026-03-20 14:57:21 +00:00
Simon Perretta
8eee60fa78 pco: use vm/icm for tile buffer store coverage mask
Use the valid/input coverage masks for tile buffer store coverage masks
when running single/multi-sampled fragment shaders respectively.

Fixes: 297a0c269a ("pvr, pco: tile buffer support")

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Reported-by: Nick Hamilton <nick.hamilton@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40456>
2026-03-20 14:57:21 +00:00
Rob Clark
2e7a64c193 freedreno/registers: Update gmu reg offsets
The kernel commit 188db3d7fe66 ("drm/msm/a6xx: Rebase GMU register
offsets") shifted the GMU reg offsets to be relative to the GPU base.
This change landed in the v6.19 kernel.

This commit pulls that change back into mesa.  Crashdec is modified to
add the offset if the devcoredump came from a kernel prior to v6.19.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40495>
2026-03-20 14:22:57 +00:00
David Rosca
089cd9d88e frontends/va: Fix leaks when create_video_codec fails
Cc: mesa-stable
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40504>
2026-03-20 13:02:23 +00:00
David Rosca
5134d37e7d frontends/va: Fix leaking H264/5 PPS/SPS objects when decoder wasn't created
When destroying H264/5 decode context we check the profile from decoder to
free the H264/5 PPS/SPS objects, but decoder is only created when decoding
first frame so these objects will never get freed in case decoder is NULL.

Cc: mesa-stable
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40504>
2026-03-20 13:02:23 +00:00
Rhys Perry
e2ebcba11b aco/tests: fix assembler/isel tests with LLVM 23
Some checks are pending
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40513>
2026-03-20 10:24:06 +00:00
Rhys Perry
0826685f1b aco/tests: fix assembler tests with LLVM 22
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40513>
2026-03-20 10:24:06 +00:00
Samuel Pitoiset
e3015d7d5a radv/meta: decompress source resolve images slighly earlier
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40491>
2026-03-20 09:56:49 +00:00
Samuel Pitoiset
d2818c5b3f radv/meta: cleanup determining the resolve method
The fragment resolve path supports everything except layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40491>
2026-03-20 09:56:49 +00:00
Eric Engestrom
82473c1524 docs: fix release calendar
I accidentally pushed all dates to one week later instead of one week earlier 🤦

Fixes: da214b0fce ("docs: update calendar for 26.0.3")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40530>
2026-03-20 09:51:22 +00:00
Georg Lehmann
cf4182ef5e broadcom/ci: skip rpi4 timeout
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
643dd510d4 nir/opt_algebraic: optimize b2f(a) * b
When the multiplication is only used by fadd, it's not a clear win
because of potential fma fusion.

Totals from 8015 (6.99% of 114655) affected shaders:
MaxWaves: 199394 -> 199466 (+0.04%); split: +0.04%, -0.01%
Instrs: 17461518 -> 17451076 (-0.06%); split: -0.10%, +0.04%
CodeSize: 94779552 -> 94769828 (-0.01%); split: -0.07%, +0.06%
VGPRs: 526012 -> 525532 (-0.09%); split: -0.10%, +0.01%
SpillSGPRs: 12466 -> 12517 (+0.41%); split: -0.09%, +0.50%
Latency: 191274766 -> 191297394 (+0.01%); split: -0.03%, +0.04%
InvThroughput: 31465968 -> 31456785 (-0.03%); split: -0.07%, +0.04%
VClause: 312081 -> 312073 (-0.00%); split: -0.10%, +0.09%
SClause: 366914 -> 366906 (-0.00%); split: -0.02%, +0.01%
Copies: 1222482 -> 1221933 (-0.04%); split: -0.20%, +0.15%
Branches: 376651 -> 376577 (-0.02%); split: -0.03%, +0.01%
PreSGPRs: 442974 -> 443240 (+0.06%); split: -0.01%, +0.07%
PreVGPRs: 415964 -> 415668 (-0.07%); split: -0.09%, +0.02%
VALU: 9403517 -> 9393916 (-0.10%); split: -0.12%, +0.02%
SALU: 2799420 -> 2800430 (+0.04%); split: -0.13%, +0.16%
VOPD: 472826 -> 472347 (-0.10%); split: +0.09%, -0.19%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
d2b37b667e nir/opt_algebraic: optimize more fmulz(1.0, a) remains
If dxvk's opencoded fmulz gets partially constant folded,
it leaves this mess behind.

It's important to do this before the more general fmul+b2f patterns added
in the next commit, because they change the signed zero behavior in a way
that can't be optimized back.

Foz-DB Navi48:
Totals from 36 (0.03% of 114655) affected shaders:

Instrs: 16513 -> 15706 (-4.89%)
CodeSize: 99756 -> 95760 (-4.01%)
Latency: 45165 -> 44151 (-2.25%)
InvThroughput: 8344 -> 7886 (-5.49%)
VClause: 395 -> 401 (+1.52%)
Copies: 639 -> 634 (-0.78%)
PreSGPRs: 1158 -> 1154 (-0.35%)
PreVGPRs: 1227 -> 1225 (-0.16%)
VALU: 11310 -> 10769 (-4.78%)
SALU: 813 -> 809 (-0.49%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
3ad142d4d7 nir/search: never insert movs for alu uses
This means we respect the pattern order better because
simple replacements like bcsel(False, a, b) -> b no longer
insert movs that can block more specialized patterns.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
1626df7a90 nir: rework nir_alu_src_is_trivial_ssa to take an alu src
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
b96c42c916 nir/opt_algebraic: optimize more near useless bcsel
Foz-DB Navi48:
Totals from 327 (0.29% of 114655) affected shaders:
Instrs: 732971 -> 731642 (-0.18%); split: -0.19%, +0.01%
CodeSize: 3696020 -> 3689824 (-0.17%); split: -0.17%, +0.00%
Latency: 4405319 -> 4403413 (-0.04%); split: -0.06%, +0.01%
InvThroughput: 650209 -> 649659 (-0.08%); split: -0.10%, +0.01%
Copies: 53872 -> 53736 (-0.25%); split: -0.27%, +0.02%
Branches: 15598 -> 15571 (-0.17%)
VALU: 262391 -> 261969 (-0.16%)
SALU: 268112 -> 267699 (-0.15%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
6cfe6eaa79 nir/opt_algebraic: create ldexp from exp2
Some checks are pending
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ldexp uses the full width VALU path, exp2 the transcendental SIMD8.

Foz-DB Navi21:
Totals from 729 (0.64% of 114627) affected shaders:
MaxWaves: 20071 -> 20103 (+0.16%); split: +0.18%, -0.02%
Instrs: 869129 -> 867654 (-0.17%); split: -0.17%, +0.00%
CodeSize: 4709000 -> 4708460 (-0.01%); split: -0.02%, +0.00%
VGPRs: 31184 -> 31128 (-0.18%); split: -0.23%, +0.05%
Latency: 7610726 -> 7597238 (-0.18%); split: -0.18%, +0.00%
InvThroughput: 1822323 -> 1819815 (-0.14%); split: -0.14%, +0.00%
VClause: 22494 -> 22493 (-0.00%); split: -0.03%, +0.02%
SClause: 20520 -> 20509 (-0.05%)
Copies: 72025 -> 72024 (-0.00%); split: -0.01%, +0.01%
Branches: 22028 -> 22029 (+0.00%)
PreVGPRs: 21601 -> 21602 (+0.00%)
VALU: 604821 -> 603339 (-0.25%); split: -0.25%, +0.00%
SALU: 114258 -> 114262 (+0.00%); split: -0.00%, +0.01%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33900>
2026-03-20 08:15:08 +00:00
Georg Lehmann
ec331cc48a nir: replace lower_ldexp with has_ldexp
I can be bothered to fix all the backends that don't set lower_ldexp,
and only two backends have ldexp anyway.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33900>
2026-03-20 08:15:08 +00:00
Iván Briano
fd556e54f6 brw: do not omit RT writes if dual_src_blend is on
Some checks are pending
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Dual source blending when one of the sources is not written to leaves
those values undefined, but the other should still be valid.
By omitting unwritten outputs, we ended up not writing anything at all
for the case that OUT1 is written to but OUT0 is undefined.

Fixes new CTS tests: dEQP-VK.pipeline.*.blend.dual_source.undefined_output.first*

Cc: mesa-stable
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40357>
2026-03-19 23:38:40 +00:00
Iván Briano
2ce8a9e1be anv: fix anv_is_dual_src_blend_equation
Fixes new tests: dEQP-VK.pipeline.*.blend.dual_source.undefined_output.second*

Cc: mesa-stable
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40357>
2026-03-19 23:38:40 +00:00
Tapani Pälli
8afb28952c intel/dev: update mesa_defs.json from workaround database
Some checks are pending
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This bring NVL_U workarounds and one update for PTL and WCL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15067
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40508>
2026-03-19 20:58:37 +00:00
Tapani Pälli
9384fd42f9 intel/dev: add NVL_U, NVL_P platforms to gen_wa_helpers.py
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40508>
2026-03-19 20:58:37 +00:00
Danylo Piliaiev
b86ecec80b tu: Fix imported memory not being affected by DEVICE_ADDRESS_CAPTURE_REPLAY
It's valid to import memory with DEVICE_ADDRESS_CAPTURE_REPLAY_BIT
and we should allocate iova from the end of VMA heap, same as with ordinary
memory allocations. This is important for replaying such memory, when it
is being replayed without being imported.

Fixes replay errors with RenderDoc.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40378>
2026-03-19 20:28:39 +00:00
Rob Clark
48be91d14b freedreno/common: Fix upstream a830 chip_id
Add missing fuse bits (which are all `1` if no fuse).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40458>
2026-03-19 19:58:20 +00:00
Rob Clark
55ee6aa57c freedreno/a6xx: Move A2D reg write to ncrb
It is not a 3d context reg.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40458>
2026-03-19 19:58:20 +00:00
Samuel Pitoiset
130a066d58 radv: stop passing radv_device for creating NIR meta shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
6bf978e13e radv: move setting NIR options for meta shaders
To remove radv_device from radv_meta_nir_init_shader().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
dcf0274e82 radv: stop associating NIR with device for debugging tools
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
fddbeddb2d radv: move valid VA debug info to radv_valid_va data
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
7ce3b2a68e radv: move radv_printf_data to radv_debug_nir
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
f776a763b4 radv: remove unnecessary radv_device parameter to few functions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
59883a5cb6 vulkan: stop passing vk_device to vk_set_subgroup_size()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Silvio Vilerino
6e39982b32 d3d12: d3d12_video_encode_support_caps was assigning a stack variable address to capEncoderSupportData in/out arg
Some checks are pending
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Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Silvio Vilerino
0e37a80aca d3d12: Truncate move_rects_support.bits.max_motion_hints 16 bit var to 65535, not 65536
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
d2ad51fc0a mediafoundation: set reasonable number of reference frames if the user didn't set CODECAPI_AVEncVideoMaxNumRefFrame
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
c97ff97df6 mediafoundation: set defualt unwrapped poc for h264 to true
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
7ae3977fe7 mediafoundation: fix hevc vui time_scale
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Thong Thai
525fcdfcee radeonsi: remove radeonsi prefix from si_pipe.h includes
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40518>
2026-03-19 18:47:29 +00:00
Lionel Landwerlin
5d7cf5e762 anv: don't queue pipe control reasons wihout a trace
When there is no trace pointer, there is usually a another tracepoint
being emitted (see STATE_BASE_ADDRESS,
3DSTATE_BINDING_TABLE_POOL_ALLOC emission).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40503>
2026-03-19 18:13:46 +00:00
Ian Romanick
d038bfa1c1 util: Use same method to clear bits in u_foreach_bit as util_bitcount
Saves about 2k text size.

Before:

   text	   data	    bss	    dec	    hex	filename
24817485	 456164	  27080	25300729	1820ef9	./lib64/libvulkan_intel.so

After:

   text	   data	    bss	    dec	    hex	filename
24815381	 456164	  27080	25298625	18206c1	./lib64/libvulkan_intel.so

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00
Ian Romanick
e13565acf4 anv: Use u_foreach_bit
Suggested-by: Lionel
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00
Ian Romanick
4cbf2ee3f0 anv: Use different logic to isolate lowest flag in anv_foreach_vk_stage
Silences many ubsan errors like:

src/intel/vulkan/anv_shader_compile.c:609:4: runtime error: shift exponent -1 is negative

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00