mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-06-10 03:28:18 +02:00
freedreno/registers: Update gmu reg offsets
The kernel commit 188db3d7fe66 ("drm/msm/a6xx: Rebase GMU register
offsets") shifted the GMU reg offsets to be relative to the GPU base.
This change landed in the v6.19 kernel.
This commit pulls that change back into mesa. Crashdec is modified to
add the offset if the devcoredump came from a kernel prior to v6.19.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40495>
This commit is contained in:
Rob Clark
Marge Bot
parent
089cd9d88e
commit
2e7a64c193
4 changed files with 1372 additions and 1337 deletions
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@ -33,6 +33,8 @@ static uint64_t fault_iova;
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static bool has_fault_iova;
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static int lookback = 20;
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static unsigned gmu_offset = 0;
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struct cffdec_options options = {
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.draw_filter = -1,
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};
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@ -691,7 +693,7 @@ decode_gmu_registers(void)
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reg_buf.regs[reg_buf.count].value = value;
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reg_buf.count++;
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if (regacc_push(&r, offset / 4, value)) {
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if (regacc_push(&r, (offset / 4) + gmu_offset, value)) {
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printf("\t%08"PRIx64"\t", r.value);
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dump_register(&r);
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}
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@ -1100,11 +1102,21 @@ decode(void)
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while ((line = popline())) {
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printf("%s", line);
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if (startswith(line, "kernel:")) {
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unsigned major, minor;
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char *release = NULL;
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parseline(line, "kernel: %ms", &release);
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strncpy((char *)snapshot_linux.release, release, sizeof(snapshot_linux.release) - 1);
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free(release);
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/* Extract the kernel version. The offset of GMU regs was
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* shifted in v6.19 as gen8 support was added. For backwards
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* compatibility with earlier kernels, we need to add an
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* offset.
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*/
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parseline(line, "kernel: %u.%u", &major, &minor);
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if ((major < 6) || ((major == 6) && (minor < 19)))
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gmu_offset = 0x1a800;
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} else if (startswith(line, "time:")) {
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double time;
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@ -40,56 +40,62 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<bitfield name="IRQ_MASK_BIT" pos="0" />
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</bitset>
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<reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
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<reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
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<reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
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<reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
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<reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
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<reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
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<reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
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<reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
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<reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
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<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
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<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
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<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
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<reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION">
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<reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
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<reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
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<reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/>
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<reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/>
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<reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/>
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<reg32 offset="0x1cbf8" name="GMU_BOOT_SLUMBER_OPTION"/>
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<reg32 offset="0x1cbf9" name="GMU_GX_VOTE_IDX"/>
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<reg32 offset="0x1cbfa" name="GMU_MX_VOTE_IDX"/>
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<reg32 offset="0x1cbfc" name="GMU_DCVS_ACK_OPTION"/>
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<reg32 offset="0x1cbfd" name="GMU_DCVS_PERF_SETTING"/>
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<reg32 offset="0x1cbfe" name="GMU_DCVS_BW_SETTING"/>
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<reg32 offset="0x1cbff" name="GMU_DCVS_RETURN"/>
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<reg32 offset="0x1d3f8" name="GMU_CORE_FW_VERSION">
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<bitfield name="MAJOR" low="28" high="31"/>
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<bitfield name="MINOR" low="16" high="27"/>
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<bitfield name="STEP" low="0" high="15"/>
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</reg32>
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<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
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<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
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<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
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<reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
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<reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
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<reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
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<reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
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<reg32 offset="0x502d" name="GMU_CM3_CFG"/>
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<reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
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<reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
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<reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
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<reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
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<reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
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<reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
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<reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
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<reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
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<reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
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<reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
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<reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
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<reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
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<reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
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<reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
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<reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
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<reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
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<reg32 offset="0x1f400" name="GMU_ICACHE_CONFIG"/>
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<reg32 offset="0x1f401" name="GMU_DCACHE_CONFIG"/>
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<reg32 offset="0x1f40f" name="GMU_SYS_BUS_CONFIG"/>
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<reg32 offset="0x1f50b" name="GMU_MRC_GBIF_QOS_CTRL"/>
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<reg32 offset="0x1f800" name="GMU_CM3_SYSRESET"/>
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<reg32 offset="0x1f801" name="GMU_CM3_BOOT_CONFIG"/>
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<reg32 offset="0x1f81a" name="GMU_CM3_FW_BUSY"/>
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<reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/>
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<reg32 offset="0x1f82d" name="GMU_CM3_CFG"/>
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<reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
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<reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" variants="A8XX"/>
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<reg32 offset="0x1f841" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
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<reg32 offset="0x1f842" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
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<reg32 offset="0x1fc40" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0" variants="A8XX-"/>
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<reg32 offset="0x1fc41" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1" variants="A8XX-"/>
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<reg32 offset="0x1f844" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
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<reg32 offset="0x1fca0" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L" variants="A8XX-"/>
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<reg32 offset="0x1f845" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
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<reg32 offset="0x1fca1" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H" variants="A8XX-"/>
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<reg32 offset="0x1f846" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
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<reg32 offset="0x1f847" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
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<reg32 offset="0x1f848" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
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<reg32 offset="0x1f849" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
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<reg32 offset="0x1f84a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
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<reg32 offset="0x1f84b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
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<reg32 offset="0x1f84c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
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<reg32 offset="0x1f84d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
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<reg32 offset="0x1f84e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
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<reg32 offset="0x1f84f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
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<reg32 offset="0x1f8c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
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<bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
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<bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
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<bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
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<bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
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<bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
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</reg32>
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<reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
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<reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
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<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
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<reg32 offset="0x1f8c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
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<reg32 offset="0x1f8c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
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<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX">
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<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
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<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
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<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
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@ -99,15 +105,19 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
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<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
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</reg32>
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<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
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<reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
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<bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
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<bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
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</reg32>
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<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
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<reg32 offset="0x1f7e8" name="GMU_PWR_CLK_STATUS" variants="A8XX-">
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<bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
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<bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
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</reg32>
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<reg32 offset="0x1f8e4" name="GMU_GPU_NAP_CTRL">
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<bitfield name="HW_NAP_ENABLE" pos="0"/>
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<bitfield name="SID" low="4" high="8"/>
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</reg32>
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<reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
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<reg32 offset="0x1f8e8" name="GMU_RPMH_CTRL">
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<bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
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<bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
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<bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
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@ -119,71 +129,84 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
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<bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
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</reg32>
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<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
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<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
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<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
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<reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
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<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
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<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
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<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
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<reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
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<reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
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<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
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<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
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<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
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<reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
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<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
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<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
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<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
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<reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
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<reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
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<reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
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<reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
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<reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
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<reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
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<reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
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<reg32 offset="0x1f8e9" name="GMU_RPMH_HYST_CTRL"/>
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<reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/>
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<reg32 offset="0x1f7e9" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A8XX-"/>
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<reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/>
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<reg32 offset="0x1f7ec" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A8XX-"/>
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<reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/>
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<reg32 offset="0x1f7ed" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A8XX-"/>
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<reg32 offset="0x1f900" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
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<reg32 offset="0x1f901" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
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<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
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<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
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<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
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<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/>
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<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/>
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<reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/>
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<reg32 offset="0x1f7e4" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A8XX-"/>
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<reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/>
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<reg32 offset="0x1f7e5" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A8XX-"/>
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<reg32 offset="0x1f980" name="GMU_HFI_CTRL_STATUS"/>
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<reg32 offset="0x1f981" name="GMU_HFI_VERSION_INFO"/>
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<reg32 offset="0x1f982" name="GMU_HFI_SFR_ADDR"/>
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<reg32 offset="0x1f983" name="GMU_HFI_MMAP_ADDR"/>
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<reg32 offset="0x1f984" name="GMU_HFI_QTBL_INFO"/>
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<reg32 offset="0x1f985" name="GMU_HFI_QTBL_ADDR"/>
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<reg32 offset="0x1f986" name="GMU_HFI_CTRL_INIT"/>
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<reg32 offset="0x1f990" name="GMU_GMU2HOST_INTR_SET"/>
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<reg32 offset="0x1f991" name="GMU_GMU2HOST_INTR_CLR"/>
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<reg32 offset="0x1f992" name="GMU_GMU2HOST_INTR_INFO">
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<bitfield name="MSGQ" pos="0" type="boolean"/>
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<bitfield name="CM3_FAULT" pos="23" type="boolean"/>
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</reg32>
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<reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
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<reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
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<reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
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<reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
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<reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
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<reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
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<reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
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<reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
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<reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
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<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
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<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
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<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
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<reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
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<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
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<reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
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<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
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<reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
|
||||
<reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
|
||||
<reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
|
||||
<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
|
||||
<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
|
||||
<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
|
||||
<reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
|
||||
<reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
|
||||
<reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
|
||||
<reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
|
||||
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
|
||||
<reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
|
||||
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
|
||||
<reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
|
||||
<reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
|
||||
<reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
|
||||
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
|
||||
<reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
|
||||
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
|
||||
<reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
|
||||
<reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
|
||||
<reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
|
||||
<reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
|
||||
<reg32 offset="0x1f993" name="GMU_GMU2HOST_INTR_MASK"/>
|
||||
<reg32 offset="0x1f994" name="GMU_HOST2GMU_INTR_SET"/>
|
||||
<reg32 offset="0x1f995" name="GMU_HOST2GMU_INTR_CLR"/>
|
||||
<reg32 offset="0x1f996" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
|
||||
<reg32 offset="0x1f997" name="GMU_HOST2GMU_INTR_EN_0"/>
|
||||
<reg32 offset="0x1f998" name="GMU_HOST2GMU_INTR_EN_1"/>
|
||||
<reg32 offset="0x1f999" name="GMU_HOST2GMU_INTR_EN_2"/>
|
||||
<reg32 offset="0x1f99a" name="GMU_HOST2GMU_INTR_EN_3"/>
|
||||
<reg32 offset="0x1f99b" name="GMU_HOST2GMU_INTR_INFO_0"/>
|
||||
<reg32 offset="0x1f99c" name="GMU_HOST2GMU_INTR_INFO_1"/>
|
||||
<reg32 offset="0x1f99d" name="GMU_HOST2GMU_INTR_INFO_2"/>
|
||||
<reg32 offset="0x1f99e" name="GMU_HOST2GMU_INTR_INFO_3"/>
|
||||
<reg32 offset="0x1f9c5" name="GMU_GENERAL_0"/>
|
||||
<reg32 offset="0x1f9c6" name="GMU_GENERAL_1"/>
|
||||
<reg32 offset="0x1f9cb" name="GMU_GENERAL_6"/>
|
||||
<reg32 offset="0x1f9cc" name="GMU_GENERAL_7"/>
|
||||
<reg32 offset="0x1f9cd" name="GMU_GENERAL_8" variants="A7XX"/>
|
||||
<reg32 offset="0x1f9ce" name="GMU_GENERAL_9" variants="A7XX"/>
|
||||
<reg32 offset="0x1f9cf" name="GMU_GENERAL_10" variants="A7XX"/>
|
||||
<reg32 offset="0x1f9c0" name="GMU_GENERAL_0" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9c1" name="GMU_GENERAL_1" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9c6" name="GMU_GENERAL_6" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9c7" name="GMU_GENERAL_7" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9c8" name="GMU_GENERAL_8" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9c9" name="GMU_GENERAL_9" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9ca" name="GMU_GENERAL_10" variants="A8XX"/>
|
||||
<reg32 offset="0x1f9cb" name="GMU_GENERAL_11" variants="A8XX"/>
|
||||
<reg32 offset="0x1f95d" name="GMU_ISENSE_CTRL"/>
|
||||
<reg32 offset="0x23120" name="GPU_CS_ENABLE_REG"/>
|
||||
<reg32 offset="0x1f95d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
|
||||
<reg32 offset="0x22d78" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
|
||||
<reg32 offset="0x22d58" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
|
||||
<reg32 offset="0x22d80" name="GPU_CS_A_SENSOR_CTRL_0"/>
|
||||
<reg32 offset="0x422da" name="GPU_CS_A_SENSOR_CTRL_2"/>
|
||||
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
|
||||
<reg32 offset="0x23157" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
|
||||
<reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
|
||||
<reg32 offset="0x2301d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
|
||||
<reg32 offset="0x2301f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
|
||||
<reg32 offset="0x23021" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
|
||||
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
|
||||
<reg32 offset="0x2316d" name="GPU_CS_AMP_PERIOD_CTRL"/>
|
||||
<reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/>
|
||||
<reg32 offset="0x1f94d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
|
||||
<reg32 offset="0x23b03" name="GMU_AO_INTERRUPT_EN"/>
|
||||
<reg32 offset="0x23b04" name="GMU_AO_HOST_INTERRUPT_CLR"/>
|
||||
<reg32 offset="0x23b05" name="GMU_AO_HOST_INTERRUPT_STATUS">
|
||||
<bitfield name="WDOG_BITE" pos="0" type="boolean"/>
|
||||
<bitfield name="RSCC_COMP" pos="1" type="boolean"/>
|
||||
<bitfield name="VDROOP" pos="2" type="boolean"/>
|
||||
|
|
@ -191,27 +214,27 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
|
||||
<bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
|
||||
<reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
|
||||
<reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
|
||||
<reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
|
||||
<reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
|
||||
<reg32 offset="0x23b06" name="GMU_AO_HOST_INTERRUPT_MASK"/>
|
||||
<reg32 offset="0x23b09" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
|
||||
<reg32 offset="0x23b0a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
|
||||
<reg32 offset="0x23b0b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
|
||||
<reg32 offset="0x23b0c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
|
||||
<bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
|
||||
<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
|
||||
<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
|
||||
<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
|
||||
<reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
|
||||
<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
|
||||
<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
|
||||
<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
|
||||
<reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
|
||||
<reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
|
||||
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
|
||||
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
|
||||
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
|
||||
<reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
|
||||
<reg32 offset="0x23b0d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
|
||||
<reg32 offset="0x23b0e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
|
||||
<reg32 offset="0x23b10" name="GMU_AO_AHB_FENCE_CTRL"/>
|
||||
<reg32 offset="0x23b13" name="GMU_AHB_FENCE_STATUS"/>
|
||||
<reg32 offset="0x23b14" name="GMU_AHB_FENCE_STATUS_CLR"/>
|
||||
<reg32 offset="0x23b15" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
|
||||
<reg32 offset="0x23b16" name="GMU_AO_SPARE_CNTL"/>
|
||||
<reg32 offset="0x23b07" name="GMU_RSCC_CONTROL_REQ"/>
|
||||
<reg32 offset="0x23b08" name="GMU_RSCC_CONTROL_ACK"/>
|
||||
<reg32 offset="0x23b11" name="GMU_AHB_FENCE_RANGE_0"/>
|
||||
<reg32 offset="0x23b12" name="GMU_AHB_FENCE_RANGE_1"/>
|
||||
<reg32 offset="0x24403" name="GPU_CC_GX_GDSCR"/>
|
||||
<reg32 offset="0x24542" name="GPU_CC_GX_DOMAIN_MISC"/>
|
||||
<reg32 offset="0x26801" name="GPU_CPR_FSM_CTL"/>
|
||||
|
||||
<!-- starts at offset 0x8c00 on most gpus -->
|
||||
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
|
||||
|
|
|
|||
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Add table
Reference in a new issue