Commit graph

6558 commits

Author SHA1 Message Date
Bas Nieuwenhuizen
379d31bc6c radv: Do pipe misalignment check per plane.
Fixes: 4c99d6ff54 ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9078>
(cherry picked from commit 596fb88c01)
2021-02-18 14:09:03 -08:00
Samuel Pitoiset
d03634d438 radv: only apply the MRT output NaN fixup to non-meta shaders
We only want this workaround to be applied for game shaders.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4163
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9048>
(cherry picked from commit f502bdf1ab)
2021-02-18 14:09:02 -08:00
Daniel Schürmann
8e8ba3402a aco: fix shared VGPR allocation on RDNA2
VGPRs are now allocated in blocks of 8 normal
or 16 shared VGPRs, respectively.

Fixes: 14a5021aff ('aco/gfx10: Refactor of GFX10 wave64 bpermute.')

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8921>
(cherry picked from commit bacc3b36f5)
2021-02-18 14:07:19 -08:00
Bas Nieuwenhuizen
67db4ad07f radv: Ignore WC flags for VRAM.
Otherwise there might be buffers for which we don't have a type.

Fixes: 7262c743dc ("radv: Determine memory type for import based on fd.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4280
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8996>
(cherry picked from commit 045a85085a)
2021-02-18 12:59:40 -08:00
Rhys Perry
339c9e52e3 aco: add fallback algorithm in get_reg()
The generated code is often terrible, but the situations where this is
needed are rare.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8881>
2021-02-18 20:12:41 +00:00
Rhys Perry
a6dd1fda4e aco: do not flag all blocks WQM to ensure we enter all nested loops in WQM
This should no longer be necessary since the mark_block_wqm() we use to
flag break conditions as WQM now adds block to the worklist. With them
added to the worklist, get_block_needs() will add WQM to block_needs.

Adding WQM to block_needs here without adding the block to the worklist
(like we do here) can cause issues because it does not ensure that the
predecessors' branches are in WQM (needed for it to be possible to
transition to WQM in the block). This happened in an Overwatch shader.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 661922f6ac ("aco: add block to worklist in mark_block_wqm()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4066
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8446>
(cherry picked from commit f0074a6f05)
2021-02-10 15:11:14 -08:00
Bas Nieuwenhuizen
0bb75ccf28 radv: Fix vram override with fully visible VRAM.
Fixes: cf2eebdf4f ("radv,gallium: Add driconf option to reduce advertised VRAM size.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8915>
(cherry picked from commit bd7d8a77e9)
2021-02-10 15:11:13 -08:00
Bas Nieuwenhuizen
a1248b811e radv: Improve spilling on discrete GPUs.
The linked bug gets better performance and I personally verified
better spilling performance on HZD so let us make this step for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3183
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3698
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6833>
(cherry picked from commit 862b6a9a97)
2021-02-10 15:11:07 -08:00
Mike Blumenkrantz
0ea5fe87ae radv: zero the bo descriptor array when allocating a new set
this must be reset to avoid issues when using VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT_EXT
when some descriptors in the set may not have been bound

fixes #4219

Fixes: 126d5adb11 ("radv: Use host memory pool for non-freeable descriptors.")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>
(cherry picked from commit 09ce403b2d)
2021-02-10 15:11:06 -08:00
Mike Blumenkrantz
bde380bde9 radv: null bo list pointer for null descriptors on update
failing to unset any existing pointers here leads to stale bo entries in
the list and then the kernel rejecting the cmdbuf with ENOENT

Fixes: 126d5adb11 ("radv: Use host memory pool for non-freeable descriptors.")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8840>
(cherry picked from commit 2f534c2e2e)
2021-02-10 15:11:06 -08:00
Rhys Perry
bb2aea8ded aco: always set exec_live=false
Register demand calculation for exec masks doesn't always match
get_live_changes() and get_temp_registers(). For now, just set
exec_live=false.

fossil-db (GFX10.3):
Totals from 108230 (77.64% of 139391) affected shaders:
SGPRs: 5759658 -> 5756818 (-0.05%); split: -0.08%, +0.03%
VGPRs: 4061104 -> 4061248 (+0.00%); split: -0.00%, +0.01%
SpillSGPRs: 14114 -> 15198 (+7.68%); split: -0.10%, +7.78%
CodeSize: 266548396 -> 266603288 (+0.02%); split: -0.01%, +0.03%
MaxWaves: 1390885 -> 1390855 (-0.00%); split: +0.00%, -0.00%
Instrs: 50983353 -> 50992972 (+0.02%); split: -0.02%, +0.04%
Cycles: 1733042048 -> 1735443264 (+0.14%); split: -0.02%, +0.16%
VMEM: 41933625 -> 41914722 (-0.05%); split: +0.04%, -0.09%
SMEM: 7197675 -> 7197789 (+0.00%); split: +0.16%, -0.16%
VClause: 1050885 -> 1050978 (+0.01%); split: -0.02%, +0.03%
SClause: 2074913 -> 2071844 (-0.15%); split: -0.23%, +0.08%
Copies: 3181464 -> 3188125 (+0.21%); split: -0.38%, +0.59%
Branches: 1127526 -> 1127716 (+0.02%); split: -0.10%, +0.12%
PreSGPRs: 3376687 -> 3586076 (+6.20%); split: -0.00%, +6.20%
PreVGPRs: 3339740 -> 3339811 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8807>
(cherry picked from commit d1f93261b1)
2021-02-10 15:11:02 -08:00
Samuel Pitoiset
60f12ee177 radv: fix waiting on the last enabled RB for occlusion queries
Wait on the last enabled RB, not the last RB. This fixes GPU hangs
because the GPU was waiting forever.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4212
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8836>
(cherry picked from commit 7e47fe9a94)
2021-02-10 15:10:59 -08:00
Rhys Perry
9cab7e3988 radv: correctly enable WGP_MODE for tessellation control
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8811>
(cherry picked from commit 0602d4ec69)
2021-02-04 14:08:35 -08:00
Rhys Perry
a0fe068d9e radv: correctly enable WGP_MODE for NGG and GS
Previously, we would set WGP_MODE on GFX10+ and then only on GFX10.
Because we used bitwise or, the result was WGP_MODE being set on GFX10+.

We also set the wrong bit, S_00B848_WGP_MODE instead of S_00B228_WGP_MODE.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8811>
(cherry picked from commit 2338e4ad36)
2021-02-04 14:08:34 -08:00
Rhys Perry
ed4d51e33a radv: round-up num_records division in radv_flush_vertex_descriptors
Vertex attribute bounds checking is supposed to be done per-attribute:
   is_oob = index * stride + attrib_offset + attrib_size > buffer_size
but we were obtaining num_records by dividing the buffer size by the
stride, making it per-vertex:
   is_oob = index * stride + (stride - 1) >= buffer_size

An example from Dead Cells (Wine) is:
attribute bindings: 0, 1, 2
attribute formats: r32g32, r32g32, r32g32b32a32
attribute offsets: 0, 0, 0
binding buffers: all the same buffer
binding offsets: 0, 8, 16
binding sizes: 128, 120, 112
binding strides: 32, 32, 32

Workaround this issue without switching to per-attribute descriptors by
rounding up the division. This is still incorrect, but it should now no
longer consider in-bounds attributes out-of-bounds.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3796
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4199
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8835>
(cherry picked from commit 56cd79b63d)
2021-02-04 14:08:34 -08:00
Dave Airlie
3dd7df6c24 radv: move queue object to a common base object
This is needed to use the new dispatch layer code.  While we're here, we
clean up the context on the error path.

Fixes: 9b1138e3f0 "radv: implement VK_EXT_private_data"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8676>
(cherry picked from commit f695957421)
2021-02-03 09:15:35 -08:00
Bas Nieuwenhuizen
6753936d0e radv: Do not hash vk_object_base in descriptor set layout.
It contains potentially pointer-y stuff.

Fixes: 178adfa6a8 ("radv: use the base object struct types")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8809>
(cherry picked from commit 1eaefe6cfd)
2021-02-03 09:15:34 -08:00
Samuel Pitoiset
26f5850810 radv: fix centroid with VRS coarse shading
Ported from RadeonSI.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8775>
(cherry picked from commit 718c4726f3)
2021-02-01 09:07:44 -08:00
Daniel Schürmann
1c4a92a7cd aco: fix nir_intrinsic_ballot with wave32
Found by inspection.

Fixes: 21db083504 ('aco/wave32: Allow setting the subgroup ballot size to 64-bit.')

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8703>
(cherry picked from commit b06609e903)
2021-01-27 10:10:50 -08:00
Timur Kristóf
172ae30602 radv: Only enable sparse features on Polaris and newer.
On Fiji, the CTS image can cause a hang when these are enabled.
Let's enable them for Polaris and newer only, for now.

Gitlab: #4136
Fixes: 9f43b44bf0
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8646>
(cherry picked from commit 3c03fa5801)
2021-01-27 10:10:49 -08:00
Daniel Schürmann
bd506cb19c aco/optimizer: don't copy-prop logical phis
This is dangerous w.r.t. LCSSA-phis.

Totals from 746 (0.54% of 139391) affected shaders (Navi10):
CodeSize: 8592160 -> 8568156 (-0.28%); split: -0.30%, +0.02%
MaxWaves: 5172 -> 5171 (-0.02%); split: +0.02%, -0.04%
Instrs: 1653949 -> 1648489 (-0.33%); split: -0.36%, +0.03%
Cycles: 49474892 -> 49329224 (-0.29%); split: -0.33%, +0.03%
VMEM: 137574 -> 137421 (-0.11%); split: +0.18%, -0.29%
SMEM: 42391 -> 42439 (+0.11%); split: +0.12%, -0.01%
VClause: 26946 -> 26943 (-0.01%)
Copies: 130902 -> 126176 (-3.61%); split: -4.05%, +0.43%
Branches: 54891 -> 54556 (-0.61%); split: -0.64%, +0.03%
PreVGPRs: 53941 -> 53939 (-0.00%)

This has a slight effect on RA due to affinity changes.

Cc: 20.3
Cc: 21.0

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8260>
(cherry picked from commit cd870d1b6a)
2021-01-26 09:18:44 -08:00
Daniel Schürmann
215266234b aco/optimizer: don't propagate subdword temps of different size
It could happen that due to inconsistent copy-propagation

  v1 = p_parallelcopy v2b

instructions were left after optimization on GFX8.

Cc: 20.3
Cc: 21.0

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8260>
(cherry picked from commit 856fd4750d)
2021-01-26 09:18:38 -08:00
David McFarland
f0bb52cf52 radv: fix divide by zero with no tesselation params
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7878>
(cherry picked from commit e3f56601e0)
2021-01-26 09:09:12 -08:00
Bas Nieuwenhuizen
fd5c91e656 radv: Use stricter HW resolve swizzle compat check.
D and linear are both DISPLAY micro tiling according to ac_surface
but don't work together. This fixes an issue with GFX9+.

This fixes the SkQP WritePixelsNonTexture_Gpu test.

Fixes: 69ea473eeb ("amd/addrlib: update to the latest version")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8665>
(cherry picked from commit 12ce72fcfc)

Conflicts:
	src/amd/vulkan/radv_meta_resolve.c
2021-01-26 09:08:43 -08:00
Samuel Pitoiset
51ff50ef30 radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
We were incorrectly shifting the input VGPRs for the instance ID
for chips affected by the LS VGPR init bug (ie. Vega10 and Raven).

When there is no HS threads, the hardware loads the LS VGPR
starting from VGPR 0, so they should be shifted by two.

This fixes some sort of vertex explosion with Squad, Visage, Barn
Finders and probably more titles that use tessellation. Note that
only Vega10 and Raven were affected by this bug.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4129
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3311
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8694>
(cherry picked from commit bb8f87088c)
2021-01-25 10:07:15 -08:00
Samuel Pitoiset
c849e15c44 radv: fix separate depth/stencil layout in render pass
We used to select the stencil layout even if we should have selected
the depth/stencil one.

Fixes: e4c8491bdf ("radv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8552>
(cherry picked from commit 3ef89b245e)
2021-01-22 09:02:46 -08:00
Samuel Pitoiset
291eebfaa4 radv: inhibit clock gating when tracing with SQTT
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8616>
(cherry picked from commit 5b5cd18853)
2021-01-22 09:01:42 -08:00
Samuel Pitoiset
acfd179fe3 radv: fix overflow when computing the SQTT buffer size
With RADV_THREAD_TRACE_BUFFER_SIZE=1073741824, the computed size
will overflow and be 4096 instead of 4294967296.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8616>
(cherry picked from commit c40ea24ee0)
2021-01-22 09:01:41 -08:00
Rhys Perry
31ef7441cd aco: don't consider a phi trivial if same's register doesn't match the def
For example:
 s2: %688:s[32-33] = p_linear_phi %3:s[10-11], %688:s[32-33]
would have been considered trivial.

This might happen due to parallelcopies when assigning phi registers.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 69b6069dd2 ("aco: refactor try_remove_trivial_phi() in RA")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8645>
(cherry picked from commit 824eba2148)
2021-01-22 09:01:41 -08:00
Samuel Pitoiset
eaefaa9610 radv: fix a sync issue with geometry shader primitives query on GFX10+
When NGG is used, the hw can't know the number of geometry shader
primitives. To fix that, the NGG geometry shader accumulates itself
the number of primitives by using an atomic operation directly to GDS.

Then, begin/query copy the start/stop values from GDS to the
query pool buffer using a PS_DONE event. This was actually wrong
because PS_DONE is completely asynchronous to everything and executed
when the preceding draws finish pixel shaders.

Fix this by using a COPY_DATA packet which is synced with CP. This
fixes random failures on Sienna Cichlid with
dEQP-VK.query_pool.statistics_query.*.geometry_shader_primitives.*.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8590>
(cherry picked from commit 085e2ce3d4)
2021-01-21 13:26:36 -08:00
Rhys Perry
8ba9bb139c radv,aco: don't use MUBUF for multi-channel loads on GFX8 with robustness2
Fixes several dEQP-VK.robustness.robustness2.* tests on GFX8. Generations
other than GFX8 don't fail the tests because bounds-checking is done using
the index (making it per-vertex).

fossil-db (Polaris):
Totals from 1387 (0.99% of 140385) affected shaders:
(no statistics affected)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 03a0d39366 ("aco: use MUBUF in some situations instead of splitting vertex fetches")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7834>
(cherry picked from commit 914c61d6c0)
2021-01-21 13:26:34 -08:00
Samuel Pitoiset
664f6976b2 radv: flush L2 for images affected by the pipe misaligned issue on GFX10+
In some rare cases, L2 needs to be flushed if an image is affected
by the pipe misaligned issue. This is roughly based on AMDVLK.

I confirmed that disabling TC-compat HTILE, and respectively DCC,
for the relevant images also fixes the regressions below.

This fixes some regressions introduced with L2 coherency for
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_* and for
dEQP-VK.renderpass2.suballocation.multisample_resolve.*.

Fixes: 4a783a3c78 ("radv: Use L2 coherency on GFX9+.")
Co-Authored-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8557>
(cherry picked from commit 4c99d6ff54)
2021-01-20 11:11:03 -08:00
Samuel Pitoiset
0acff8c6f2 radv: restore invalidating the vector cache for internal meta operations
The driver used to invalidate the vector cache for meta operations
but this has been removed and I think it should be restored to fix
a bunch of regressions on GFX8.

This probably needs to be cleaned up but this is a hotfix.

This fixes a bunch of regressions and flakes on GFX8 like
dEQP-VK.pipeline.multisample.sample_locations_ext.draw.color.samples_4.*.

Fixes: 8f8d72af55 ("radv: Use access helpers for flushing with meta operations.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8573>
(cherry picked from commit 8882abe47e)
2021-01-20 11:11:03 -08:00
Rhys Perry
b98745871b aco: fix convert_to_SDWA() check in add_subdword_definition()
v_or_b32 with a v2b definition should use SDWA if is_partial=true.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 56345b8c61 ("aco: allow reading/writing upper halves/bytes when possible")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8577>
(cherry picked from commit fcda9b6737)
2021-01-20 09:22:16 -08:00
Samuel Pitoiset
3994f5db48 radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9
This restores the previous logic because L2 coherency was fully
implemented. It appears that flushing L2 metadata with a CS_DONE
event hangs.

This fixes GPU hangs with Monster Hunter World.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8566>
(cherry picked from commit c3ac6f7cd7)
2021-01-20 09:22:16 -08:00
Bas Nieuwenhuizen
380c7edbc2 radv: Do not use a pipe offset for aliased sparse images.
Otherwise the offset might not match between the images that are
aliased.

Fixes: e553ea51e8 ("radv: Create sparse images.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4072
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8535>
(cherry picked from commit af1aef10f9)
2021-01-20 09:22:16 -08:00
Bas Nieuwenhuizen
98706b7754 ac/surface: Fix GFX9 sparse mip info.
Used the wrong offset & pitch for gfx9.

Fixes: 50bafb85ec ("ac/surf: Add sparse texture info to radeon_surf.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4072
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8526>
(cherry picked from commit c28469bae1)
2021-01-20 09:22:16 -08:00
Samuel Pitoiset
73ea60139d radv: do not invalidate the L2 metadata cache on compute queues
The flush VA space was only allocated for command buffers on the
graphics queue. Also, the ZPASS_DONE event should never be emitted
on compute queues because it hangs.

Invalidating the L2 metadata cache is only required for coherency
between the RBs and L2, so only on the graphics queue.

The L2 cache is invalidated at beginning of any IBs and that should
also invalidate the L2 metadata cache for compute anyways.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8494>
(cherry picked from commit c6849f9687)
2021-01-15 09:19:51 -08:00
Rhys Perry
82e845ba67 nir/loop_unroll: unroll more aggressively if it can improve load scheduling
Significantly improves performance of a Control compute shader. Also seems
to increase FPS at the very start of the game by ~5% (RX 580, 1080p,
medium settings, no MSAA).

fossil-db (Sienna):
Totals from 81 (0.06% of 139391) affected shaders:
SGPRs: 3848 -> 4362 (+13.36%); split: -0.99%, +14.35%
VGPRs: 4132 -> 4648 (+12.49%)
CodeSize: 275532 -> 659188 (+139.24%)
MaxWaves: 986 -> 906 (-8.11%)
Instrs: 54422 -> 126865 (+133.11%)
Cycles: 1057240 -> 750464 (-29.02%); split: -42.61%, +13.60%
VMEM: 26507 -> 61829 (+133.26%); split: +135.56%, -2.30%
SMEM: 4748 -> 5895 (+24.16%); split: +31.47%, -7.31%
VClause: 1933 -> 6802 (+251.89%); split: -0.72%, +252.61%
SClause: 1179 -> 1810 (+53.52%); split: -3.14%, +56.66%
Branches: 1174 -> 1157 (-1.45%); split: -23.94%, +22.49%
PreVGPRs: 3219 -> 3387 (+5.22%); split: -0.96%, +6.18%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6538>
(cherry picked from commit dfe429eb41)
2021-01-13 11:24:15 -08:00
Daniel Schürmann
3aaf5188fe aco: remove divergent branches which only jump over very few instructions
Totals from 18436 (13.23% of 139391) affected shaders (NAVI10):
CodeSize: 138428504 -> 138172588 (-0.18%)
Instrs: 26605127 -> 26541176 (-0.24%)
Cycles: 1624994088 -> 1622461620 (-0.16%)
VMEM: 3689892 -> 3689102 (-0.02%)
SMEM: 1131767 -> 1131761 (-0.00%)
Branches: 851796 -> 787852 (-7.51%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7814>
(cherry picked from commit 288032a873)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
0d63d9463e aco: propagate swizzles when optimizing packed clamp & fma
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 412291ddef)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
71a58f02e5 aco: optimize v_pk_fma_f16 -> v_pk_fmac_f16 on GFX10
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 6ecbccfb23)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
4562f9f894 aco: optimize packed fneg
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit b03be30e07)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
3760fdf7e6 aco: optimize packed clamp
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit e3790fc458)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
28df87bbe2 aco: optimize packed mul+add to v_pk_fma_f16
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit a9fd9187e8)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
7f40dc9760 aco: simplify multiply-add combining
When both operands of a v_sub (same apply for v_add) are mul and one
already uses clamp/omod, pick the other operand to get a chance to
combine to a MAD.

No fossils-db changes.

Co-authored-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 01134b0bfe)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
12c0bfaaf9 radv: vectorize 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit fcd2ef23e5)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
6a7552aa10 aco: emit packed 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 454bbf8f23)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
01a7662154 aco: create helpers to emit vop3p instructions
Also make get_alu_src() capable to return
unswizzled multi-component SGPR sources.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 5ad52ac906)
2021-01-13 11:24:11 -08:00
Daniel Schürmann
65288fe496 aco: change usesModifiers() considering opsel_hi on packed instructions
opsel_hi == 1 means that the high operand selects the
high bits of the input, which is the normal behavior.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
(cherry picked from commit 036a369f46)
2021-01-13 11:24:11 -08:00