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radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9

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We were incorrectly shifting the input VGPRs for the instance ID
for chips affected by the LS VGPR init bug (ie. Vega10 and Raven).

When there is no HS threads, the hardware loads the LS VGPR
starting from VGPR 0, so they should be shifted by two.

This fixes some sort of vertex explosion with Squad, Visage, Barn
Finders and probably more titles that use tessellation. Note that
only Vega10 and Raven were affected by this bug.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4129
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3311
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8694>
(cherry picked from commit bb8f87088c)
This commit is contained in:
Samuel Pitoiset 2021-01-25 13:42:35 +01:00 • committed by Dylan Baker
parent f59b95c7b3
commit 51ff50ef30
3 changed files with 3 additions and 3 deletions
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2
.pick_status.json
View file

@ -49,7 +49,7 @@
"description": "radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

2
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -11188,7 +11188,7 @@ void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
/* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
get_arg(ctx, ctx->args->ac.vs_rel_patch_id),
get_arg(ctx, ctx->args->ac.vertex_id),
get_arg(ctx, ctx->args->ac.instance_id),
ls_has_nonzero_hs_threads);
Temp vs_rel_patch_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),

2
src/amd/vulkan/radv_nir_to_llvm.c
View file

@ -3797,7 +3797,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
ctx->ac.i32_0, "");
ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
ac_get_arg(&ctx->ac, ctx->args->ac.vs_rel_patch_id),
ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
ctx->abi.instance_id, "");
ctx->vs_rel_patch_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),