fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 13:18:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: correctly enable WGP_MODE for NGG and GS

Browse source 
Previously, we would set WGP_MODE on GFX10+ and then only on GFX10.
Because we used bitwise or, the result was WGP_MODE being set on GFX10+.

We also set the wrong bit, S_00B848_WGP_MODE instead of S_00B228_WGP_MODE.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8811>
(cherry picked from commit 2338e4ad36)
This commit is contained in:
Rhys Perry 2021-02-01 15:01:57 +00:00 • committed by Dylan Baker
parent ed4d51e33a
commit a0fe068d9e
2 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -256,7 +256,7 @@
"description": "radv: correctly enable WGP_MODE for NGG and GS",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

8
src/amd/vulkan/radv_shader.c
View file

@ -1029,8 +1029,7 @@ static void radv_postprocess_config(const struct radv_device *device,
S_00B02C_EXCP_EN(excp_en);
break;
case MESA_SHADER_GEOMETRY:
config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
S_00B22C_EXCP_EN(excp_en);
break;
@ -1087,7 +1086,7 @@ static void radv_postprocess_config(const struct radv_device *device,
* disable exactly 1 CU per SA for GS.
*/
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
S_00B848_WGP_MODE(pdevice->rad_info.chip_class == GFX10);
S_00B228_WGP_MODE(pdevice->rad_info.chip_class == GFX10);
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_LDS_SIZE(config_in->lds_size) |
S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
@ -1122,7 +1121,8 @@ static void radv_postprocess_config(const struct radv_device *device,
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
}
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
S_00B228_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
} else if (pdevice->rad_info.chip_class >= GFX9 &&