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aco/wave32: Allow setting the subgroup ballot size to 64-bit.

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Previously, it would only work when the ballot size was set to the
lane mask. This patch makes is possible to set the ballot size
to either 32-bit or 64-bit for wave32 mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
This commit is contained in:
Timur Kristóf 2019-11-28 10:41:19 +01:00 • committed by Daniel Schürmann
parent ed815d503e
commit 21db083504
2 changed files with 8 additions and 4 deletions
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11
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -5709,18 +5709,23 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
Definition tmp = bld.def(dst.regClass());
Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
if (instr->src[0].ssa->bit_size == 1) {
assert(src.regClass() == bld.lm);
bld.sop2(Builder::s_and, tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
} else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
bld.vopc(aco_opcode::v_cmp_lg_u32, tmp, Operand(0u), src);
bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
} else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
bld.vopc(aco_opcode::v_cmp_lg_u64, tmp, Operand(0u), src);
bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
} else {
fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr);
fprintf(stderr, "\n");
}
if (dst.size() != bld.lm.size()) {
/* Wave32 with ballot size set to 64 */
bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
}
emit_wqm(ctx, tmp.getTemp(), dst);
break;
}

1
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -294,7 +294,6 @@ void init_context(isel_context *ctx, nir_shader *shader)
break;
case nir_intrinsic_ballot:
type = RegType::sgpr;
size = lane_mask_size;
break;
case nir_intrinsic_load_sample_id:
case nir_intrinsic_load_sample_mask_in: