Within the driver buffers are treated as 2D as sampling them as 1D
will run into HW restrictions on max size.
The compiler does the same however for atomic image ops the address
is manually calculated and doing this via the 2D path leads to
incorrect offsets.
The fix is to treat buffers as 1D for atomic ops which calculates
the correct offsets for the operations.
Fix deqp:
dEQP-VK.image.atomic_operations.add.buffer.*
dEQP-VK.image.atomic_operations.and.buffer.*
dEQP-VK.image.atomic_operations.compare_exchange.buffer.*
dEQP-VK.image.atomic_operations.dec.buffer.*
dEQP-VK.image.atomic_operations.exchange.buffer.*
dEQP-VK.image.atomic_operations.inc.buffer.*
dEQP-VK.image.atomic_operations.max.buffer.*
dEQP-VK.image.atomic_operations.min.buffer.*
dEQP-VK.image.atomic_operations.or.buffer.*
dEQP-VK.image.atomic_operations.sub.buffer.*
dEQP-VK.image.atomic_operations.xor.buffer.*
Fixes: 6dc5e1e109 ("pco: fully support Vulkan 1.2 image atomics")
Signed-off-by: Nick Hamilton <nick.hamilton@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
(cherry picked from commit 079377c767)
Conflicts:
src/imagination/ci/bxs-4-64-fails.txt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS state should be emitted as part
of TU_DYNAMIC_STATE_RB_DEPTH_CNTL along with other depth state, and not as
part of dynamic stencil state.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 979cf7bac0 ("tu: Merge depth/stencil draw states")
(cherry picked from commit 3cb4776ede)
Conflicts:
src/freedreno/vulkan/tu_pipeline.cc
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Turns out ir3 isn't enforcing this itself.
Fixes: c323848b0b ("ir3, tu: Plumb through support for per-shader robustness")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
(cherry picked from commit 455b692e4f)
Conflicts:
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Each node has their own opacity bits, so we don't need to track these
opacity flags at header level.
This commit also fixes the instance flag. Instance flag is 8bit wide,
but we were always using 4 lower bits.
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
(cherry picked from commit 8e85607130)
Conflicts:
src/intel/vulkan/bvh/encode.comp
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Fixes a bunch of new VKCTS coverage like
dEQP-VK.pipeline.monolithic.multisample.m10_resolve.resolve_cmd.d32_sfloat.depth.average.full_multilayer.no_flags
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 91a5a0f2b9)
Conflicts:
src/amd/vulkan/meta/radv_meta_resolve_cs.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
This change updates the vs_as_ls switch logic to make it
reliable. It resets the dirty flag when the switch is
happening. It uses also evergreen_emit_vs_constant_buffers()
to try to update again some of the states which could be
lost otherwise.
This change fixes some "flakes". These tests needed previously
to be executed twice to set the hardware in the proper state
for the test to pass. It also fixes the main issue of the
texture_view.view_sampling test.
This change was tested on palm and cayman. Here are the tests
which are now utterly fixed:
khr-gl4[3-6]/stencil_texturing/functional: fail pass
khr-gl4[4-6]/texture_cube_map_array/texture_size_tesselation_ev_sh: fail pass
khr-gles31/core/texture_cube_map_array/texture_size_tesselation_ev_sh: fail pass
khr-glesext/texture_cube_map_array/texture_size_tesselation_ev_sh: fail pass
Fixes: 25f96c1120 ("r600: hook up constants/samplers/sampler view for tessellation")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 9c5e15e6f5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
This matches the initialization that the proprietary driver does.
Fixes dEQP-VK.query_pool.discard.*.alpha_to_coverage* on vk cts 1.4.5
Cc: mesa-stable
Reviewed-by: Mary Guillemard <mary@mary.zone>
(cherry picked from commit 8d7f14620b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Expose DRM format modifiers via VkDrmFormatModifierPropertiesList2EXT.
VVL is one notable user.
This is required for VK_EXT_image_drm_format_modifier when
VK_KHR_format_feature_flags2 is supported.
Cc: mesa-stable
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
(cherry picked from commit e185f40fc3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Also change to use H265 constant for maxDpbSlots (both values for H264 and H265
are the same).
Fixes: ee535aa039 ("radv: video: rework maxActiveReferenceSlot/MaxDpbSlots")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
(cherry picked from commit 7607aeefa6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
The pMiColStarts/pMiRowStarts arrays from applications may have
incorrect units. Instead of using them directly, compute the tile
start positions in superblock units internally based on the tile
dimensions.
Cc: mesa-stable
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 8e9fec8e40)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
It might be that the radv_pipeline_cache_lookup_nir_handle() in
radv_ray_tracing_pipeline_cache_search() fails but we will later need the
NIR. If rt_stages[i].shader was non-NULL, then we would not have created
the NIR.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.2
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
(cherry picked from commit 89eefdcadb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
The non-dynamic members of xfb_info are already included in
sizeof(hk_passthrough_gs_key), so adding nir_xfb_info_size counts them
twice. Because of this we were including uninitialized memory in the key
in hk_handle_passthrough_gs, which is undefined behavior.
Fixes: 5bc8284816 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
(cherry picked from commit d6745b358d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
When proceeding with rendering, any transient attachment that will be used
as LRZ buffer should also be allocated. With GMEM rendering, these
attachments otherwise remained unloaded and subsequent LRZ clears produced
GPU faults.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: 764b3d9161 ("tu: Implement transient attachments and lazily allocated memory")
Fixes: #14604
(cherry picked from commit b6a049ea4b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
For mesh/task shaders, the thread payload provides a local invocation
index, but it's always linear so it doesn't give the correct value when
quad derivatives are in use.
The lowering pass where all of this is done correctly for compute
shaders assumes load_local_invocation_index will be lowered in the
backend for mesh/task, calculates the values for the quads correctly but
then avoid replacing the original intrinsic and we remain with the wrong
results.
Add an intel specific intrinsic and always lower the generic one to that
(or whatever else was calculated) to avoid ambiguities and fix the value
for quad derivatives.
Fixes future CTS tests using mesh/task shaders under:
dEQP-VK.spirv_assembly.instruction.compute.compute_shader_derivatives.*
Fixes: d89bfb1ff7 ("intel/brw: Reorganize lowering of LocalID/Index to handle Mesh/Task")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 5b48805b42)
Conflicts:
src/compiler/nir/nir_divergence_analysis.c
src/intel/compiler/brw/brw_compile_mesh.cpp
src/intel/vulkan/anv_shader_compile.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
We started allowing non-default clear colors with FCV in commit
cd8e120b97. When rendering to an image with FCV, set the fast-clear
type to ANV_FAST_CLEAR_ANY if the image properties allow such
fast-clears.
Fixes: cd8e120b97 ("anv: Allow more single subresource fast-clears with FCV")
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
(cherry picked from commit ce196c9de5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
On Xe2+, HSD 14011946253 and the related documents explain that MCS
still only supports a single clear color.
Fixes: df006bba02 ("iris: Update aux state for color fast clears (xe2)")
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
(cherry picked from commit 6c6b2d8f30)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
When changing the clear color without a fast clear, use dirty bits to
ensure that surfaces with inline clear colors are updated and that
partial resolves are done as needed.
Remove the flags at the bottom of fast_clear_color() as
blorp_fast_clear() already sets them for us.
Fixes: 64d861b700 ("iris: Skip some fast-clears even on color changes")
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
(cherry picked from commit 3b642f7456)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
From RENDER_SURFACE_STATE::AuxiliarySurfaceQPitch on BDW+,
This field must be set to an integer multiple of the Surface
Vertical Alignment
Accomplish this by aligning the height of each MCS layer to main
surface's vertical alignment. Prevents the following test group from
failing on Xe2 when a future commit enables multi-layer fast-clears in
anv:
dEQP-VK.api.image_clearing.*.
clear_color_attachment.multiple_layers.
*_clamp_input_sample_count_*
The main test I used to debug this:
dEQP-VK.api.image_clearing.core.
clear_color_attachment.multiple_layers.
a8b8g8r8_unorm_pack32_64x11_clamp_input_sample_count_2
Backport-to: 25.3
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
(cherry picked from commit eb4a581e44)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
Prevent assert failures in a future commit where Tile64 will be selected
more often.
Fixes: 42ef23ecd1 ("intel/blorp: Don't redescribe some Tile64 clears")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 6fc0e5c0aa)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39745>
