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synced 2026-02-09 20:40:28 +01:00
tu: Merge depth/stencil draw states
This removes more draw states that are commonly set together. We still have a separate draw state for RB_DEPTH_CNTL, because it depends on other things like the attachment state and depth clamp and it would be more difficult for layers like zink to use a combined depth/stencil state. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
This commit is contained in:
Connor Abbott
Marge Bot
parent
3a1f7c61b6
commit
979cf7bac0
2 changed files with 57 additions and 125 deletions
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@ -4321,31 +4321,26 @@ tu6_emit_rast(struct tu_cs *cs,
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}
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static const enum mesa_vk_dynamic_graphics_state tu_ds_state[] = {
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MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE,
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MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE,
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MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP,
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MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE,
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MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE,
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MESA_VK_DYNAMIC_DS_STENCIL_OP,
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MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE,
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MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK,
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MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK,
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MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE,
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MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
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};
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template <chip CHIP>
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static unsigned
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tu6_ds_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds,
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const struct vk_render_pass_state *rp,
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const struct vk_rasterization_state *rs)
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const struct vk_depth_stencil_state *ds)
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{
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return 4;
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return 11;
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}
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template <chip CHIP>
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static void
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tu6_emit_ds(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds,
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const struct vk_render_pass_state *rp,
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const struct vk_rasterization_state *rs)
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const struct vk_depth_stencil_state *ds)
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{
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tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CONTROL(
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.stencil_enable = ds->stencil.test_enable,
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@ -4360,6 +4355,48 @@ tu6_emit_ds(struct tu_cs *cs,
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.zpass_bf = tu6_stencil_op((VkStencilOp)ds->stencil.back.op.pass),
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.zfail_bf = tu6_stencil_op((VkStencilOp)ds->stencil.back.op.depth_fail)));
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tu_cs_emit_regs(cs, A6XX_RB_STENCILMASK(
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.mask = ds->stencil.front.compare_mask,
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.bfmask = ds->stencil.back.compare_mask));
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tu_cs_emit_regs(cs, A6XX_RB_STENCILWRMASK(
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.wrmask = ds->stencil.front.write_mask,
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.bfwrmask = ds->stencil.back.write_mask));
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tu_cs_emit_regs(cs, A6XX_RB_STENCILREF(
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.ref = ds->stencil.front.reference,
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.bfref = ds->stencil.back.reference));
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tu_cs_emit_regs(cs,
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A6XX_RB_Z_BOUNDS_MIN(ds->depth.bounds_test.min),
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A6XX_RB_Z_BOUNDS_MAX(ds->depth.bounds_test.max));
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}
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static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
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MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE,
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MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE,
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MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP,
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MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE,
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MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE,
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};
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template <chip CHIP>
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static unsigned
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tu6_rb_depth_cntl_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds,
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const struct vk_render_pass_state *rp,
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const struct vk_rasterization_state *rs)
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{
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return 2;
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}
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template <chip CHIP>
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static void
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tu6_emit_rb_depth_cntl(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds,
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const struct vk_render_pass_state *rp,
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const struct vk_rasterization_state *rs)
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{
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if (rp->attachment_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
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bool depth_test = ds->depth.test_enable;
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enum adreno_compare_func zfunc = tu6_compare_func(ds->depth.compare_op);
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@ -4390,94 +4427,6 @@ tu6_emit_ds(struct tu_cs *cs,
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}
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}
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static const enum mesa_vk_dynamic_graphics_state tu_depth_bounds_state[] = {
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MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_BOUNDS,
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};
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template <chip CHIP>
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static unsigned
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tu6_depth_bounds_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds)
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{
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return 3;
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}
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template <chip CHIP>
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static void
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tu6_emit_depth_bounds(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds)
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{
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tu_cs_emit_regs(cs,
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A6XX_RB_Z_BOUNDS_MIN(ds->depth.bounds_test.min),
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A6XX_RB_Z_BOUNDS_MAX(ds->depth.bounds_test.max));
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}
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static const enum mesa_vk_dynamic_graphics_state tu_stencil_compare_mask_state[] = {
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MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK,
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};
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template <chip CHIP>
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static unsigned
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tu6_stencil_compare_mask_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds)
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{
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return 2;
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}
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template <chip CHIP>
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static void
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tu6_emit_stencil_compare_mask(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds)
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{
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tu_cs_emit_regs(cs, A6XX_RB_STENCILMASK(
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.mask = ds->stencil.front.compare_mask,
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.bfmask = ds->stencil.back.compare_mask));
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}
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static const enum mesa_vk_dynamic_graphics_state tu_stencil_write_mask_state[] = {
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MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK,
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};
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template <chip CHIP>
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static unsigned
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tu6_stencil_write_mask_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds)
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{
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return 2;
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}
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template <chip CHIP>
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static void
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tu6_emit_stencil_write_mask(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds)
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{
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tu_cs_emit_regs(cs, A6XX_RB_STENCILWRMASK(
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.wrmask = ds->stencil.front.write_mask,
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.bfwrmask = ds->stencil.back.write_mask));
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}
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static const enum mesa_vk_dynamic_graphics_state tu_stencil_reference_state[] = {
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MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE,
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};
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template <chip CHIP>
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static unsigned
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tu6_stencil_reference_size(struct tu_device *dev,
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const struct vk_depth_stencil_state *ds)
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{
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return 2;
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}
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template <chip CHIP>
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static void
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tu6_emit_stencil_reference(struct tu_cs *cs,
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const struct vk_depth_stencil_state *ds)
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{
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tu_cs_emit_regs(cs, A6XX_RB_STENCILREF(
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.ref = ds->stencil.front.reference,
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.bfref = ds->stencil.back.reference));
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}
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static inline bool
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emit_pipeline_state(BITSET_WORD *keep, BITSET_WORD *remove,
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BITSET_WORD *pipeline_set,
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@ -4623,21 +4572,13 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder,
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builder->graphics_state.vp,
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builder->graphics_state.rp->view_mask != 0,
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pipeline->program.per_view_viewport);
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DRAW_STATE_COND(ds, TU_DYNAMIC_STATE_DS,
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DRAW_STATE(ds, TU_DYNAMIC_STATE_DS,
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builder->graphics_state.ds);
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DRAW_STATE_COND(rb_depth_cntl, TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
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attachments_valid,
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builder->graphics_state.ds,
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builder->graphics_state.rp,
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builder->graphics_state.rs);
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DRAW_STATE(depth_bounds, TU_DYNAMIC_STATE_DEPTH_BOUNDS,
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builder->graphics_state.ds);
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DRAW_STATE(depth_bounds, TU_DYNAMIC_STATE_DEPTH_BOUNDS,
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builder->graphics_state.ds);
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DRAW_STATE(stencil_compare_mask, TU_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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builder->graphics_state.ds);
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DRAW_STATE(stencil_write_mask, TU_DYNAMIC_STATE_STENCIL_WRITE_MASK,
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builder->graphics_state.ds);
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DRAW_STATE(stencil_reference, TU_DYNAMIC_STATE_STENCIL_REFERENCE,
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builder->graphics_state.ds);
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DRAW_STATE_COND(patch_control_points,
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TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
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pipeline_contains_all_shader_state(pipeline),
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@ -4811,19 +4752,13 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd)
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&cmd->vk.dynamic_graphics_state.vp,
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cmd->state.vk_rp.view_mask != 0,
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cmd->state.per_view_viewport);
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DRAW_STATE_COND(ds, TU_DYNAMIC_STATE_DS,
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DRAW_STATE(ds, TU_DYNAMIC_STATE_DS,
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&cmd->vk.dynamic_graphics_state.ds);
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DRAW_STATE_COND(rb_depth_cntl, TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
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cmd->state.dirty & TU_CMD_DIRTY_SUBPASS,
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&cmd->vk.dynamic_graphics_state.ds,
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&cmd->state.vk_rp,
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&cmd->vk.dynamic_graphics_state.rs);
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DRAW_STATE(depth_bounds, TU_DYNAMIC_STATE_DEPTH_BOUNDS,
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&cmd->vk.dynamic_graphics_state.ds);
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DRAW_STATE(stencil_compare_mask, TU_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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&cmd->vk.dynamic_graphics_state.ds);
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DRAW_STATE(stencil_write_mask, TU_DYNAMIC_STATE_STENCIL_WRITE_MASK,
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&cmd->vk.dynamic_graphics_state.ds);
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DRAW_STATE(stencil_reference, TU_DYNAMIC_STATE_STENCIL_REFERENCE,
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&cmd->vk.dynamic_graphics_state.ds);
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DRAW_STATE_COND(patch_control_points,
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TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
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cmd->state.dirty & TU_CMD_DIRTY_PIPELINE,
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@ -24,12 +24,9 @@ enum tu_dynamic_state
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TU_DYNAMIC_STATE_RAST,
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TU_DYNAMIC_STATE_DEPTH_BIAS,
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TU_DYNAMIC_STATE_BLEND_CONSTANTS,
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TU_DYNAMIC_STATE_DEPTH_BOUNDS,
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TU_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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TU_DYNAMIC_STATE_STENCIL_WRITE_MASK,
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TU_DYNAMIC_STATE_STENCIL_REFERENCE,
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TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
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TU_DYNAMIC_STATE_DS,
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TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
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TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
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TU_DYNAMIC_STATE_VB_STRIDE,
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TU_DYNAMIC_STATE_BLEND,
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TU_DYNAMIC_STATE_VERTEX_INPUT,
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