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iris: Set missing flags on clear color changes

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When changing the clear color without a fast clear, use dirty bits to
ensure that surfaces with inline clear colors are updated and that
partial resolves are done as needed.

Remove the flags at the bottom of fast_clear_color() as
blorp_fast_clear() already sets them for us.

Fixes: 64d861b700 ("iris: Skip some fast-clears even on color changes")
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37660>
This commit is contained in:
Nanley Chery 2025-10-02 14:34:57 -04:00 • committed by Marge Bot
parent eb4a581e44
commit 3b642f7456
1 changed files with 22 additions and 6 deletions
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28
src/gallium/drivers/iris/iris_clear.c
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@ -383,9 +383,28 @@ fast_clear_color(struct iris_context *ice,
PIPE_CONTROL_RENDER_TARGET_FLUSH);
}
/* Update the clear color now that previous rendering is complete. */
if (color_changed && res->aux.clear_color_bo)
iris_resource_update_indirect_color(batch, res);
if (color_changed) {
if (devinfo->ver <= 12) {
/* A new clear color may require partial resolves later on. */
ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES;
ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
}
if (devinfo->ver >= 20) {
/* The clear pixel is updated by hardware during fast clears. */
assert(batch->screen->isl_dev.ss.clear_color_state_size == 0);
assert(batch->screen->isl_dev.ss.clear_value_size == 0);
} else if (devinfo->ver >= 11) {
/* Update dwords used for rendering and sampling. */
assert(batch->screen->isl_dev.ss.clear_color_state_size > 0);
iris_resource_update_indirect_color(batch, res);
} else {
/* We've flagged surface states with inline clear colors as dirty. */
assert(batch->screen->isl_dev.ss.clear_value_size > 0);
assert(ice->state.stage_dirty & IRIS_ALL_STAGE_DIRTY_BINDINGS);
}
}
/* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear is redundant
* and can be skipped.
@ -468,9 +487,6 @@ fast_clear_color(struct iris_context *ice,
box->depth, devinfo->ver < 20 ?
ISL_AUX_STATE_CLEAR :
ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
return;
}
static void