Commit graph

84833 commits

Author SHA1 Message Date
Sirisha Gandikota
1ab92d80a8 aubinator: Make gen_disasm_disassemble handle split sends
Skylake adds new SENDS and SENDSC opcodes, which should be
handled in the send-with-EOT check. Make an is_send() helper
that checks if the opcode is SEND/SENDC/SENDS/SENDSC (Ken)

v2: Make is_send() much more crispier, Mix declaration and
code to make the code compact (Ken)

Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-13 16:32:39 -07:00
Sirisha Gandikota
5d2440532f aubinator: Simplify print_dword_val() method
Remove the float/dword union and use the iter->p[f->start / 32]
directly as printf formatter %08x expects uint32_t (Ken)

v2: Make the cleanup much more crispier (Ken)

Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-13 16:32:24 -07:00
Jason Ekstrand
1eebb60917 anv/image: Set correct base_array_layer and array_len for storage images
Since Vulkan doesn't allow single-slice 3D storage images, we need to just
set the base_array_layer and array_len to the full size of the 3-D LOD.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-13 14:45:49 -07:00
Jason Ekstrand
106709db7b Revert "intel/isl: Ignore base_array_layer and array_len for 3D storage..."
This reverts commit 3943888c94.  It turns out
that commit was pretty-much bogus since it breaks binding a 3-D texture as a
2-D storage image.  The correct fix for the Vulkan CTS tests needs to be in
the Vulkan driver itself rather than ISL.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-13 14:45:15 -07:00
Jason Ekstrand
330104464f anv: Use blorp for doing MSAA resolves
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-13 12:40:13 -07:00
Jason Ekstrand
6bcb1f753e anv: Use blorp for ClearColorImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-13 12:40:13 -07:00
Jason Ekstrand
57e87862eb anv: Delete meta_blit2d
Everything that we were once using the blit2d framework for is now done
with blorp.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-13 12:40:13 -07:00
Jason Ekstrand
36286ccb96 anv/blorp: Add a gcd_pow2_u64 helper and use it for buffer alignments
This is a lot cleaner and easier to read than the old piles of if
statements.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-09-13 12:40:13 -07:00
Jason Ekstrand
af5d30de55 anv: Use blorp for CopyBuffer and UpdateBuffer
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-09-13 12:40:13 -07:00
Jason Ekstrand
0f1ca5407a anv: Use blorp for CopyImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
58593f24cb anv: Use blorp for CopyBufferToImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
f07f44a5bc anv: Use blorp for CopyImageToBuffer
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
9f44745eca anv: Use blorp to implement VkBlitImage
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
52fa3e8347 anv: Make image_get_surface_for_aspect_mask const
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
8f780af968 anv: Add initial blorp support
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
1fe8bf82b2 intel/anv: Use #defines for all __gen_ helpers
This allows us to #undef them later if we don't want them to persist

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
4a6c9e20b8 anv: Generalize emit_urb_setup
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
8cb144bd93 anv/pipeline: Roll compute_urb_partition into emit_urb_setup
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
823ab83432 intel/blorp: Use #defines for all __gen_ helpers
This allows us to #undef them later if we don't want them to persist

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
c0b9776cd6 intel/isl: Divide QPitch by 2 for 3-D stencil textures on SKL+
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
00e79cec99 isl/state: Don't set QPitch for GEN4_3D surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
cb780c9ccf intel/blorp: Rework alloc_binding_table
The original blorp_alloc_binding_table helper was supposed to return the
binding table offset and map along with the surface state maps.  This isn't
quite what we want, however.  What we really want is the binding table
offsets, surface state offsets, and surface state maps.  In the GL driver,
the binding table map *is* an array of surface state offsets.  However, in
Vulkan, this isn't quite true as the entries in the binding table are
surface state offsets combined with another binding table block offset.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-13 12:40:11 -07:00
Marek Olšák
524fd55d2d tgsi/scan: don't set interp flags for inputs only used by INTERP instructions
radeonsi depends on the interp flags a little bit too much.

This fixes 9 randomly failing tests:
  GL45-CTS.shader_multisample_interpolation.render.interpolate_at_centroid.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
15a127bc2c radeonsi: fix FP64 UBO loads with indirect uniform block indexing
No known tests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
35d284d08e winsys/amdgpu: don't assume GTT if the VRAM flag isn't set
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
6df872df59 radeonsi: clean up CP DMA emit code
Unify the clear and copy paths, clean up the definitions.
It looks more like a rework. It's a preparation for GDS support,
which might or might not come.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
84860dd0bb radeonsi: print the IB and buffer list in VM fault reports
This is a fallout from reworking the debug flags.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
fd69fa65a8 radeonsi: add sampler view BOs to the BO list last
If si_sampler_view_add_buffer ends up flushing, then the code
in begin_new_cs would previously have added the buffer(s) for
whatever was previously bound to that slot. Now it would add only
the new buffer.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
275c073c6a radeonsi: export SampleMask from pixel shaders at full rate
Heaven and Valley write gl_SampleMask and not Z.
Use 16_ABGR instead of 32_ABGR if Z isn't written.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
b89854b0c7 gallium/radeon: set new r600_resource fields correctly in other places too
This was missed in:

    commit 0d2e43fcb1
    Author: Marek Olšák <marek.olsak@amd.com>
    Date:   Thu Aug 18 16:30:00 2016 +0200

        gallium/radeon: derive buffer placement and flags only at initialization

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
c723acc03d ddebug: dump shader buffers and images
this was unimplemented

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
fdd457c89f ddebug: fix a crash in resource_get_handle
broken recently

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Jan Vesely
b671909d27 radeon: Don't check DCC on pipe buffers
Fixes segfaults in EG compute since:
commit 21de3be8e6
radeonsi: fix texture format reinterpretation with DCC

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-13 14:23:26 -04:00
Andy Furniss
304f70536a vl/util: Fix YV12/I420 convert to NV12 U/V reversal
Fix VAAPI YV12/I420 convert to NV12 U/V reversal.
Input order is YVU when this is called.

Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2016-09-13 13:58:40 -04:00
Jason Ekstrand
6ac469a6c3 anv/allocator: Use VG_NOACCESS_WRITE in anv_bo_pool_free
Previously, we were relying on the fact that VALGRIND_MEMPOOL_FREE came
later on in the function to prevent "link->bo = bo" from causing an invalid
write.  However, in the case where the size requested by the user is very
small (less than sizeof(struct anv_bo)), this isn't sufficient.  Instead,
we should call VALGRIND_MEMPOOL_FREE early and then use VG_NOACCESS_WRITE.
We do, however, have to call VALGRIND_MEMPOOL_FREE after reading bo_in
because it may be stored in the bo itself.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-13 10:44:03 -07:00
Jason Ekstrand
3943888c94 intel/isl: Ignore base_array_layer and array_len for 3D storage surfaces
The time we want to restrict the Z range of a 3-D surface is when rendering
to it.  For storage surfaces, we always want he full range.  However, we
still need to set MinimumArrayElement and RenderTargetViewExtent to
sensible values so we'll just set them to the reasonable defaults we used
before we started respecting the base_array_layer and array_len.

This fixes a bunch of Vulkan CTS regressions caused by 48f195d7c6.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97790
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 10:43:21 -07:00
Jose Fonseca
62affedbed appveyor: Update winflexbison download URL.
This particular version got moved into a `old_versions` subdirectory.
2016-09-13 17:54:51 +01:00
Jason Ekstrand
a1e49be713 i965: Use blorp_copy for all copy_image operations on gen6+
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
540395bf9b i965/blorp: Add a copy_miptrees helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
d038adca0e intel/isl: Add support for RGB formats in X and Y-tiled memory
Normally, using a non-linear tiling format helps improve cache locality by
ensuring that neighboring pixels are usually close-by in memory.  For RGB
formats, this still sort-of holds, but it can also lead to rather terrible
memory access patterns where a single RGB pixel value crosses a tile
boundary and gets split into two pieces in different 4K pages.  It also
makes for some rather awkward calculations because your tile size is no
longer an even multiple of surface element size.  For these reasons, we
chose to simply never create tiled RGB images in the Vulkan driver.

The GL driver, however, is not so kind so we need to support it somehow.  I
briefly toyed with a couple of different schemes but this is the best one I
could come up with.  The fundamental problem is that a tile no longer
contains an integer number of surface elements.  I briefly considered a
couple other options but found them wanting:

 1) Using floats for the logical tile size.  This leads to potential
    rounding error problems.

 2) When presented with a RGB format, just make the tile 3-times as wide.
    This isn't so nice because now our tiles are no longer power-of-two
    size.  Also, it can force the row_pitch to be larger than needed which,
    while not strictly a problem for ISL, causes incompatibility problems
    with the way the GL driver chooses surface pitches.

The chosen method requires that you pay attention and not just assume that
your tile_info is in the units you think it is.  However, it's nice because
it provides a nice "these are the units" declaration in isl_tile_info
itself.  Previously, the tile_info wasn't usable as a stand-alone structure
because you had to also know the format.  It also forces figuring out how
to deal with inconsistencies between tiling and format back to the caller
which is good because the two different consumers of isl_tile_info really
want to deal with it differently:  Computation of the surface size wants
the fewest number of horizontal tiles possible while get_intratile_offset
is far more concerned with things aligning nicely.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
883086500b intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7
The restriction that Y-tiled surfaces must have valign == 4 only aplies to
render targets but we were applying it universally.  This causes problems
if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this
should be okay because you can't render to that format.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
54db5afd2c intel/blorp: Work in terms of logical array layers
When Ivy Bridge introduced array multisampling, someone made the decision
to do lots of stuff throughout the driver in terms of physical array layers
rather than logical array layers.  In ISL, we use logical array layers most
of the time and it really makes no sense to use physical array layers in
the blorp API.  Every time someone passes physical array layers into blorp
for an array multisampled surface, they're always divisible by the number
of samples and we divide right away.

Eventually, I'd like to rework most of the GL driver internals to use
logical array layers but that's going to be a big project and will probably
happen as part of the ISL conversion.  For now, we'll do the conversion in
brw_blorp and let blorp just use the logical layers.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
fa4627149d intel/blorp: Increase the presision of coordinate transform calculations
The result of this calculation goes into an fma() in the shader and we
would like it to be as precise as possible.  The division in particular
was a source of imprecision whenever dst1 - dst0 was not a power of two.
This prevents regressions in some of the new Vulkan CTS tests for blitting
using a filtering of NEAREST.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
c70be1ead5 intel/blorp: Add a swizzle parameter to blorp_clear
While we're here, we also re-arrange the parameters to better match the
parameter order of blorp_blit.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
ea1399aba0 intel/blorp: Make color_write_disable const and optional
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
9286f62f11 intel/blorp: Add support for clearing R9G9B9E5 surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
ab03e59867 intel/blorp: Add support for RGB destinations in copies
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
5ae8043fed intel/blorp: Add an entrypoint for doing bit-for-bit copies
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
941b4d063a intel/blorp: Pull the guts of blorp_blit into a helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
4e03edf189 intel/blorp: Stop using the X/YOffset field of RENDER_SURFACE_STATE
While it can be useful, the field has substantial limtations.  In
particular, the bittom 2 or 3 bits is missing so your offset always has to
be a multiple of 4 or 8.  While surface alignments usually work out to make
this ok, when you start trying to fake compressed surfaces as uncompressed
(which we will want to do) this falls apart.  The easiest solution is to
simply align all offsets to a tile boundary and munge the regions we're
copying to account for the intratile offset.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00