The main motivation is that no_error allows us to drop count==0 draws
at the beginning of the marshal function, instead of forwarding them
to the frontend thread. Such draws are plentiful with Viewperf.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27350>
We have to write all the same regs blob is writing or we risk using
stale reg value written by blob.
I went through blob trace again and added all missing magic regs,
I hope for the last time.
This fixes screen corruption for Mobox users and in some cases
for different emulators users. The reg which caused the issue
is HLSQ_UNKNOWN_A9AC.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27721>
I think it's better to keep the other checks (check for dmabuf, uuid,
...) as we can use them to know the features required.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
We have a situation where some drivers have all the required features,
but they are not working with gl_sharing, so we end up advertising it
wrongly. Add this cap to ensure this driver was tested to work with
cl_khr_gl_sharing.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26071>
Use the same intializing trick as in 27d5543: first we initialize our
properties struct to { false }, then we fill the fields in one by one.
C++ does not allow assigning to an array from an initializer list, so
the properties exposed as an array in the struct are initialized either
one by one, or assigned in a chain.
As the properties are initialized at init time, move tu_get_properties
and tu_get_physical_device_properties_* before tu_physical_device_init,
so get_properties() would be callable by it.
This lets us delegate the physical device property entrypoints to
common runtime code.
Tested with drm-shim, doing a diff on vulkaninfo output. Differing
fields were pipelineCacheUUID, driverInfo and driverUUID, i.e. the
actual properties do not differ.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27723>
Some D3D11 games rely on out-of-bounds indirect UBO loads to return
real values from underlying bound descriptor. This workaround would
prevent us from lowering indirectly accessed UBOs to consts.
Later DXVK would declare dynamically indexed uniforms with upper
size bound, to make the accesses spec compliant. But for now
we need our own workaround.
Known affected games:
- Dark Souls 3
- Sekiro: Shadows Die Twice
- Final Fantasy Type-0 HD
- Ultrakill
- Dishonored 2
DXVK discussions:
- https://github.com/doitsujin/dxvk/issues/405
- https://github.com/doitsujin/dxvk/issues/3861
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27727>
This was a copy+paste error, probably from vk_drm_syncobj.c. If we do
WAIT_AVAILABLE, it only waits for the dma_fence to exist, not for it to
signal. Instead, we want WAIT_FOR_SUBMIT. (Technically, that's not
necessary but it is typical for CPU waits to also wait for the time
point to materialize.)
Fixes: 2074e28a0d ("nvk: Add an upload queue")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27757>
Zink is the only way to use hw accelerated GL on
a7xx and the preferred way for hw supporting NVK.
Start building Zink by default everywhere that we
would build swrast by default, except for Mac +
Cygwin + Haiku.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27737>
For AV1, the hardware supports decoding at 16x16, but for AVC & HEVC,
64 is the minimum.
The following Fluster tests used to check this,
av1-1-b8-01-size-16x16.ivf
av1-1-b8-01-size-32x32.ivf
Signed-off-by: Charlie Turner <cturner@igalia.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27085>
Only a matter of enabling it as packing itself works the same no
matter the number of components.
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27471>
On Xe2+, timestamp register can hold value upto 64-bit.
This change also fixes the timestamp related tests on Xe2 platform.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27713>
Conditional rendering is annoying to implement on ACE because there is
no predication packet like on GFX. With DGC it's even worse because
ACE is missing the IB2 packet which means it's not possible to predicate
the DGC IB entirely.
The provided solution is to always run the DGC prepare shader if
conditional rendering is enabled in order to generate a cmdbuf which
only contains NOPs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27673>
Avoids flushing jobs that write a texture that is read by a job in the
same job submission.
Now we need to handle the case where a texture is written by the
graphics pipeline and it is read by a compute pipeline.
Before this patch, glTextureBarrier() could be implemented as a NOP in
v3d. So the driver was doing more flushing than needed when
glTextureBarrier was not used.
v2: Use V3D_FLUSH_ALWAYS for resources written by graphics pipeline
and read by compute insead of V3D_FLUSH_DEFAULT. (Iago Toral)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27550>
