Commit graph

11465 commits

Author SHA1 Message Date
Aaron Watry
8c9a9205d9 radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcode
Previously we were creating a new LLVMContext every time that we called
radeon_llvm_parse_bitcode, which caused us to leak the context every time
that we compiled a CL program.

Sadly, we can't dispose of the LLVMContext at the point that it was being
created because evergreen_launch_grid (and possibly the SI equivalent) was
assuming that the context used to compile the kernels was still available.

Now, we'll create a new LLVMContext when creating EG/SI compute state, store
it there, and pass it to all of the places that need it.

The LLVM Context gets destroyed when we delete the EG/SI compute state.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Jonathan Liu
7990ab58fa llvmpipe: use pipe_sampler_view_release() to avoid segfault
This fixes another case of faulting when freeing a pipe_sampler_view
that belongs to a previously destroyed context.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-22 07:07:56 -07:00
Andreas Hartmetz
2efe7927d3 radeonsi: Use htile_buffer for depth only when there is no stencil.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2013-12-22 01:41:03 +01:00
Michel Dänzer
d580905000 radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
It's not relevant for other shader types.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-12-20 18:51:09 +09:00
Aaron Watry
8252847b7b r600g: Fix spelling error
Trivial change, testing commit access
2013-12-19 14:30:51 -06:00
Marek Olšák
37c24e6d86 radeonsi: set CB_DISABLE if the color mask is 0
Also needed for the DB in-place decompression according to hw docs.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-18 01:20:11 +01:00
Marek Olšák
3352ff97c2 radeonsi: add the htile buffer to the CS ioctl buffer list
This may fix the GPU crashes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-18 01:20:11 +01:00
Marek Olšák
2b404a6504 radeonsi: improve HiZ precision for less and lequal depth functions
r600g needs this too.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-17 15:41:46 +01:00
Marek Olšák
1a63f278f2 radeonsi: make DB_RENDER_OVERRIDE an invariant register
All this cruft was ported from r600g and isn't needed on SI and later
according to hw docs. If we implemented HiS, we would set it to 0.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-17 15:41:46 +01:00
Marek Olšák
249cb511c5 radeonsi: flush HTILE when appropriate
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-17 15:41:46 +01:00
Rob Clark
f9cfe5ce82 freedreno: dummy-draw workaround for a320
Fixes gpu lockups in supertuxkart.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-12-14 12:35:07 -05:00
Marek Olšák
b56c7f4df1 r600g: expose 32-bit integer vertex formats
This advertises GL_ARB_texture_buffer_object_rgb32.
2013-12-14 17:42:08 +01:00
Marek Olšák
2eb321b992 radeonsi: move invariant regs to si_init_config
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-14 17:42:08 +01:00
Marek Olšák
696229523d r600g: use shader-based MSAA resolving when hw-based one cannot be used
This fixes some MSAA integer tests.
2013-12-14 17:42:08 +01:00
Marek Olšák
9ebb9a3c8e radeonsi: use shader-based MSAA resolving when hw-based one cannot be used
This fixes MSAA resolving for 32-bit integer colorbuffers, which isn't
implemented by the hardware.

It also fixes VM protection faults when resolving MSAA 2D array textures.
This may be a CB bug, because shader-based resolving works fine.

It may also be faster for upside-down and scaled blits.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-14 17:42:08 +01:00
Marek Olšák
f0ed082bab gallium/u_blitter: remove useless parameters from some functions
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-14 17:42:08 +01:00
Roland Scheidegger
7c027666da llvmpipe: get rid of barycentric calculation of a0
Didn't really work as well as hoped (in particular it was not generally
more accurate), will solve this differently.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-12-14 17:11:03 +01:00
Roland Scheidegger
bfcf1ba1c4 llvmpipe: (trivial) get rid of triangle subdivision code
This code was always problematic, and with 64bit rasterization we no longer
need it at all.

Reviewed-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-14 17:11:03 +01:00
Brian Paul
d6a8421f3b svga: don't emit extraneous fs shadow code
Depending on the depth texture format, we may or may not have to
emit explicit fs code to do the shadow comparison.  Before, we
were emitting it more often than needed.

v2: check the actual texture format rather than the screen->depth.z16
field.  The screen->depth.z16, x8z24, s8z24 fields may not all be set
to a consistent set of depth formats.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-12-13 12:01:28 -08:00
Dave Airlie
ba00f2f6f5 swrast* (gallium, classic): add MESA_copy_sub_buffer support (v3)
This patches add MESA_copy_sub_buffer support to the dri sw loader and
then to gallium state tracker, llvmpipe, softpipe and other bits.

It reuses the dri1 driver extension interface, and it updates the swrast
loader interface for a new putimage which can take a stride.

I've tested this with gnome-shell with a cogl hacked to reenable sub copies
for llvmpipe and the one piglit test.

I could probably split this patch up as well.

v2: pass a pipe_box, to reduce the entrypoints, as per Jose's review,
add to p_screen doc comments.

v3: finish off winsys interfaces, add swrast classic support as well.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

swrast: add support for copy_sub_buffer
2013-12-13 14:37:01 +10:00
Marek Olšák
164dc6216a gallium: allow choosing which colorbuffers to clear
Required for glClearBuffer, which only clears one colorbuffer attachment.

Example:
   If the first colorbuffer is float and the second one is int:
      pipe->clear(pipe, PIPE_CLEAR_COLOR0, float_clear_color, ...);
      pipe->clear(pipe, PIPE_CLEAR_COLOR1, int_clear_color, ...);

This doesn't need any driver changes yet, because all drivers just use:
  if (flags & PIPE_CLEAR_COLOR) ..

The drivers which support GL 3.0 will have to implement it properly though.
2013-12-12 18:48:04 +01:00
Marek Olšák
e4ef639a57 r600g,radeonsi: fix initialized buffer range tracking for DMA, add comments
The DMA functions modify dst_offset and size and util_range_add gets wrong
values.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:48:04 +01:00
Marek Olšák
7fa8fb7382 radeonsi: fix binding the dummy pixel shader
This fixes valgrind errors in glxinfo.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:48:04 +01:00
Marek Olšák
0eb528abf2 radeonsi: fix FS_COLOR0_WRITES_ALL_CBUFS with mixed colorbuffer formats
The 16bpc packing must be done separately for each render target.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:48:04 +01:00
Marek Olšák
cd86f773a7 radeonsi: use the colorbuffer count from the shader key
As a result, the initialization of write_all must be done before
the compilation.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:48:04 +01:00
Marek Olšák
e9fc552837 radeonsi: remove unused variable in si_pipe_shader_ps
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:48:04 +01:00
Andreas Hartmetz
8ee7370c9b radeonsi: Write htile state to hardware. 2013-12-12 18:34:11 +01:00
Andreas Hartmetz
a32aa2617d radeon: Allocate htile buffer for SI in r600_texture. 2013-12-12 18:34:11 +01:00
Andreas Hartmetz
ca5812b45c radeon: rearrange r600_texture and related code a bit.
This should make the differences and similarities between color and
depth buffer handling more clear.
2013-12-12 18:34:11 +01:00
Marek Olšák
91aca8c662 r600g,radeonsi: consolidate buffer code, add handling of DISCARD_RANGE for SI
This adds 2 optimizations for radeonsi:
- handling of DISCARD_RANGE
- mapping an uninitialized buffer range is automatically UNSYNCHRONIZED

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
12806449fa r600g,radeonsi: add common interface for buffer invalidation
This will be used by common code in the next commit.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
e1374d86fe r600g,radeonsi: consolidate some debug flags
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
43ea10eb1d r600g: refactor out code for buffer invalidation
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
bba39d8804 r600g,radeonsi: share flags has_cp_dma and has_streamout
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
32fd445daa radeonsi: handle PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
which can come from glBufferData and glMapBufferRange.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
cc2c100274 radeonsi: implement accelerated buffer copying
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
171e4842ec r600g: use common interfaces in buffer_transfer_unmap
i.e. dma_copy and resource_copy_region.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 18:34:11 +01:00
Marek Olšák
0aea43db93 radeon: move some functions to r600_buffer_common.c
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christoph Brill <egore911@gmail.com>

v2: Renamed r600_buffer.c to r600_buffer_common.c. The stupid build system
    doesn't allow 2 files of the same name in different directories.
2013-12-12 18:34:05 +01:00
Marek Olšák
0b37737cc3 winsys/radeon: set/get the scanout flag with the tiling ioctls
If we assume that all buffers allocated by the DDX are scanout, a new flag
that says "this is not scanout" has to be added to support the non-scanout
buffers and maintain backward compatibility.

This fixes bad rendering on Wayland.

The flag is defined as:
  #define RADEON_TILING_R600_NO_SCANOUT   RADEON_TILING_SWAP_16BIT

AFAIK, RADEON_TILING_SWAP_16BIT is not used on SI.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-12-12 17:26:41 +01:00
Brian Paul
ccd6bf8272 svga: expose HW smooth/stipple/wide lines
Newer virtual HW versions support smooth/stipple/wide lines.
Use that instead of 'draw' fallbacks when possible.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-12-11 17:19:44 -08:00
Matthew McClure
e84a1ab3c4 llvmpipe: add plumbing for ARB_depth_clamp
With this patch llvmpipe will adhere to the ARB_depth_clamp enabled state when
clamping the fragment's zw value. To support this, the variant key now includes
the depth_clamp state. key->depth_clamp is derived from pipe_rasterizer_state's
(depth_clip == 0), thus depth clamp is only enabled when depth clip is disabled.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2013-12-11 18:24:21 +00:00
Vadim Girlin
00faf82832 r600g/sb: fix stack size computation on evergreen
On evergreen we have to reserve 1 stack element in some additional cases
besides the ones mentioned in the docs, but stack size computation was
recently reimplemented exactly as described in the docs by the patch that
added workarounds for stack issues on EG/CM, resulting in regressions
with some apps (Serious Sam 3).

This patch fixes it by restoring previous behavior.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=72369

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Andre Heider <a.heider@gmail.com>
2013-12-11 04:08:32 +04:00
Zack Rusin
7a50d38a2b llvmpipe: add a very useful (disabled) debugging output
Disabled by default, but it's very useful when needed.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-12-10 16:41:11 -05:00
Zack Rusin
155139059b llvmpipe: fix blending with half-float formats
The fact that we flush denorms to zero breaks our half-float
conversion and blending. This patches enables denorms for
blending. It's a little tricky due to the llvm bug that makes
it incorrectly reorder the mxcsr intrinsics:
http://llvm.org/bugs/show_bug.cgi?id=6393

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Zack Rusin <zackr@vmware.com>
2013-12-10 16:39:48 -05:00
Maarten Lankhorst
3e680de1eb nouveau: Support DRI Image 7 extension
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-12-10 09:46:17 +01:00
Christopher James Halse Rogers
d5a3a2d2fb gallium/winsys/drm: Prepare for passing prime fds in winsys_handle
Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-12-10 09:46:05 +01:00
Ilia Mirkin
bad8871e52 nv50: report 15 max inputs for fragment programs
First off, nv50_program only has 16 in/out varyings. However reporting
16 makes 'm' become 68 in nv50_fp_linkage_validate with the
varying-packing-simple piglit test. (Subverting the assert makes it
compile but fail.) With this patch, varying-packing-simple passes.

See: https://bugs.freedesktop.org/show_bug.cgi?id=69155

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "9.2 10.0" <mesa-stable@lists.freedesktop.org>
2013-12-10 08:45:59 +01:00
Maarten Lankhorst
5576ad11ed nouveau: Fix compiler warning regression
cfg is now unused, remove it.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-10 08:43:41 +01:00
Tom Stellard
9a5ce0c4c9 r300/compiler/tests: Fix line length check in test parser
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

CC: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-09 09:40:15 -05:00
Tom Stellard
1896431f79 r300/compiler/tests: Fix segfault
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

CC: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-09 09:40:15 -05:00