Commit graph

98694 commits

Author SHA1 Message Date
Emil Velikov
11ec85ddee docs: add release notes for 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 4f5e85e9e9)
2017-12-21 17:39:38 +00:00
Samuel Pitoiset
9f54675dbe radv/gfx9: fix primitive topology when adjacency is used
Found by inspection.

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-21 10:49:17 +01:00
Brian Paul
6e5b882339 glsl: disable vec3 packing/splitting in tfb separate mode
This fixes a varying packing issue when using transform feedback in
GL_SEPARATE_ATTRIBS mode.  By time we get to linking, we already
know that the number of feedback attributes is under the
GL_MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS limit so packing isn't
as critical.  In fact, packing/splitting vec3 attributes can cause
trouble because splitting effectively creates another TFB output
which can exceed device limits.  So, disable vec3 packing when it's
not needed to avoid that issue.

Fixes the Piglit ext_transform_feedback-separate test on VMware
driver.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:17 -07:00
Brian Paul
462df64495 glsl: simply packing class comparison
Handle comparing the packing class using the same method as we do
for var->data.is_xfb_only

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:17 -07:00
Brian Paul
06588a065f glsl: document varying_matches::assign_locations() params and return value
And change *components to components[] as a reminder that it's an array.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
544f41ff19 glsl: remove some continue statements
In some cases, I think loop code is easier to read without continue
statements.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
76fc24ba8d glsl: use bitwise operators in varying_matches::compute_packing_class()
The mix of bitwise operators with * and + to compute the packing_class
values was a little weird.  Just use bitwise ops instead.

v2: add assertion to make sure interpolation bits fit without collision,
per Timothy.  Basically, rewrite function to be simpler.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
cd7705de44 glsl: simplify loop in varying_matches::assign_locations()
The use of break/continue was kind of weird/confusing.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
47b4183c92 glsl: minor simplification in assign_varying_locations()
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
a0430bb62c glsl: make varying_matches::is_varying_packing_safe() const
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Brian Paul
d86c9836d5 glsl: trivial comment fixes in lower_packed_varyings.cpp
Reviewed by: Timothy Arceri <tarceri@itsqueeze.com>
2017-12-20 11:23:16 -07:00
Andres Gomez
a42e96f522 docs: update 17.3 and 18.0 cycles for the release calendar
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-20 19:48:58 +02:00
Juan A. Suarez Romero
24aac5f81e spirv: Makefile.nir.am: include vtn_gather_types_c.py script in tarball dist
Fixes: bb1e6ff161 ("spirv: Add a prepass to set types on vtn_values")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-12-20 17:44:35 +01:00
Lucas Stach
51523ab9fa st/dri: allow direct YUYV import
Push this format to the pipe driver unchanged.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-12-20 16:54:37 +01:00
Juan A. Suarez Romero
9702fac68e spirv: consider bitsize when handling OpSwitch cases
When walking over all the cases in a OpSwitch, take in account the bitsize
of the literals to avoid getting wrong cases.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-12-20 10:39:15 +01:00
Tapani Pälli
fcfb423646 drirc: set allow_glsl_cross_stage_interpolation_mismatch for more games
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Suggested-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104288
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-12-20 09:43:42 +02:00
Samuel Iglesias Gonsálvez
a31f0c4a36 anv: disallow VK_REMAINING_ARRAY_LAYERS in vkCmdClearAttachments()
Vulkan spec doesn't specify that VK_REMAINING_ARRAY_LAYERS is allowed
in the passed VkClearRect struct.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-12-20 06:55:41 +01:00
Ilia Mirkin
0cf6320eb5 nvc0/ir: change textureGrad to always use lane 0 as the tex origin
Thanks to Karol Herbst for the debugging / tracing work that led to this
change.

Move to using lane 0 as the "work" lane for the texture. It is unclear
why this helps, as that computation should be identical to doing it in
the "correct" lane with the properly adjusted quadops.

In order to be able to use the lane 0 result, we also have to ensure
that lane 0 contains the proper array/indirect/shadow values.

This applies to Fermi and Kepler. Maxwell+ may or may not need fixing,
but that lowering logic is separate.

Fixes KHR-GL45.texture_cube_map_array.sampling

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-12-19 23:09:19 -05:00
Eric Anholt
22ceb1f99b broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.
Most piglit textures happened to work out by RGBW not changing in that
bit, but it did cause failures in RGBA16F fbo-generatemipmap-formats.
2017-12-19 15:55:14 -08:00
Eric Anholt
200562ad01 broadcom/vc5: Clean up the comment and code around level 0 UIF.
I wrote this early in driver development, and our UIF handling is much
better now.
2017-12-19 14:20:19 -08:00
Eric Anholt
5473dc2b1f broadcom/vc5: Simplify the tiling calculations.
The mb_tile_layout table was just the utile_w/h times two, so reuse the
utile code instead.
2017-12-19 14:10:06 -08:00
Eric Anholt
81cdfdd670 broadcom/vc5: Return the depth in all components of depth textures.
Apparently gallium's u_blitter wants depth from at least the .z component,
and other swizzling appears to apply on top of that.  Fixes
fbo-generatemipmap-formats failures with depth formats.
2017-12-19 13:40:30 -08:00
Eric Anholt
8efb57c05e broadcom/vc5: Enable decompressing RGTC for desktop GL support.
This matches freedreno's behavior.
2017-12-19 13:40:30 -08:00
Eric Anholt
a13e9915c2 broadcom/vc5: Use u_transfer_helper for MSAA mappings. 2017-12-19 13:40:30 -08:00
Eric Anholt
7a30517cce broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.
There may be some more RCL work to be done (I think I need to split my Z/S
stores when doing separate stencil), but this gets piglit's "texwrap
GL_ARB_depth_buffer_float" working.

v2: Unwrap the z32f_wrapper before calling the helper, rather than having
    the helper have a callback.
v3: Rebase on Rob Clark's u_transfer_helper instead
2017-12-19 13:40:30 -08:00
Rob Clark
308076fd55 freedreno: add debug flag to force high priority context
Mainly for testing, FD_MESA_DEBUG=hiprio will force high priority
contexts.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-19 16:36:10 -05:00
Rob Clark
805a72404c freedreno: context priority support
For devices (and kernels) which support different priority ringbuffers,
expose context priority support.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-19 16:36:10 -05:00
Rob Clark
0015217c1e gallium: plumb context priority through to driver
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-12-19 16:36:10 -05:00
Rafael Antognolli
85789831b4 intel/compiler/gen10: Disable push constants.
We still have gpu hangs on Cannonlake when using push constants, so
disable them for now until we have a proper fix for these hangs.

v2: Add warning message when creating context too.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2017-12-19 12:32:24 -08:00
Samuel Pitoiset
4237c3d645 radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID components
F1 2017 looks good now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:26:25 +01:00
Samuel Pitoiset
0c4a30eb51 radv: do not add extra SGPR when push constants are not used
This is not because the vertex stage needs some push constants
that other stages need them too. This should reduce the number
of loaded SGPRs in some situations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:18 +01:00
Samuel Pitoiset
39097282f7 radv: change the needs_push_constants logic
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:16 +01:00
Samuel Pitoiset
ca8f3a8d55 radv: store pipeline stages that need push constants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:14 +01:00
Samuel Pitoiset
1cecaa9174 radv: remove one useless check in ac_nir_shader_info_pass()
pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:12 +01:00
Samuel Pitoiset
f9a07474a1 radv: remove one useless check in radv_flush_constants()
pipeline->layout can't be NULL now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:11 +01:00
Samuel Pitoiset
00162b2108 radv: add assertions to make sure pipeline layout objects are valid
The spec requires it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:09 +01:00
Samuel Pitoiset
3595a11648 radv: create pipeline layout objects for all meta operations
They are dummy objects but the spec requires layout to not be
NULL, this just makes sure we are creating valid pipeline layout
objects. This will allow us to remove some useless checks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-19 21:22:06 +01:00
Bas Nieuwenhuizen
8b5fe4b2b4 radv: Use a sort for rebuilding the sparse buffer bo list.
It uses slightly more memory (though still bounded by the number
of mapped ranges), but gives less quadratic behavior.

Cuts 4 minutes from the runtime of the CTS *.sparse.* tests.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-19 21:12:48 +01:00
Rob Clark
3511a51be0 freedreno/ir3: handle VTXID_BASE for indirect draws
Need to do some gymnastics to copy the parameter from the indirect
parameters buffer to uniform so shader sees the correct base-vertex-id.

Fixes ./bin/arb_draw_indirect-vertexid on a5xx and probably a4xx too.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-19 15:00:18 -05:00
Rob Clark
d7cb509fd3 freedreno/ir3: add ctx->mem_to_mem()
For dealing with indirect-draw + gl_VertexID, we'll introduce another
case where we need to use CP_MEM_TO_MEM.  Rather than adding more
if(a5xx)/else make this a ctx vfunc.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-19 15:00:18 -05:00
Rob Clark
0536737983 freedreno/a5xx: use vertex_id_zero_base
Cmdstream traces from blob make it clear that the blob driver dev's
*think* a5xx has a real (non-zero-based) vtxid.  But reality claims
differently.

Fixes ./bin/gl-3.2-basevertex-vertexid and probably others.

This means draw-indirect is going to need some gymnastics to copy
base-vertex into uniform.  (a4xx probably needs that too.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-12-19 15:00:18 -05:00
Dave Airlie
a1e18e87c7 r600: clear compressed flags in image state on unbind.
If we aren't binding an image, clear the compressed flags.

This fixes a segfault seen with an apitrace.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104331
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-19 05:38:12 +00:00
George Kyriazis
999f1cd5c6 swr: Account for index_bias in offsets
When calculating buffer offsets for client buffers account for info.index_bias.

Fixes the follow piglit tests:
arb_draw_elements_base_vertex-drawelements-user_varrays
arb_draw_elements_base_vertex-negative-index-user_varrays

Reviewed-By: Bruce Cherniak <bruce.cherniak@intel.com>
2017-12-18 18:51:25 -06:00
Dave Airlie
6ab346c4d9 r600: only reported tgsi ir compute support on evergreen+
This fixes a crash on r600/r700.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-18 21:41:46 +00:00
Bas Nieuwenhuizen
42bc25a79c radv: Advertise sync fd import and export.
Passes dEQP-VK.*.sync_fd.*

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-12-18 22:13:31 +01:00
Bas Nieuwenhuizen
52b3f50df8 radv: Implement sync file import/export for fences & semaphores.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-12-18 22:13:31 +01:00
Bas Nieuwenhuizen
b98bbdf490 radv/amdgpu: wrap sync fd import/export.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-12-18 22:13:31 +01:00
Dave Airlie
dd517ad96d ac/nir: fix lds store for patch outputs.
This wasn't calculating the correct value, this along with
a nir patch fixes a regression in:
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 043d14db30 (ac/nir: don't write tcs outputs to LDS that aren't read back.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-19 06:44:24 +10:00
Dave Airlie
0e8e7ccf9d nir/linking: always set the used_across_stages/outputs_read bits
If we don't remap and output this code would trample the outputs
read bits.

This fixes a regression in
dEQP-VK.tessellation.shader_input_output.barrier

Fixes: 1c9c42d16b (nir: add varying component packing helpers)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-19 06:44:11 +10:00
Jason Ekstrand
3be382cd7c spirv: Relax the validation conditions of OpSelect
The Talos Principle contains shaders with an OpSelect between two
vectors where the condition is a scalar boolean.  This is technically
against the spec bout nir_builder gracefully handles it by splatting
out the condition to all the channels.  So long as the condition is a
boolean, just emit a warning instead of failing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104246
2017-12-18 09:48:58 -08:00