Commit graph

80915 commits

Author SHA1 Message Date
Christian Gmeiner
103c363e0a etnaviv: add flags parameter to texture barrier
Fixes compile warning introduced by commit a1c848.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-01-18 16:58:11 +01:00
Christian Gmeiner
3ef916c128 etnaviv: handle PIPE_CAP_TGSI_FS_FBFETCH
Fixes compile warning introduced by commit ee3ebe.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-01-18 16:58:05 +01:00
Roland Scheidegger
56441708cf gallivm: (trivial) fix copy/paste bug with big endian code
8bd67a35c5 introduced using undefined variable
on big endian archs due to copy/paste bug.
(compile hack tested only)
2017-01-18 16:30:50 +01:00
Jose Fonseca
34041968f8 configure.ac: Revert recent HAVE_LLVM changes.
This reverts changes 903eb09b5fb78d47d0f8a4bdf826a113ca2aff40..1a0aa468f354f0ee94dd383cd40ae915584624aa:

  Tobias Droste (5):
    configure.ac: Rename MESA_LLVM to FOUND_LLVM
    configure.ac: Only set LLVM_LIBS if LLVM is used
    configure.ac: Only define HAVE_LLVM if LLVM is used
    configure.ac: Set and use HAVE_GALLIUM_LLVM define
    configure.ac: Don't check LLVM version in gallium_require_llvm

They break scons build, and I'm not convinced this is the right fix.  In
particular changing HAVE_LLVM in the C code is something I'd rather
avoid no matter what.  So it's better to discuss without the pressure of
broken builds.
2017-01-18 14:46:54 +00:00
Emil Velikov
8d1712a065 vulkan: automake: do not use EXTRA_DIST in a conditional
Otherwise the file might not end up in the tarball.

Fixes: dbd677efb4 "vulkan: add API registry"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-18 13:41:32 +00:00
Tobias Droste
4d0efb9683 configure.ac: Set and use HAVE_GALLIUM_LLVM define
Gallium code used HAVE_LLVM to check if it needs to compile code for
LLVM in header and source files.

With the new logic HAVE_LLVM is always set. Use extra define to figure
out if LLVM is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99010

Signed-off-by: Tobias Droste <tdroste@gmx.de>
2017-01-18 13:23:01 +00:00
Jose Fonseca
903eb09b5f gallivm: Cleanup USE_MCJIT.
Split USE_MCJIT macro dual nature into a separate constant time define
and a run-time variable.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-18 12:35:01 +00:00
Kenneth Graunke
aa291c3ba9 i965: Don't map/unmap in brw_print_program_cache on LLC platforms.
We have a persistent mapping.  Don't map it a second time or try to
unmap it.  Just use the pointer.

This most likely would wreak havoc except that this code is unused
(it's only called from an if (0) debug block).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-01-17 21:47:38 -08:00
Kenneth Graunke
ce89239294 i965: Move program cache printing to brw_program_cache.c.
It makes sense to put a function which prints out the entire contents
of the program cache in the file that implements the program cache.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-01-17 21:47:36 -08:00
Kenneth Graunke
f9edc550b2 i965: Make a helper for finding an existing shader variant.
We had five copies of the same "walk the cache and look for an
existing shader variant for this program" code.  Now we have one
helper function that returns the key.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-01-17 21:47:10 -08:00
Kenneth Graunke
e7d4008ebf glsl: Make copy propagation not panic when it sees an intrinsic.
A number of games have large arrays of constants, which we promote to
uniforms.  This introduces copies from the uniform array to the original
temporary array.  Normally, copy propagation eliminates those copies,
making everything refer to the uniform array directly.

A number of shaders in "Deus Ex: Mankind Divided" recently exposed a
limitation of copy propagation - if we had any intrinsics (i.e. image
access in a compute shader), we weren't able to get rid of these copies.

That meant that any variable indexing remained on the temporary array
rather being moved to the uniform array.  i965's scalar backend
currently doesn't support indirect addressing of temporary arrays,
which meant lowering it to if-ladders.  This was horrible.

According to Marek, on radeonsi/GCN, "F1 2015" uses 64% less
spilled-temp-array memory.

On i965/Skylake:

total instructions in shared programs: 13362954 -> 13329878 (-0.25%)
instructions in affected programs: 43745 -> 10669 (-75.61%)
helped: 12
HURT: 0

total cycles in shared programs: 248081010 -> 245949178 (-0.86%)
cycles in affected programs: 4597930 -> 2466098 (-46.37%)
helped: 12
HURT: 0

total spills in shared programs: 9493 -> 9507 (0.15%)
spills in affected programs: 25 -> 39 (56.00%)
helped: 0
HURT: 1

total fills in shared programs: 12127 -> 12197 (0.58%)
fills in affected programs: 110 -> 180 (63.64%)
helped: 0
HURT: 1

Helps Deus Ex: Mankind Divided.   The one shader with hurt spills/fills
is from Tomb Raider at Ultra settings, but that same shader has a
-39.55% reduction in instructions and -14.09% reduction in cycle counts,
so it seems like a win there as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-17 21:45:22 -08:00
Kenneth Graunke
9919542f1c i965: Make DCE set null destinations on messages with side effects.
(Co-authored by Matt Turner.)

Image atomics, for example, return a value - but the shader may not
want to use it.  We assigned a useless VGRF destination.  This seemed
harmless, but it can actually be quite harmful.  The register allocator
has to assign that VGRF to a real register.  It may assign the same
actual GRF to the destination of an instruction that follows soon after.

This results in a write-after-write (WAW) dependency, and stall.

A number of "Deus Ex: Mankind Divided" shaders use image atomics, but
don't use the return value.  Several of these were hitting WAW stalls
for nearly 14,000 (poorly estimated) cycles a pop.  Making dead code
elimination null out the destination avoids this issue.

This patch cuts one shader's estimated cycles by -98.39%!  Removing the
message response should also help with data cluster bandwidth.

On Skylake:

(instruction counts remain identical)

total cycles in shared programs: 255413890 -> 248081010 (-2.87%)
cycles in affected programs: 12019948 -> 4687068 (-61.01%)
helped: 24
HURT: 10

v2: Make can_omit_write independent of can_eliminate (Curro).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-17 21:45:04 -08:00
Kenneth Graunke
90bf39cd2b i965: Combine some dead code elimination NOP'ing code.
In theory we might have incorrectly NOP'd instructions that write the
flag, but where that flag value isn't used, and yet the instruction
either writes the accumulator or has side effects.

I don't believe any such instructions exist, so this is mostly a
code cleanup.

Curro pointed out that FS_OPCODE_FB_WRITE has a null destination and
actually writes the flag on Gen4-5 to dynamically decide whether to
write some payload data.  The hunk removed in this patch might have
NOP'd it, except that we don't actually mark flags_written() in the
IR, so it doesn't think the flag is touched at all.  That's sketchy,
but it means it wouldn't hit this today (though there are likely other
problems!).

v2: Properly replace the inst->regs_written() check in the second
    hunk with the flag being live (mistake caught by Curro).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-17 21:45:00 -08:00
Kenneth Graunke
be5f53e769 i965: Make DCE explicitly not eliminate any control flow instructions.
According to Matt, the dead code pass explicitly avoided IF and WHILE
because on Sandybridge, these could have conditional modifiers and
null destination registers.  Normally, those instructions use BAD_FILE
for the destination register.  Nowadays, we don't do that anymore, so
we could technically drop these checks.

However, it's clearer to explicitly leave control flow instructions
alone, so change it to the more generic !inst->is_control_flow().

This should have no actual change.

[This patch implements review feedback from Curro and Matt.]

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-17 21:44:29 -08:00
Dave Airlie
aac562f112 radv: disable vertex reuse when writing viewport index
This fixes some issues we'd hit later if using viewport
indexes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-18 08:04:11 +10:00
Dave Airlie
7e0382fb35 radv: add support for layered clears (v2)
Just always use the layer clear pipelines,
the overhead of emitting the layer shouldn't be
too large.

v2: Bas suggested we always use it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-18 06:21:22 +10:00
Dave Airlie
7886100811 radv/ac: split part of llvm compile into a separate function
This is needed to have common code for gs copy shader emission.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-18 06:21:05 +10:00
Dave Airlie
5dadd7ca27 radv/ac: switch an if to switch
makes it easier to add other shader stages.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-18 06:20:48 +10:00
Dave Airlie
6b635bbe16 radv: add support for writing layer/viewport index (v2)
This just adds the infrastructure to allow writing layer
and viewport index. It's just a first patch out of the geom
shader tree, and doesn't do much on its own.

v2: add missing if statement change (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-18 06:20:44 +10:00
Bas Nieuwenhuizen
3b4bf8aa63 ac/debug: Decrease num_dw for type 2 NOP's.
Otherwise we read past the end of the buffer.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-17 20:54:57 +01:00
Marek Olšák
57f18623fb radeonsi: for the tess barrier, only use emit_waitcnt on SI and LLVM 3.9+
Cc: 17.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-17 16:13:25 +01:00
Nayan Deshmukh
3a8f316e7b st/vdpau: remove the delayed rendering hack(v1.1)
the hack was introduced to avoid an extra copying
but now with dri3 we don't need it anymore

v1.1: rebasing

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-01-17 11:52:03 +01:00
Nayan Deshmukh
15bfdea99c st/vdpau: use dri3 to directly send the buffer to X(v2)
this avoids an extra copy which occurs in case of dri2

v1.1: fallback to dri2 if dri3 fails to initialize
v2: add PIPE_BIND_SCANOUT to output buffers as they will
    be send to X server directly (Michel)

Suggested-by: Christian König <christian.koenig@amd.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
2017-01-17 11:51:56 +01:00
Nayan Deshmukh
0ef17d76bb vl/dri3: use external texture as back buffers(v4)
dri3 allows us to send handle of a texture directly to X
so this patch allows a state tracker to directly send its
texture to X to be used as back buffer and avoids extra
copying

v2: use clip width/height to display a portion of the surface
v3: remove redundant variables, fix wrapping, rename variables
    handle vaapi path
v3.1: we need clip_width/height for every frame so we don't need
      to maintain it for each buffer instead use a global variable
v4: In case of single gpu we can cache the buffers as applications
    use constant number of buffer and we can avoid calls to present
    extension for every frame

Reviewed and Suggested-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
2017-01-17 11:51:50 +01:00
Iago Toral Quiroga
9fe9db8031 anv: set UAV coherence required bit when needed
The same we do in the OpenGL driver (comment copied from there).

This is required to ensure that we execute the fragment shader stage when
side-effects (such as image or ssbo stores) are present but there are no
color writes.

I found this while writing a test to check rendering to a framebuffer
without attachments where the fragment shader does not produce any
color outputs but writes to an image via imageStore(). Without this patch
the fragment shader does not execute and the image is not written,
which is not correct.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-17 07:57:04 +01:00
Samuel Iglesias Gonsálvez
ff0dd67d2f anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 1 MB
Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a
fragment shader code bigger than 128 kB.

This patch increases the allocation size limit to 1 MB.

v2:
- Increase it to 1 MB (Jason)
- Increase device->instruction_block_pool allocation size in
  anv_device.c (Jason)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-17 06:42:42 +01:00
Ilia Mirkin
19963231a3 nv50/ir: optimize shl + and
Address loading can often end up as shl + shr + shl combinations. The
latter two are equal shifts, which get converted into an and mask.
However if the previous shl is more than the mask is trying to remove
(in terms of low bits), we can just remove the and entirely. This
reduces some large shaders by as many as 3% of instructions (out of 2K).

total instructions in shared programs : 6495509 -> 6491076 (-0.07%)
total gprs used in shared programs    : 954621 -> 954623 (0.00%)

                local        gpr       inst      bytes
    helped           0           0        1014        1014
      hurt           0           2           0           0

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
5ba380c226 nvc0: enable FBFETCH with a special slot for color buffer 0
We don't need to support all the color buffers for advanced blend, just
cb0. For Fermi, we use the special binding slots so that we don't
overlap with user textures, while Kepler+ gets a dedicated position for
the fb handle in the driver constbuf.

This logic is only triggered when a FBFETCH is actually present so it
should be a no-op most of the time.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
6b7511c2f1 st/mesa: add support for advanced blend when fb can be fetched from
This implements support for emitting FBFETCH ops, using the existing
lowering pass for advanced blend logic, and disabling hw blend when
advanced blending is enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
a1c8484271 gallium: add flags parameter to texture barrier
This is so that we can differentiate between flushing any framebuffer
reading caches from regular sampler caches.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
ee3ebe68f9 gallium: add PIPE_CAP_TGSI_FS_FBFETCH
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
1393999541 gallium: add FBFETCH opcode to retrieve the current sample value
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Ilia Mirkin
376316e963 mesa: allow BlendBarrier to be used without support for full fb fetch
The extension spec is not currently published, so it's a bit premature
to require it for BlendBarrier usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Ilia Mirkin
2dd4cdeb4e glsl: avoid treating fb fetches as output reads to be lowered
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Dave Airlie
75f858cc33 radv/meta: split color renderpass creation out.
This is just prep work for layered clears, it doesn't change
anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 08:22:48 +10:00
Bas Nieuwenhuizen
5ae4de18d9 radv: Support multiple devices.
Pretty straightforward. Also deleted the big comment block as it
is a pretty standard pattern for filling in arrays.

Also removed the error message on non-existent devices, as getting
7 errors printed to the console each time you enumerate the
devices is pretty confusing.

v2: Add constant for number of DRM devices.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-01-16 22:15:22 +01:00
Bas Nieuwenhuizen
8406f79d6a radv: Get physical device from radv_device instead of the instance.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-01-16 22:15:22 +01:00
Ilia Mirkin
0baa639f76 nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwell
This had been updated in one place but not the other.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-01-16 16:04:55 -05:00
Dave Airlie
d4392a877c radv/ac: use ctx->voidt in more places. (v2)
Just noticed this while in the area.

v2: one replacement was incorrect.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 06:55:51 +10:00
Dave Airlie
3634dfd9e7 radv/meta: consolidate the depth stencil clear renderpasses
We only need one per samples (maybe not even that), reduce
all the unneeded ones.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 06:51:25 +10:00
Ilia Mirkin
5eeebca12f nv50/ir: handle new DDIV op which will be used for double divisions
The existing lowering is in place to lower that to RCP + MUL, or fancier
things down the line if necessary.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-16 14:45:46 -05:00
Nicolai Hähnle
6be4a40430 tgsi: add DDIV instruction
Double-precision division, to allow more precision than a DRCP + DMUL
sequence.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-16 20:17:22 +01:00
Nicolai Hähnle
5e94e5bb9b radeonsi: fix R600_DEBUG=nooptvariant
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2017-01-16 20:16:18 +01:00
Kenneth Graunke
7a2b65a1d7 i965: Make BLORP disable the NP Z PMA stall fix.
This may fix GPU hangs on Gen8.  I don't know if it does though.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-16 10:15:06 -08:00
Kenneth Graunke
d2590eb65f i965: Enable OpenGL 4.5 on Haswell.
Everything is in place and the test results look solid.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-01-16 10:13:23 -08:00
Marek Olšák
d523415609 radeonsi: implement GL_FIXED vertex format
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
018fb2ecb3 radeonsi: implement 32-bit SNORM/UNORM/SSCALED/USCALED vertex formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
44e9b67229 radeonsi: make fix_fetch 64-bit
v2: add u_bit_consecutive64

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Thomas Hindoe Paaboel Andersen
8daf6de3de gallium/hud: avoid buffer overrun
Renaming data sources was added in
e8bb97ce30
It was possible to use a new name longer than
the name array in hud_graph of 128. This
patch truncates the name to fit the array.

CC: Marek Olšák <marek.olsak@amd.com>

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
0d9a4efce9 gallium/radeon: add GPU-shaders-busy HUD query
It should be close to the GPU load, but it can be much lower if something
is stalling shader execution (e.g. CP DMA).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00