Commit graph

98742 commits

Author SHA1 Message Date
Samuel Pitoiset
0f8290dd32 radeonsi: make use of ac_init_exec_full_mask()
Similar to si_init_exec_full_mask().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-27 09:57:10 +01:00
Brian Paul
2250c967e7 svga: use tgsi_util_get_shadow_ref_src_index() in a couple place
No piglit changes.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-12-26 21:44:42 -07:00
Brian Paul
ad26999d33 tgsi: improve comment on tgsi_util_get_shadow_ref_src_index()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-12-26 21:44:33 -07:00
Brian Paul
8571506e51 svga: fix TGSI_TEXTURE_SHADOW1D coordinate selection
Fixes about 24 Piglit tex-miplevel-selection tests.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-12-26 21:44:22 -07:00
Brian Paul
1e0b64ced9 svga: fix shadow comparison failures
In some cases, We do shadow comparison cases in the fragment shader
instead of with texture sampler state.  But when we do so, we must
disable the shadow comparison test in the sampler state.  As it
was, we were doing the comparison twice, which resulted in nonsense.
Also, we had the texcoord and texel value swapped in the comparison
instruction.

Fixes about 38 Piglit tex-miplevel-selection tests.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-12-26 21:43:37 -07:00
Brian Paul
ac78ab951a util: add trivial comment on u_upload_create() 2017-12-26 21:40:49 -07:00
Dave Airlie
88d09b642d r600: fix atomic counter index mode getting emitted on pre-cayman
This is a regression since I added cayman atomic support, not sure
it fixes anything, but the shader dumps look better.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-27 02:02:46 +00:00
Dave Airlie
34d23e82ca radv: set some dcc parameters depending on if texture will be sampled
This is ported from amdvlk which sets the independent 64b blocks
only for image which will sample dcc.

I'm not sure how to port this to radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-27 11:10:52 +10:00
Dave Airlie
db27907d78 radv/radeonsi: set dcc min uncompressed properly for APUs.
This is ported from amdvlk.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-27 11:10:50 +10:00
Dave Airlie
cf363e4405 amd/common/radv/radeonsi: use register defines for dcc block sizes.
These are just taken from amdvlk, we probably knew these already,
but may as well port them now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-27 11:10:35 +10:00
Timothy Arceri
a88532c612 st/glsl_to_nir: add patch support to st_nir_assign_var_locations()
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-27 11:26:08 +11:00
Timothy Arceri
351eee05d3 st/glsl_to_nir: call post opt functions after opts have finished
We need to move this to a separate loop because
nir_compact_varyings() can alter the IR of a previous stage.

Fixes: 6648bd68fd "st/glsl_to_nir: enable NIR link time opts"

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-27 11:26:08 +11:00
Timothy Arceri
ddc0e7941f st/st_glsl_to_nir: call nir_lower_64bit_pack
Fixes 56 crashes in the radeonsi nir backend.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-27 11:26:08 +11:00
Dave Airlie
ae556ba778 docs/features: show es3.1 compat done on r600.
This was already being reported, just missed the docs.

Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-27 00:08:20 +00:00
Miklós Máté
3667714ccd mesa: always compare optype with symbolic name in ATI_fs
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
0fd82f5455 mesa: document ati_fragment_shader::cur_pass and swizzlerq
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
f5415dcc8c mesa: move ATI_fs state compile changes after the error checks
Both in setup and arithmetic instructions. Also, remove the useless
new_*_inst() functions, and refactor check_arith_arg(), because it did
two completely different things.

Piglit: spec/ati_fragment_shader/error04-endshader

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
7df48c48f9 tnl: fix not having texture coords in ATI_fs in swrast
ATI_fs in swrast only had access to texture coordinates if there was a
valid texture bound and texturing was enabled.

Piglit: spec/ati_fragment_shader/render-sources and render-notexture

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
a64d6fb730 mesa: fix not having secondary color in ATI_fs in swrast
ATI_fs in swrast only had secondary color if GL_COLOR_SUM was enabled.
This patch probably fixes the same issue in r200.

Piglit: spec/ati_fragment_shader/render-sources and render-precedence

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
759d193ceb mesa: fix validate for secondary interpolator
This patch fixes multiple problems:
- the interpolator check was duplicated
- both had arg instead of argRep
- I split it into color and alpha for better readability and error msg
- the DOT4 check only applies to color instruction according to the spec
- made the DOT4 check fatal, and improved the error msg

Piglit: spec/ati_fragment_shader/error08-secondary

v2: fixed formatting, added spec quotations

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
8b3a519913 mesa: fix typo in ATI_fs dstMod error checking
Piglit: spec/ati_fragment_shader/error14-invalidmod

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
4003ad298a mesa: fix crash when an ATI_fs pass begins with an alpha inst
This fixes crash when:
- first pass begins with alpha inst
- first pass ends with color inst, second pass begins with alpha inst
Also, use the symbolic name instead of a number.

Piglit: spec/ati_fragment_shader/api-alphafirst

v2: fixed formatting

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:23 +01:00
Miklós Máté
178a3dfb0e mesa: add fallback texture for SampleMapATI if there is nothing
This fixes crash in the state tracker.

Piglit: spec/ati_fragment_shader/render-notexture

v2: fixed formatting, moved stuff inside the loop,
    moved the fallback later to fix more cases

Signed-off-by: Miklós Máté <mtmkls@gmail.com>
2017-12-25 14:32:22 +01:00
Marek Olšák
f9cd6c502e radeonsi: don't use fast color clear for small images even on APUs
Increase the limit and handle non-square images better.

This makes glxgears 20% faster on APUs, and a little more on dGPUs.
We all use and love glxgears.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-12-25 14:23:18 +01:00
Marek Olšák
afdcf0f6b2 radeonsi: set PNT_SPRITE_ENA = point_quad_rasterization
This is based on how nvc0 translates the state.
2017-12-25 14:23:02 +01:00
Marek Olšák
986e467e4c gallium/util: add util_num_layers helper 2017-12-25 14:23:02 +01:00
Bas Nieuwenhuizen
70b5e85fc3 radv: Fix DCC compatible formats.
DCC was disabled when the image format is !!supported, which is one ! too many.

Ironically the commit that introduced it was supposed to lead to more DCC use ...

Fixes: 969537d935 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-12-23 10:58:18 +01:00
Anuj Phogat
2d04572038 Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"
This reverts commit 9cd60fce9c.
Above commit caused 2000+ piglit tests to assert fail. Disabling
the align1 mode on gen10 for now to avoid failures.

Cc: Matt Turner <mattst88@gmail.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-12-22 16:40:40 -08:00
Andres Gomez
466011e46a docs: update calendar, add news item and link release notes for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-12-23 00:59:22 +02:00
Andres Gomez
7f4ea112ce docs: add sha256 checksums for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 3281775ab9)
2017-12-23 00:55:35 +02:00
Andres Gomez
d18f00e160 docs: add release notes for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 3482790712)
2017-12-23 00:55:33 +02:00
Ilia Mirkin
0dbdb07070 freedreno: set missing internal_format when importing texture
Fixes running piglits without -fbo. Probably lots of other stuff too.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-12-22 09:56:02 -05:00
Samuel Pitoiset
38f9b87af2 amd/common: add ac_export_mrt_z() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-22 10:38:49 +01:00
Samuel Pitoiset
03ef264146 amd/common: pass the family to ac_llvm_context_init()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-22 10:38:44 +01:00
Samuel Pitoiset
79c495aa37 radv: reduce the number of small surfaces that need CMASK or DCC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-22 10:38:44 +01:00
Ilia Mirkin
05944a392e gm107/ir: use lane 0 for manual textureGrad handling
This is parallel to the pre-SM50 change which does this. Adjusts the
shuffles / quadops to make the values correct relative to lane 0, and
then splat the results to all lanes for the final move into the target
register.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-By: Karol Herbst <kherbst@redhat.com>
2017-12-22 00:17:15 -05:00
Dave Airlie
fbac9f86aa radv/meta: fix blit paths for depth/stencil (v2.1)
This fixes the layout issue for the blit path as well.

This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint*

v2: use compatible render passes.
v2.1: use enum

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:11:02 +10:00
Dave Airlie
821b5379f0 radv: handle depth/stencil image copy with layouts better. (v3.1)
If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.

This fixes:
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.optimal_general
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.general_general

v2: refactor some shared helpers for blit patches
v3: we only need multiple render passes as they should be compatible.
v3.1: use enum (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:10:04 +10:00
Dave Airlie
286fe1db47 radv: refactor blit2d pipeline creation
This just refactors the gfx9 blit2d pipeline creation
to be less lines of code.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:09:49 +10:00
Dave Airlie
9f675bf934 radv/gfx9: add support for 3d images to blit 2d paths
This add support for a 3D image reading path to the blit 2d paths,
like I did for the clear paths.

Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:09:28 +10:00
Dave Airlie
a99fa7e8a2 radv/gfx9: add 3d sampler image->buffer copy shader. (v3)
On GFX9 we must access 3D textures with 3D samplers AFAICS.

This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer

on GFX9 for me.

v1.1: fix tex->sampler_dim to dim
v2: send layer in from outside
v3: don't regress on pre-gfx9

Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:08:48 +10:00
Dave Airlie
9594667899 radv: fix surface max layer count (v2)
looking at traces I noticed we'd set slice_max too large sometimes.

This should fix it.

v2: fix missing - 1

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 14:07:55 +10:00
Francisco Jerez
b3e3cb9901 intel/fs: Initialize fs_visitor::grf_used on construction.
This should shut up some Valgrind errors during pre-regalloc
scheduling.  The errors were harmless since they could only have led
to the estimation of the bank conflict penalty of an instruction
pre-regalloc, which is inaccurate at that point of the program
compilation, but no less accurate than the intended "return 0"
fall-back path.  The scheduling pass is normally re-run after regalloc
with a well-defined grf_used value and accurate bank conflict
information.

Fixes: acf98ff933 "intel/fs: Teach instruction scheduler about GRF bank conflict cycles."
Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-21 15:20:17 -08:00
Francisco Jerez
1aa79d5ed5 intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to obtain vector storage.
The weight_vector_type constructor was inadvertently assuming C++17
semantics of the new operator applied on a type with alignment
requirement greater than the largest fundamental alignment.
Unfortunately on earlier C++ dialects the implementation was allowed
to raise an allocation failure when the alignment requirement of the
allocated type was unsupported, in an implementation-defined fashion.
It's expected that a C++ implementation recent enough to implement
P0035R4 would have honored allocation requests for such over-aligned
types even if the C++17 dialect wasn't active, which is likely the
reason why this problem wasn't caught by our CI system.

A more elegant fix would involve wrapping the __SSE2__ block in a
'__cpp_aligned_new >= 201606' preprocessor conditional and continue
taking advantage of the language feature, but that would yield lower
compile-time performance on old compilers not implementing it
(e.g. GCC versions older than 7.0).

Fixes: af2c320190 "intel/fs: Implement GRF bank conflict mitigation pass."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104226
Reported-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-12-21 15:19:59 -08:00
Mark Janes
7665383a33 Revert "spirv: consider bitsize when handling OpSwitch cases"
This reverts commit 9702fac68e, which
hangs vulkancts and crucible on all platforms.

The patch is being reverted because it disables continuous integration
testing.  The patch from bug 104359 does not apply to master.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104359
2017-12-21 12:15:40 -08:00
Dave Airlie
b81f1a592b radv: fix issue with multisample positions and interp_var_at_sample.
This fixes vmfaults seen on vega with:
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_single_sample_.128_128_1.samples_1

These were caused by the don't allocate cmask but it was just accidental.

The actual problem was the shader was trying to get the sample positions from
a buffer, but the buffer was never getting configured to contain them, as the
previous shader never needed them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 1171b304f3 (radv: overhaul fragment shader sample positions.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-22 05:42:48 +10:00
Emil Velikov
be86e5e7d5 docs: update calendar, add news item and link release notes for 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-21 17:40:16 +00:00
Emil Velikov
022258117e docs: add sha256 checksums for 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f66496d291)
2017-12-21 17:39:38 +00:00
Emil Velikov
11ec85ddee docs: add release notes for 17.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 4f5e85e9e9)
2017-12-21 17:39:38 +00:00
Samuel Pitoiset
9f54675dbe radv/gfx9: fix primitive topology when adjacency is used
Found by inspection.

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-21 10:49:17 +01:00