Commit graph

171886 commits

Author SHA1 Message Date
Kenneth Graunke
0eeeab16a8 intel/brw: Delete brw_wm_prog_key::line_aa
Not used on modern hardware.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
bfb12def74 intel/brw: Delete enum gfx6_gather_sampler_wa
Only needed on Gfx6, which we don't support anymore.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
5fbba530cf intel/brw: Delete compiler->supports_shader_constants
True for all drivers using this compiler.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
485b2bca17 intel/brw: Delete constant_buffer_0_is_relative
This was only for old kernels on old hardware.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
eebd24680c intel/brw: Delete SINCOS
Only existed on Gfx4-5.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
292e424162 intel/brw: Delete more unused compression stuff
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
a18030305c intel/brw: Delete SIMD4x2 URB opcodes
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
288b966e3e intel/brw: Delete legacy SFIDs
This involves a little rework in the assembler to treat "math" as an
opcode token rather than an SFID.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
afae5e78ca intel/brw: Delete more unused defines
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
Kenneth Graunke
3202f3fdbe intel/brw: Delete enum brw_urb_write_flags
This was used by the vec4 backend.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27872>
2024-02-29 18:00:14 +00:00
David Rosca
cbbed6ca3e radeonsi/vcn: Implement separate QP for I/P/B frames
This also fixes max_au_size as a side effect of using new IB.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27558>
2024-02-29 16:12:13 +00:00
David Rosca
252ba4bbdd radeonsi/vcn: Use temporal_layer_index to select temporal layer
Don't change enc_pic.temporal_id as that is used in AV1 encode.

Fixes: 8d44a11508 ("radeonsi/vcn: Don't reinitialize encode session on bitrate/fps change")

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27558>
2024-02-29 16:12:13 +00:00
David Rosca
8c9445896f frontends/va: Separate QP for I/P/B frames
For H264/HEVC this needs to calculate init_qp + slice_qp_delta.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27558>
2024-02-29 16:12:13 +00:00
Mike Blumenkrantz
532d43881f zink: stop enabling EXT_conservative_rasterization
this isn't used

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27882>
2024-02-29 15:32:05 +00:00
Eric Engestrom
64f037e079 vk/util: print a nice error in vk_icd_gen.py when VK_HEADER_VERSION is not defined
Shouldn't be reachable in normal case, but when messing with vk.xml it's
nicer than the current:

    TypeError: can only concatenate str (not NoneType) to str

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27779>
2024-02-29 14:25:49 +00:00
Eric Engestrom
3f2790adcd vk/util: trivial cleanups in vk_icd_gen.py
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27779>
2024-02-29 14:25:49 +00:00
Mike Blumenkrantz
e4d45c582b glx: only print zink failure-to-load messages if explicitly requested
if zink is inferred, let it fail silently

ref #10293

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27836>
2024-02-29 13:13:09 +00:00
Mike Blumenkrantz
571effdf08 egl/dri2: use the right egl platform enum
this is otherwise completely broken and allows loading zink in all cases

Fixes: 0fd066a1d7 ("egl: only check dri3 on X11")

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27836>
2024-02-29 13:13:09 +00:00
Nanley Chery
6d76d46154 iris: Enable pass-through state init for gfx12 CCS
The previous patch changed the gfx12 CCS initial aux state from
pass-through to compressed-no-clear. This isn't always accurate.

This patch determines if a CCS is in the pass-through state by
inspecting the associated resources' bo field. In order to do that
clearly, move aux-state initialization out of
iris_resource_configure_aux (which can be called before BO creation).
Split up that logic and move the pieces into iris_resource_from_handle,
iris_resource_init_aux_buf, and a new function in ISL.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27835>
2024-02-29 12:32:11 +00:00
Nanley Chery
06dff45abb iris: Don't memset CCS on integrated gfx12
There are no illegal CCS values on integrated gfx12 platforms.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27835>
2024-02-29 12:32:11 +00:00
Nanley Chery
e1443074f3 iris: Don't memset the extra_aux memory range
The extra_aux memory range holds the CCS portion of surfaces using
MCS_CCS or HiZ+CCS on integrated gfx12.x. Avoid memsetting because:

* There's no known CCS initialization requirement for MCS_CCS.

* ACM has the same documented initialization requirements for HIZ+CCS on
  TGL/MTL, but iris doesn't initialize the CCS portion on discrete. For
  TGL+, anv does not initialize the CCS portion of HiZ+CCS. Let's be
  consistent with these other cases and avoid initialization.

If we end up needing to initialize the CCS, we can try come up with
something that will work for both integrated and discrete gfx12.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27835>
2024-02-29 12:32:11 +00:00
Danylo Piliaiev
8567d02682 tu: Update prim restart state when we switch from/to indexed draw
Previously, if first draw call with wasn't indexed but pipeline
had primitive restart enabled - primitive restart would be disabled
for draw calls, even indexed, that follow.

However, prim restart index works in non-indexed draw calls, but since
we don't emit fresh PC_RESTART_INDEX for them - they may use stale
value if prim restart is enabled for non-indexed draw calls.

So we have track the switch between indexed and non-indexed draw calls
and emit PC_PRIMITIVE_CNTL_0 for them.

Fixes car rear window in Need for Speed: Most Wanted (2012)

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27821>
2024-02-29 11:56:01 +00:00
Mike Blumenkrantz
d4f3770ea2 zink: use uncompacted vk_dispatch_table
the dispatch table doesn't know which extensions zink wants to use,
so let zink use the extensions it wants to use

fixes #10513

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27834>
2024-02-29 11:18:18 +00:00
Mike Blumenkrantz
5d91db9666 vulkan/dispatch_table: add an uncompacted version of the table
this is a bandaid fix that allows users (zink) to actually call the
functions intended to be called. the real fix would be to figure out
which extensions are enabled on the device and then only GPA the
functions associated with those extensions

that's too hard though so I'm slapping some flex tape on it

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27834>
2024-02-29 11:18:18 +00:00
Tapani Pälli
185d420b27 anv: make sure aux is disabled for memory objects
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9248
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10608
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27614>
2024-02-29 07:44:09 +00:00
Tapani Pälli
9058a2a78e iris: make sure aux is disabled for external objects
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27614>
2024-02-29 07:44:09 +00:00
Lionel Landwerlin
fe037dec6e anv: expose VK_EXT_descriptor_buffer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
454d381243 anv: disable mutable combined image/sampler in descriptor buffer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
ab7641b8dc anv: implement descriptor buffer binding
And barriers for them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
349c46c553 anv: handle push descriptor writes with descriptor buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
1de44b1951 anv: add pipeline/shader support for descriptor buffers
Lowering/layout is pretty much the same as direct descriptors. The
caveats is that since the descriptor buffers are not visible from the
binding tables we can't promote anything to the binding table (except
push descriptors).

The reason for this is that there is nothing that prevents an
application to use both types of descriptors and because descriptor
buffers have visible address + capture replay, we can't merge the 2
types in the same virtual address space location (limited to 4Gb max,
limited 2Gb with binding tables).

If we had the guarantee that both are not going to be used at the same
time, we could consider a 2Gb VA for descriptor buffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
8090bd78b8 anv: add descriptor set layout support for descriptor buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
7ba059854c anv: add new helper to update binding table pool offset
We'll want to differentiate STATE_BASE_ADDRESS from
3DSTATE_BINDING_TABLE_POOL updates.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
ef8f09148f anv: add embedded sampler support
Those samplers live in the dynamic state base address and their offset
can be directly baking into the shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
259cdc5496 nir: add additional flag to resource_intel for embedded samplers
This will enable specific lowering of embedded samplers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
99047451c9 intel/fs: add plumbing for embedded samplers
We can address samplers from 3 different locations :
   - binding table
   - dynamic state base address
   - bindless sampler base address (only Gfx11+)

Here we allow samplers to be address from the dynamic state base
address with the embedded sampler flag.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
3f25b2826f anv: add embedded sampler parameters in descriptor set layout hash
The way we implement embedded samplers will be to have the sampler
handle as a relocated constant in the shader.

This implies that 2 identical shaders with different embedded sampler
parameters must have different hash as we cannot reuse the final
shader binary.

So add the sampler hash to the descriptor set layout hash when the set
has embedded samplers.

This has the effect of creating multiple shader entries in the cache
unfortunately. An improvement over this would be to have a anv_device
map of (embedded samplers hash + shader hash) to shader in instruction
heap, so that pipeline caches only have a single entry regardless of
embedded sampler parameters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
6d59168dc9 anv: compute a sampler hash based on parameters
To be used for embedded samplers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
9506d3f338 anv: implement data write entry points for EXT_descriptor_buffer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
ec73db3b8c anv: allocate fsr states for descriptor buffer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
44bf552704 anv: allocate border colors for descriptor buffers
Because we have 2 dynamic state heaps, we need to duplicate values.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
271f0b8b9c anv: allocate slice_hash for descriptor buffer
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
859f087c0b anv: move aux-tt to general state pool
We're about to use 2 different location for the dynamic state heap.
Which means at least on i915 we need 2 copies of all the fixed
(CPS_STATE, border colors, slice hash) stuff on the dynamic state
heap.

Let's avoid having the aux-tt tables in there too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
226c519f28 anv: add a second dynamic state heap for descriptor buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
82d772fa9b anv: create new helper for small allocations
A number of allocations during command buffer building are sourced
from the dynamic state heap. They're not actually access using an
offset in the dynamic state heap, it just happens to be a conveninent
place.

Use different helpers for thoses so we dynamically change the dynamic
state heap location in the next commits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:06 +00:00
Lionel Landwerlin
c6a91f1695 anv: add new heap/pool for descriptor buffers
We'll use a new heap & a new pool for descriptor buffers. The heap
will hold descriptor buffers, while the pool will only be used on
Gfx12.5+ for push descriptors.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:05 +00:00
Lionel Landwerlin
fc1aeb57bb anv: optimize push descriptor updates
vkd3d-proton uses a descriptor set with a single descriptor, so we
don't even need to copy the old data where there is an update.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
2024-02-29 07:05:05 +00:00
Mike Blumenkrantz
3d38c9597f zink: hook up KHR_partial_update
this just requires clamping the renderArea to the passed damage rect,
which is composed by merging all the passed rects into a single large
region

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27867>
2024-02-29 03:26:14 +00:00
Mike Blumenkrantz
e0131cd371 zink: use VK_KHR_incremental_present to propagate damage rects
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27867>
2024-02-29 03:26:14 +00:00
Mike Blumenkrantz
4fe88170ce zink: hook up VK_KHR_incremental_present
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27867>
2024-02-29 03:26:14 +00:00