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iris: Don't memset the extra_aux memory range

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The extra_aux memory range holds the CCS portion of surfaces using
MCS_CCS or HiZ+CCS on integrated gfx12.x. Avoid memsetting because:

* There's no known CCS initialization requirement for MCS_CCS.

* ACM has the same documented initialization requirements for HIZ+CCS on
  TGL/MTL, but iris doesn't initialize the CCS portion on discrete. For
  TGL+, anv does not initialize the CCS portion of HiZ+CCS. Let's be
  consistent with these other cases and avoid initialization.

If we end up needing to initialize the CCS, we can try come up with
something that will work for both integrated and discrete gfx12.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27835>
This commit is contained in:
Nanley Chery 2023-08-02 11:52:51 -04:00 • committed by Marge Bot
parent 8567d02682
commit e1443074f3
1 changed files with 2 additions and 16 deletions
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18
src/gallium/drivers/iris/iris_resource.c
View file

@ -999,30 +999,16 @@ static bool
iris_resource_init_aux_buf(struct iris_screen *screen,
struct iris_resource *res)
{
void *map = NULL;
if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID &&
res->aux.surf.size_B > 0) {
if (!map)
map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
void* map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
if (!map)
return false;
memset((char*)map + res->aux.offset, 0, res->aux.surf.size_B);
}
if (res->aux.extra_aux.surf.size_B > 0) {
if (!map)
map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
if (!map)
return false;
memset((char*)map + res->aux.extra_aux.offset,
0, res->aux.extra_aux.surf.size_B);
}
if (map)
iris_bo_unmap(res->bo);
}
if (res->aux.surf.size_B > 0) {
res->aux.bo = res->bo;