Commit graph

7908 commits

Author SHA1 Message Date
Iván Briano
2fcda40ea4 anv: do not get rid of empty/useless fragment shaders
This was an optimization done a while ago that doesn't seem to be having
much of an impact anymore, and on the other hand, causes all sorts of
breakage with queries, as many of our HW counters don't get incremented
when rasterization is disabled.

This fixes a bunch of issues Zink has with ANV, but more importantly, it
fixes upcoming CTS tests:
dEQP-VK.transform_feedback.primitives_generated_query.*.empty_frag.*
dEQP-VK.transform_feedback.primitives_generated_query.*.no_attachment.*
dEQP-VK.transform_feedback.primitives_generated_query.*.color_write_disable_*

Cc: mesa-stable

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17038>
(cherry picked from commit 4666ef720e)

Conflicts:
	src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt

CI file was deleted as it doesn't exist on 22.1
2022-06-17 09:03:13 -07:00
Ian Romanick
9ff1f30d45 anv: Remove FS executables when applying the null FS optimization
If the executables are still hanging out,
anv_GetPipelineExecutableStatisticsKHR will try to dereference NULL
pointers in pipeline->shaders[MESA_SHADER_FRAGMENT].

At least in terms of fossil-db output, this matches the behavior from
before 73b3efcd59.

Fixes: 73b3efcd59 ("anv: Handle the null FS optimization after compiling shaders")
Closes: #6590
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16898>
(cherry picked from commit 65d6708bc3)
2022-06-15 16:12:58 -07:00
Kenneth Graunke
d962bdcdd3 intel/compiler: Fix uncompaction of signed word immediates on Tigerlake
This expression accidentally performs a 32-bit sign-extension when
processing the second half of the expression (the low 16 bits).

Consider -7W, which is represented as 0xfff9fff9 in our encoding (the
16-bit word is replicated to both halves of the 32-bit dword).

Tigerlake's compaction stores the low 11-bits of an immediate as-is,
and replicates the 12th bit.  So here, compacted_imm will be 0xff9.

   (  (int)(0xff9 << 20) >> 4) |
   ((short)(0xff9 <<  4) >> 4))

   0xfff90000 | (0xff90 >> 4)
   0xfff90000 | 0xfffffff9 ...oops...
   0xfffffff9

By casting the second line of the expression to unsigned short, we
prevent the sign-extension when it combines both parts, so we get:

   0xfff90000 | 0x0000fff9
   0xfff9fff9

Fixes: 12d3b11908 ("intel/compiler: Add instruction compaction support on Gen12")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16833>
(cherry picked from commit 26bb81f3f6)
2022-06-07 13:17:38 -07:00
Erik Faye-Lund
c9d10441f0 intel: remove stale makefile
When this landed, the Autotools build system was already removed. Why
was this file added in the first place? Probably a rebase-mistake...

Fixes: 134e750e16 ("i965: extract performance query metrics")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16790>
(cherry picked from commit a8605db504)
2022-06-07 13:17:38 -07:00
Jason Ekstrand
901d5b8617 anv: Don't disable the fragment shader if XFB is enabled
It turns out that we need a fragment shader for streamout.  Whh?  From
Lionel's reading of simulator sources, it seems the streamout unit is
looking at enabled next stages.  It'll generate output to the clipper in
the following cases :

 - 3DSTATE_STREAMOUT::ForceRendering = ON
 - PS enabled
 - Stencil test enabled
 - depth test enabled
 - depth write enabled
 - some other depth/hiz clear condition

Forcing rendering without a PS seems like a recipe for hangs so it's
probably better to just enable the PS in this case.

Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
(cherry picked from commit 0d28de212a)
2022-06-01 14:10:28 -07:00
Jason Ekstrand
365b1a2daa anv: Handle the null FS optimization after compiling shaders
Actually compile and cache the no-op fragment shader but remove it from
the pipeline if we determine it's a no-op.  This way we always have it
even if it's not strictly needed.

Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
(cherry picked from commit 73b3efcd59)
2022-06-01 14:10:28 -07:00
Jason Ekstrand
84c1da77de anv: Drop alpha_to_coverage from the NULL FS optimization
Starting with Ivy Bridge, we implement alpha-to-coverage by writting
gl_SampleMask with a pattern based on alpha.  This will show up in
wm_prog_data::uses_omask so we don't need to look at the key.

Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
(cherry picked from commit 9fe6caf4e7)
2022-06-01 14:10:28 -07:00
Jason Ekstrand
3cceae1986 intel/fs: Copy color_outputs_valid into wm_prog_data
Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
(cherry picked from commit 1b9248e761)
2022-06-01 14:10:28 -07:00
Michael Skorokhodov
b7b727f561 anv: Update line range
This commit increases the maximum line width to 8.0 for SLK+
and to 7.9921875 for BDW and earlier.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6234
Fixes: fce0027d ("anv: Unbreak wide lines on HSW/BDW")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15879>
(cherry picked from commit 10b6d9230c)
2022-06-01 14:10:28 -07:00
Marcin Ślusarz
2cca7dce1e anv: disable streamout before emitting mesh shading state
Fixes tests which use secondary command buffers.

Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
(cherry picked from commit aa1c128b54)
2022-05-13 10:06:04 -07:00
Marcin Ślusarz
d7ef4f99da anv: update task/mesh distribution with the recommended values
Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
(cherry picked from commit f083df8710)
2022-05-13 10:06:03 -07:00
Kenneth Graunke
a21fe41535 anv: Fix INTEL_DEBUG=bat on XeHP
We no longer emit STATE_BASE_ADDRESS in every batch on XeHP, so the
decoder might not know what the various base addresses are if it's only
looking at a single batch.  Fortunately, they also never change, so we
can just emit them once here.

On earlier platforms, initializing them here should be harmless.  We'll
emit STATE_BASE_ADDRESS if we change them, which will update these.

Thanks to Iván Briano for catching this.

Fixes: 8831cb38aa ("anv: Stop updating STATE_BASE_ADDRESS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16287>
(cherry picked from commit ad537edc7c)
2022-05-13 10:06:02 -07:00
Jordan Justen
9c84a34361 intel/dev: Enable first set of DG2 PCI IDs
Mostly Matt Roper's kernel patch commit message:

The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now.

The remaining DG2 IDs for add-in cards will be enabled in a future
patch once some additional required functionality has fully landed.

Ref: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
(cherry picked from commit ad565f6b70)
2022-05-13 10:06:00 -07:00
Jordan Justen
24626dca6b intel/dev: Add INTEL_PLATFORM_DG2_G12
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
(cherry picked from commit 4456209ce5)
2022-05-13 10:05:59 -07:00
Iván Briano
03d5e496d9 anv: re-alloc push constants after secondary command buffers
If the secondary command buffer executed used push constants on a
different set of stages than the primary is using, we may end up not
reallocating them for the primary, getting misrender artifacts at best,
or a nice GPU hang at worst.

Fixes the tests from a CTS from the future:
dEQP-VK.dynamic_rendering.random.*

Cc: mesa-stable

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16439>
(cherry picked from commit 2e46f38902)
2022-05-10 21:23:14 -07:00
Chia-I Wu
a068671262 anv: advertise rectangularLines only for Gen10+
We use the non-strict algorithm (with parallelograms) prior to Gen10 for
wide lines.  We can not advertise rectangularLines.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Fixes: f6e7de41d7 ("anv: Implement VK_EXT_line_rasterization")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15432>
(cherry picked from commit b2b810ebff)
2022-05-10 20:08:47 -07:00
Lionel Landwerlin
ca8af9c529 anv: remove static_state_mask
This is now unnecessary. Either an instruction is never dynamic and
it's emitted in genX_pipeline.c or it can be and it's emitted in
genX_cmd_buffer.c/gfx8_cmd_buffer/gfx7_cmd_buffer.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 797a8850b9)
2022-05-04 16:05:53 -07:00
Lionel Landwerlin
5346b6aac4 anv: don't emit 3DSTATE_VF_TOPOLOGY in pipeline batch
v2: drop primitive_topology = 0xffffffff (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 74a27a6ccb)
2022-05-04 16:05:46 -07:00
Lionel Landwerlin
1cd83f0311 anv: don't emit 3DSTATE_DEPTH_BOUNDS in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 48229d11ba)
2022-05-04 16:05:38 -07:00
Lionel Landwerlin
0dcd1ac226 anv: don't emit 3DSTATE_BLEND_STATE_POINTERS in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 76e735d09c)
2022-05-04 16:05:31 -07:00
Lionel Landwerlin
265351f03f anv: don't emit 3DSTATE_WM in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit e9d000a831)
2022-05-04 16:05:23 -07:00
Lionel Landwerlin
5eadf0d634 anv: don't emit 3DSTATE_STREAMOUT in pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 065242d623)
2022-05-04 16:05:15 -07:00
Lionel Landwerlin
579a90e3c4 anv: never emit 3DSTATE_CPS in the pipeline batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit ce8bb29342)
2022-05-04 16:05:03 -07:00
Lionel Landwerlin
c4fac8fbbe anv: rework sample location
On Gfx7 we can only give the sample location for a given multisample
number. This means everytime the multisampling value changes, we have
to re-emit the locations. It's fine because it's also where
(3DSTATE_MULTISAMPLE) the number of samples is stored.

On Gfx8+ though, 3DSTATE_MULTISAMPLE only holds the number of samples
and all the sample locations for all number of samples are located in
3DSTATE_SAMPLE_PATTERN. So to be more effecient there, we need to
track the locations for all sample numbers and compare new values with
the relevant sample count when touching the dynamic state.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 168b13364f)
2022-05-04 16:04:51 -07:00
Lionel Landwerlin
218b619ab2 Revert "anv: fix dynamic state emission"
This reverts commit f348103fce. The
change was causing performance regressions.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 810518fda7)
2022-05-04 16:04:41 -07:00
Lionel Landwerlin
ebb13496c4 anv: add missing logic op set in pipeline dyn state
v2: add ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP check (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 75ad0e4b08 ("anv: support blending logic op dynamic state")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 69e6417e19)
2022-05-04 16:04:36 -07:00
Lionel Landwerlin
96202a0fab anv: reset all dynamic state after secondary execution
We don't know in what state the secondary buffer will leave the HW
when it ends. It's easier to consider everything needs to be reemitted
for now.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
(cherry picked from commit 5048f15737)
2022-05-04 16:04:36 -07:00
Lionel Landwerlin
381ec467db anv: fix invalid utrace memcpy l3 config on gfx < 11
device->l3_config is only valid on Gfx11+

This only fixes using GPU_TRACE=1

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02a4d622ed ("anv: expose a couple of emit helper to build utrace buffer copies")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16291>
(cherry picked from commit 4efc997472)
2022-05-03 09:41:32 -07:00
Jordan Justen
ae7c0db4b3 intel_dev_info: Add --hwconfig command line parameter
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit de99a11172)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16231>
2022-05-02 11:35:31 -07:00
Jordan Justen
b29e15e515 intel/dev: Read hwconfig from i915
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit d9ff9ea9c3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16231>
2022-05-02 11:35:31 -07:00
Lionel Landwerlin
9fdb834853 anv: fix clflush usage on utrace copy batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
(cherry picked from commit 44e93b4c6f)
2022-05-02 10:46:40 -07:00
Francisco Jerez
2f286bfef5 intel/dev: Compute pixel pipe information based on geometry topology DRM query.
This changes the intel_device_info calculation to call an additional
DRM query requesting the geometry topology from the kernel, which may
differ from the result of the current topology query on XeHP+
platforms with compute-only and 3D-only DSSes.  This seems more
reliable than the current guesswork done in intel_device_info.c trying
to figure out which DSSes are available for the render CS.

Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143>
(cherry picked from commit 14cad38b19)
2022-05-02 10:46:39 -07:00
Nanley Chery
d45ccc05f1 isl,iris: Add DG2 CCS modifier support for XeHP
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
(cherry picked from commit b023f18bad)
2022-05-02 10:46:33 -07:00
Nanley Chery
21753f734e intel/isl: Add a score for I915_FORMAT_MOD_4_TILED
Enables the modifier in anv.

Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
(cherry picked from commit a53abeb7fb)
2022-05-02 10:46:32 -07:00
Anuj Phogat
2385ca720b isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHP
This patch adds Tile 4 modifier support to Mesa and allows Mesa to
use Tile 4 on gen12-hp with GBM.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
(cherry picked from commit ac441d0953)
2022-05-02 10:46:32 -07:00
Tapani Pälli
b39d53761c isl: disable mcs (and mcs+ccs) for color msaa on DG2
Fixes lots of various test failures in:
   dEQP-VK.pipeline.multisample.min_sample_shading_disabled.*
   dEQP-GLES3.functional*multisample.*
   KHR-GL*sample_variables.*

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13991>
(cherry picked from commit d3ef3657b2)
2022-04-28 21:52:59 -04:00
Sviatoslav Peleshko
fe83982fa6 anv: workaround apps that assume full subgroups without specifying it
Without this we might choose 8 or 16 width, while the app assumes 32.
With subgroup operations it may cause wrong calculations and thus bugs.

Examples of such games are Aperture Desk Job and DOOM Eternal.

v2: Make it a driconf option instead of applying unconditionally, move
    from brw_required_dispatch_width to brw_compile_cs
v3: Rename allow_assuming_full_subgroups -> assume_full_subgroups.
    Include assume_full_subgroups value in anv_pipeline_hash_compute().
v4: Move actual workaround code from brw_fs.c -> anv_pipeline.c.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6171
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15708>
(cherry picked from commit 28ca5636f6)
2022-04-26 09:06:12 -07:00
Lionel Landwerlin
1e1b7661e2 anv: skip acceleration structure in binding table emission
With mutable descriptor types, we can end up in a situation where a
binding can be, for instance, both a UBO and an acceleration
structure.

While we can promote the UBO to a binding table entry and the shader
can use it, this isn't true of acceleration structures that have no
surface state. In that case just skip the entry. The shader is already
compiled to use the descriptor entry.

In the non mutable case, the entry will not be created by
anv_nir_apply_pipeline_layout.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 63e91148b7 ("anv: Enable VK_VALVE_mutable_descriptor_type")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15969>
(cherry picked from commit fe413962b4)
2022-04-26 09:06:09 -07:00
Lionel Landwerlin
12eb1548bd anv: fix acceleration structure descriptor template writes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d258b0bf0e ("anv: Add support for binding acceleration structures")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16058>
(cherry picked from commit b7828f56ba)
2022-04-26 09:06:07 -07:00
Lionel Landwerlin
4a434c77fc intel: fixup number of threads per EU on XeHP
Computations for indexing in-memory data structures for ray queries
depend on this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4f9141607f ("intel: Add device info for DG2")
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15925>
(cherry picked from commit 107acf5a4a)
2022-04-26 09:06:07 -07:00
Vadym Shovkoplias
692d9bce64 anv: Fix geometry flickering issue when compute and 3D passes are combined
Call flush_pipeline_select_3d in CmdBeginRendering() to emit a dummy MEDIA_VFE_STATE
before switching from GPGPU to 3D.

Original commit with the fix:
bc612536 ("anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3D")

Fixes: 3501a3f9ed ("anv: Convert to 100% dynamic rendering")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6201
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15954>
(cherry picked from commit 785b6579ae)
2022-04-21 11:20:20 -07:00
Jordan Justen
503440f0dc intel/dev: Add device info for RPL-P
Cc: mesa-stable
Ref: https://patchwork.freedesktop.org/series/102701/
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16054>
(cherry picked from commit d257494ec4)
2022-04-21 11:20:19 -07:00
Marcin Ślusarz
9a28aea2a2 intel/compiler: invalidate metadata in brw_nir_initialize_mue
New "if" blocks may have been inserted.

Fixes: bc4f8c073a ("intel/compiler: inject MUE initialization")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15924>
(cherry picked from commit 5dace41c10)
2022-04-20 21:44:50 -07:00
Marcin Ślusarz
30a980fb94 intel/compiler: invalidate all metadata in brw_nir_lower_intersection_shader
New "if" blocks were inserted.

Fixes: 303378e1dd ("intel/rt: Add lowering for combined intersection/any-hit shaders")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15924>
(cherry picked from commit 4fddef33d5)
2022-04-20 21:44:50 -07:00
Marcin Ślusarz
4f031f35fe anv: invalidate all metadata in anv_nir_lower_ubo_loads
lower_ubo_load_instr may insert "if" blocks.

Fixes: 61749b5a15 ("anv: Add a pass for lowering A64 UBO access")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15924>
(cherry picked from commit 5bd3ba5b67)
2022-04-20 21:44:50 -07:00
Lionel Landwerlin
df6dc532d2 anv: allow getting the address of the beginning of the batch
There is no reason not to be able to get it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 34a0ce58c7 ("anv: add a new execution mode for secondary command buffers")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15968>
(cherry picked from commit 184084e21c)
2022-04-20 21:44:50 -07:00
Lionel Landwerlin
db3e06f76c intel: fix URB programming for GT1s
We're missing a programming restriction.

Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>.
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596>
(cherry picked from commit b07c215c35)
2022-04-20 21:44:49 -07:00
Lionel Landwerlin
08f3950d6b anv: stop using old entrypoint/struct/enum names for 1.3
v2: More replacements

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15920>
2022-04-13 21:13:56 +00:00
Lionel Landwerlin
e11bedb9f5 intel/fs: add a note on possible optimization of root node address
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15910>
2022-04-13 11:24:49 +00:00
Lionel Landwerlin
9c0805ef91 intel/fs: fix metadata preserve on trace_ray intrinsic
c78be5da30 ("intel/fs: lower ray query intrinsics") introduced a
helper function using nir_(push|pop)_if which invalidated dominance &
block_index for the replacement of nir_intrinsic_rt_trace_ray.

We can still keep dominance/block_index metadata for the lowering of
nir_intrinsic_rt_execute_callable though.

This change uses 2 different lowering function with correct metadata
preservation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c78be5da30 ("intel/fs: lower ray query intrinsics")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15910>
2022-04-13 11:24:49 +00:00