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anv: don't emit 3DSTATE_BLEND_STATE_POINTERS in pipeline batch

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>
This commit is contained in:
Lionel Landwerlin 2022-04-28 00:12:52 +03:00 • committed by Marge Bot
parent e9d000a831
commit 76e735d09c
5 changed files with 12 additions and 64 deletions
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3
src/intel/vulkan/anv_pipeline.c
View file

@ -234,9 +234,6 @@ void anv_DestroyPipeline(
struct anv_graphics_pipeline *gfx_pipeline =
anv_pipeline_to_graphics(pipeline);
if (gfx_pipeline->blend_state.map)
anv_state_pool_free(&device->dynamic_state_pool, gfx_pipeline->blend_state);
for (unsigned s = 0; s < ARRAY_SIZE(gfx_pipeline->shaders); s++) {
if (gfx_pipeline->shaders[s])
anv_shader_bin_unref(device, gfx_pipeline->shaders[s]);

2
src/intel/vulkan/anv_private.h
View file

@ -3383,8 +3383,6 @@ struct anv_graphics_pipeline {
*/
bool use_primitive_replication;
struct anv_state blend_state;
uint32_t vb_used;
struct anv_pipeline_vertex_binding {
uint32_t stride;

62
src/intel/vulkan/genX_pipeline.c
View file

@ -1316,24 +1316,11 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
surface_count = map->surface_count;
}
const uint32_t num_dwords = GENX(BLEND_STATE_length) +
GENX(BLEND_STATE_ENTRY_length) * surface_count;
uint32_t *blend_state_start, *state_pos;
const struct intel_device_info *devinfo = &pipeline->base.device->info;
uint32_t *blend_state_start = devinfo->ver >= 8 ?
pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
uint32_t *state_pos = blend_state_start;
if (dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
const struct intel_device_info *devinfo = &pipeline->base.device->info;
blend_state_start = devinfo->ver >= 8 ?
pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
pipeline->blend_state = ANV_STATE_NULL;
} else {
pipeline->blend_state =
anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
blend_state_start = pipeline->blend_state.map;
}
state_pos = blend_state_start;
bool has_writeable_rt = false;
state_pos += GENX(BLEND_STATE_length);
#if GFX_VER >= 8
struct GENX(BLEND_STATE_ENTRY) bs0 = { 0 };
@ -1353,11 +1340,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
continue;
}
if ((pipeline->dynamic_state.color_writes & (1u << binding->index)) == 0) {
state_pos = write_disabled_blend(state_pos);
continue;
}
const VkPipelineColorBlendAttachmentState *a =
&info->pAttachments[binding->index];
@ -1395,18 +1377,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
.AlphaBlendFunction = vk_to_intel_blend_op[a->alphaBlendOp],
};
/* Write logic op if not dynamic */
if (!(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP))
entry.LogicOpFunction = genX(vk_to_intel_logic_op)[info->logicOp];
/* Write blending color if not dynamic */
if (!(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
entry.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT);
entry.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT);
entry.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT);
entry.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT);
}
if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
a->colorBlendOp != a->alphaBlendOp) {
@ -1439,9 +1409,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
entry.ColorBufferBlendEnable = false;
}
if (a->colorWriteMask != 0)
has_writeable_rt = true;
/* Our hardware applies the blend factor prior to the blend function
* regardless of what function is used. Technically, this means the
* hardware can do MORE than GL or Vulkan specify. However, it also
@ -1471,7 +1438,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
GENX(3DSTATE_PS_BLEND_header),
};
blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable;
blend.HasWriteableRT = has_writeable_rt;
blend.ColorBufferBlendEnable = bs0.ColorBufferBlendEnable;
blend.SourceAlphaBlendFactor = bs0.SourceAlphaBlendFactor;
blend.DestinationAlphaBlendFactor = bs0.DestinationAlphaBlendFactor;
@ -1480,28 +1446,10 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
blend.AlphaTestEnable = false;
blend.IndependentAlphaBlendEnable = blend_state.IndependentAlphaBlendEnable;
if (dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
GENX(3DSTATE_PS_BLEND_pack)(NULL, pipeline->gfx8.ps_blend, &blend);
} else {
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_BLEND), _blend)
_blend = blend;
}
#else
(void)has_writeable_rt;
GENX(3DSTATE_PS_BLEND_pack)(NULL, pipeline->gfx8.ps_blend, &blend);
#endif
GENX(BLEND_STATE_pack)(NULL, blend_state_start, &blend_state);
if (!(dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP))) {
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
bsp.BlendStatePointer = pipeline->blend_state.offset;
#if GFX_VER >= 8
bsp.BlendStatePointerValid = true;
#endif
}
}
}
static void

3
src/intel/vulkan/gfx7_cmd_buffer.c
View file

@ -310,7 +310,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
pipeline->rasterization_samples));
}
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;

6
src/intel/vulkan/gfx8_cmd_buffer.c
View file

@ -650,6 +650,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
const uint8_t color_writes = d->color_writes;
const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
bool has_writeable_rt =
anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
(color_writes & ((1u << state->color_att_count) - 1)) != 0;
/* 3DSTATE_PS_BLEND to be consistent with the rest of the
* BLEND_STATE_ENTRY.
@ -657,7 +661,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
uint32_t ps_blend_dwords[GENX(3DSTATE_PS_BLEND_length)];
struct GENX(3DSTATE_PS_BLEND) ps_blend = {
GENX(3DSTATE_PS_BLEND_header),
.HasWriteableRT = color_writes != 0,
.HasWriteableRT = has_writeable_rt,
};
GENX(3DSTATE_PS_BLEND_pack)(NULL, ps_blend_dwords, &ps_blend);
anv_batch_emit_merge(&cmd_buffer->batch, ps_blend_dwords,