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intel: fix URB programming for GT1s

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We're missing a programming restriction.

Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>.
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596>
(cherry picked from commit b07c215c35)
This commit is contained in:
Lionel Landwerlin 2022-03-26 23:59:26 +02:00 • committed by Dylan Baker
parent 353330c094
commit db3e06f76c
2 changed files with 24 additions and 7 deletions
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2
.pick_status.json
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@ -1336,7 +1336,7 @@
"description": "intel: fix URB programming for GT1s",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

29
src/intel/common/intel_urb_config.c
View file

@ -225,14 +225,32 @@ intel_get_urb_config(const struct intel_device_info *devinfo,
}
/* Lay out the URB in pipeline order: push constants, VS, HS, DS, GS. */
int next = push_constant_chunks;
int first_urb = push_constant_chunks;
/* From the BDW PRM: for 3DSTATE_URB_*: VS URB Starting Address
*
* "Value: [4,48] Device [SliceCount] GT 1"
*
* From the ICL PRMs and above :
*
* "If CTXT_SR_CTL::POSH_Enable is clear and Push Constants are required
* or Device[SliceCount] GT 1, the lower limit is 4."
*
* "If Push Constants are not required andDevice[SliceCount] == 1, the
* lower limit is 0."
*/
if ((devinfo->ver == 8 && devinfo->num_slices == 1) ||
(devinfo->ver >= 11 && push_constant_chunks > 0 && devinfo->num_slices == 1))
first_urb = MAX2(first_urb, 4);
int next_urb = first_urb;
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
if (entries[i]) {
start[i] = next;
next += chunks[i];
start[i] = next_urb;
next_urb += chunks[i];
} else {
/* Just put disabled stages at the beginning. */
start[i] = 0;
/* Put disabled stages at the beginning of the valid range */
start[i] = first_urb;
}
}
@ -359,4 +377,3 @@ intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
return r;
}