Commit graph

11081 commits

Author SHA1 Message Date
Tatsuyuki Ishi
0b2fad0426 radv: Fix emitting tess indirect descriptors twice.
This fixes a copy-paste error found by manual inspection.

TES may be merged into GS with certain HW stage mappings, which lead to
duplicate set-register commands to be emitted with the old code.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20935>
2023-01-27 18:31:58 +00:00
Rhys Perry
695cf75266 aco: set has_color_exports with GPL
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 192486b7aa ("aco/gfx11: export mrtz in discard early exit for non-color shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20937>
2023-01-27 16:51:56 +00:00
Samuel Pitoiset
1a93cd1556 radv: add a layer for fixing rendering issues with RAGE2
This game seems to incorrectly set the render area and since we switched
to full dynamic rendering, the framebuffer dimensions is no longer used.

Forcing the render area to be the framebuffer dimensions restore the
previous logic and it fixes rendering issues.

Fixes: c7d0d328d5 ("radv: Set the window scissor to the render area, not framebuffer")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20900>
2023-01-27 15:28:45 +00:00
Turo Lamminen
b2df787058 radv: Optimize emitting prefetches
Check the need for emitting prefetch before calling si_emit_cache_flush
to mask a possible cache miss delay and always inline radv_emit_prefetch_L2.
Either change alone is not significant but together they increase
drawcall throughput by 8% on i5-2500.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20877>
2023-01-27 15:05:03 +00:00
Turo Lamminen
bd78c8bbfa radv: Avoid redundant fetch of radv_device
0.6% gain in drawcall throughput on i5-2500.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20877>
2023-01-27 15:05:03 +00:00
Turo Lamminen
b5de1ee1f7 radv: Clean up variables in si_get_ia_multi_vgt_param
8% gain in drawcall throughput on i5-2500. This can significantly change
how compiler allocates registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20877>
2023-01-27 15:05:03 +00:00
Turo Lamminen
4b8dfaae89 radv: Change radeon_cmdbuf counters to uint64_t to make alias analysis optimize radeon_emit better
1% gain in drawcall throughput on i5-2500. Depends quite heavily on
compiler and CPU.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20877>
2023-01-27 15:05:03 +00:00
Erik Faye-Lund
b6a344f4ba meson: do not reconstruct ICD paths
Meson will already construct these paths for us, so let's reuse them
instead of throwing away the result and recontstructing them.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20907>
2023-01-27 11:35:50 +00:00
Erik Faye-Lund
d54c8a47c6 meson: avoid using deprecated build_root() method
The meson.build_root() method has been deprecated, so let's switch to
meson.project_build_root(), which usually means the same thing. The case
where it doesn't do the same thing is if Mesa is a subproject to some
other project, but in that case I believe we want the build root of Mesa,
not of the parent project anyway.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20907>
2023-01-27 11:35:50 +00:00
Marek Olšák
2ae08c3e8f ac/llvm: remove llvm:: now that we use "using namespace llvm"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20297>
2023-01-26 19:33:55 -05:00
Marek Olšák
a273f64f80 ac/llvm: run the IPSCCP pass
AMDVLK runs it and it seems useful.

https://en.wikipedia.org/wiki/Sparse_conditional_constant_propagation

58380 shaders in 35438 tests
Totals:
SGPRS: 2709080 -> 2709224 (0.01 %)
VGPRS: 1592972 -> 1592808 (-0.01 %)
Spilled SGPRs: 2420 -> 2420 (0.00 %)
Spilled VGPRs: 1077 -> 1077 (0.00 %)
Private memory VGPRs: 253 -> 253 (0.00 %)
Scratch size: 1232 -> 1232 (0.00 %) dwords per thread
Code Size: 61382088 -> 61356504 (-0.04 %) bytes
Max Waves: 849293 -> 849308 (0.00 %)
Outputs: 127090 -> 127090 (0.00 %)
Patch Outputs: 579 -> 579 (0.00 %)

Totals from affected shaders:
SGPRS: 5400 -> 5544 (2.67 %)
VGPRS: 6200 -> 6036 (-2.65 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 975824 -> 950240 (-2.62 %) bytes
Max Waves: 1214 -> 1229 (1.24 %)
Outputs: 232 -> 232 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20297>
2023-01-26 19:33:43 -05:00
Marek Olšák
d05c3811cd ac/llvm: run the LLVM sinking pass because LLVM will stop running it
shader-db was run with the sinking pass disabled in LLVM.

58380 shaders in 35438 tests
Totals:
SGPRS: 2730768 -> 2730768 (0.00 %)
VGPRS: 1592932 -> 1592928 (-0.00 %)
Spilled SGPRs: 2687 -> 2687 (0.00 %)
Spilled VGPRs: 551 -> 551 (0.00 %)
Private memory VGPRs: 253 -> 253 (0.00 %)
Scratch size: 700 -> 700 (0.00 %) dwords per thread
Code Size: 61238872 -> 61238868 (-0.00 %) bytes
Max Waves: 849209 -> 849209 (0.00 %)
Outputs: 127090 -> 127090 (0.00 %)
Patch Outputs: 579 -> 579 (0.00 %)

Totals from affected shaders:
SGPRS: 440 -> 440 (0.00 %)
VGPRS: 396 -> 392 (-1.01 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 49880 -> 49876 (-0.01 %) bytes
Max Waves: 105 -> 105 (0.00 %)
Outputs: 14 -> 14 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20297>
2023-01-26 19:33:17 -05:00
Timur Kristóf
c644461b71 radv, aco, ac: Implement pack_half_2x16_rtz_split.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15838>
2023-01-26 12:24:24 +00:00
Samuel Pitoiset
b97fee432c radv: fix ignoring graphics shader stages that don't need to be imported
If a shader stage is already imported from a library it should be
properly ignored.

Fixes recent CTS dEQP-VK.pipeline.fast_linked_library.misc.unused_shader_stages*.

Fixes: c8765c5244 ("radv: ignore shader stages that don't need to be imported with GPL")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20899>
2023-01-26 08:34:36 +00:00
Samuel Pitoiset
6bec915919 radv: fix creating libraries with PS epilog and all CB states as dynamic
It's legal to create a library with FRAGMENT_OUTPUT_INTERFACE and with
all CB states as dynamic, in this case the PS epilog should be dynamic.

This fixes a bunch of regressions while running Zink/RADV CTS with
RADV_PERFTEST=gpl.

Zink is the final boss.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20882>
2023-01-26 08:14:39 +00:00
Timur Kristóf
9fc5d8d211 aco: Remove dynamic VS input loads.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20733>
2023-01-26 02:43:11 +00:00
Timur Kristóf
15b689604e radv: Lower dynamic VS inputs in NIR.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20733>
2023-01-26 02:43:11 +00:00
Timur Kristóf
81620fc7b0 aco: Enable constant exec mask based optimization on compute shaders.
We know for sure exec is initially -1 when the shader always has full subgroups.

Fossil DB stats on GFX11:
Totals from 3884 (2.88% of 134913) affected shaders:
SpillSGPRs: 1673 -> 1697 (+1.43%); split: -1.67%, +3.11%
SpillVGPRs: 2316 -> 2310 (-0.26%); split: -0.65%, +0.39%
CodeSize: 19584436 -> 19567156 (-0.09%); split: -0.13%, +0.04%
Scratch: 217088 -> 216832 (-0.12%)
Instrs: 3784596 -> 3780303 (-0.11%); split: -0.15%, +0.03%
Latency: 39971204 -> 39794967 (-0.44%); split: -0.47%, +0.03%
InvThroughput: 7885552 -> 7801247 (-1.07%); split: -1.14%, +0.07%
VClause: 74654 -> 74611 (-0.06%); split: -0.07%, +0.01%
SClause: 103139 -> 103043 (-0.09%); split: -0.13%, +0.04%
Copies: 279864 -> 281995 (+0.76%); split: -0.72%, +1.48%
Branches: 92082 -> 92084 (+0.00%); split: -0.03%, +0.03%
PreSGPRs: 155637 -> 149491 (-3.95%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20670>
2023-01-26 01:59:26 +00:00
Timur Kristóf
39448c8e9c radv, aco: Add uses_full_subgroups to compute shader info.
Allow the compiler to assume that the shader always has full subgroups,
meaning that the initial EXEC mask is -1 in all waves (all lanes enabled).
This assumption is incorrect for ray tracing and internal (meta) shaders
because they can use unaligned dispatch.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20670>
2023-01-26 01:59:26 +00:00
Timur Kristóf
22b350fa27 radv: Get rid of app_shaders_internal.
This will make sure the internal field is set to true for internal
shaders which are initialized outside of radv_device_init_meta.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20670>
2023-01-26 01:59:26 +00:00
Friedrich Vock
e07729e8de radv/rmv: Correct timestamp shifting
The shifting was off-by-one compared to how it is done in the kernel. Also, excess_length needs to be casted to uint64_t to prevent zeroing everything except the 5 LSBs.

Fixes: abf3bcd6 ("radv: Add RMV resource tracking")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20820>
2023-01-26 01:17:26 +00:00
Friedrich Vock
292d7b95fc radv/rmv: Log bo destruction before freeing it
Fixes: abf3bcd6 ("radv: Add RMV resource tracking")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20820>
2023-01-26 01:17:26 +00:00
Friedrich Vock
2d5d247203 radv/rmv: Avoid more CPU unmap deadlocks
Fixes: 8d0e6c02 ("radv: Add RMV tracing utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20820>
2023-01-26 01:17:26 +00:00
Friedrich Vock
2dec10c297 radv/rmv: Also check the other pid field
Sometimes it seems like this field contains the correct pid instead.

Fixes: 8d0e6c02 ("radv: Add RMV tracing utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20820>
2023-01-26 01:17:26 +00:00
Emma Anholt
f6c06ef2f6 ci: Add manual rules variations to disable irrelevant driver jobs.
If you're only affecting one or a couple of drivers, it would be nice if
your pipeline buttons on the web UI weren't full of manual run buttons for
all the other drivers.

This is a bunch of duplicated lines, but less than it could have been now
that we have !references.

In some of these cases (i915g, nouveau, etnaviv), we have no non-manual
jobs for those drivers, so I could have just rewritten the original
"driver-rules" to "driver-manual-rules".  I decided to keep things
consistent between drivers, though, because this is all esoteric enough to
readers already without making different drivers' rules look different.

Fixes: #4891
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17445>
2023-01-26 00:48:19 +00:00
Samuel Pitoiset
a5bff81f47 radv/winsys: prefix all error messages with RADV
RadeonSI prints the exact same message and it can be confusing.
All other error messages in the winsys are prefixed now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20904>
2023-01-25 18:47:52 +00:00
Mike Blumenkrantz
d5846bd1e5 radv: Move constant flushing check out to callers.
Approximately 10% improvement in CPU overhead score on 3900X.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20655>
2023-01-25 18:27:20 +00:00
Konstantin Seurer
3eb646efd0 radv: Merge the leaf and internal converter
We have everything we need in the internal one already so we can just
encode leaf nodes there. Since this functionality isn't split anymore,
the shader was renamed to "encode".

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20768>
2023-01-25 15:54:03 +00:00
Rhys Perry
883f18f761 radv: skip creation of null TLAS for null winsys
This won't work because there are no memory types.

Fixes fossilize replay with NULL winsys.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Fixes: 31ca19589f ("radv: Create a null TLAS as meta state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20878>
2023-01-25 14:16:54 +00:00
Samuel Pitoiset
7b76d46e38 radv: fix RADV_DEBUG=hang with multiple cmdbuffer per submission
With RADV_DEBUG=hang, there is only one cmdbuffer per submission and
this has been broken recently.

This fixes a segfault when generating GPU hang reports.

Fixes: 76deaa1b1a ("radv: Refactor command buffer handling in radv_queue_submit_normal.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20860>
2023-01-25 09:05:11 +00:00
Bas Nieuwenhuizen
75ae391375 radv: Reduce descriptor pool allocation for alignment.
Since we can now rely on this due to the stricter layout code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20847>
2023-01-25 08:45:50 +00:00
Bas Nieuwenhuizen
6a16d3b312 radv: Strictly limit alignment needed within a descriptor set.
By doing two passes we limit the number of times we need to have a gap
after a 16-byte descriptor to align for an image descriptor.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20847>
2023-01-25 08:45:50 +00:00
Yogesh Mohan Marimuthu
44f25792d5 radv: allow NULL initial_preamble_cs in radv_amdgpu_winsys_cs_submit_sysmem()
In case of mcbp, shadowed_regs is initialized early in radv_queue_init()
function by submitting the command buffer. The command buffer is submitted in
radv_init_shadowed_regs_buffer_state() function. When RADV_DEBUG=noibs is used
radv_amdgpu_winsys_cs_submit_sysmem() function is used to submit command buffer.
radv_amdgpu_winsys_cs_submit_sysmem() crashes here because initial_preamble_cs
is NULL. This patch fixes the radv_amdgpu_winsys_cs_submit_sysmem() function
to support NULL initial_preamble_cs.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
c6702e1530 radv: fence complete struct is 4 qw size
also libdrm function amdgpu_cs_chunk_fence_info_to_data() has qw multiplier
and hence need not do it in radv_amdgpu_cs_submit().

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
b11f49f069 radv: INDEX_TYPE and NUM_INSTANCES PKT3 are not shadowed
INDEX_TYPE and NUM_INSTANCES PKT3 should be always written
if shadowing is enabled since they are not shadowed.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
2258090c73 radv: set preemp flag and pre_ena bit for shadowregs
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
97b9b2cf40 radv: add support for register shadowing
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
db61db7f67 radv: add shadowregs variable to RADV_DEBUG environment variable
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Yogesh Mohan Marimuthu
5f0fcc05c2 ac,radeonsi: move shadow regs create ib preamble function to amd common
The si_create_shadowing_ib_preamble() function can be reused from radv also.
Hence it is moved.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
2023-01-25 04:53:34 +00:00
Samuel Pitoiset
49b7f0842e radv: print depth image size with RADV_DEBUG=img
This turned out to be useful when investigating a GPU hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20872>
2023-01-24 15:42:44 +00:00
Samuel Pitoiset
bf3c14b8a5 radv/winsys: fix incorrect PCIID for GFX11 in the null winsys
Fixes: bbad550f3d ("radv/winsys: fill real info for CHIP_GFX1100")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20850>
2023-01-24 08:00:57 +00:00
Emma Anholt
849af68dbd ci/piglit: Add some common piglit skips for Mesa CI's testing of glx.
Since our X servers don't have a compositor, and we run tests in parallel,
various swap and frontbuffer tests won't ever be stable.  Rather than
having every driver have to track those flakes, make a general X11 skips
list as a known issue of our CI rather than pointing fingers at drivers.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20798>
2023-01-24 00:13:02 +00:00
Emma Anholt
ac5b1df2b9 ci: Move PIGLIT_PLATFORM settings out of the .tomls.
I'm going to add some automatic platform-based skips lists shortly (like
all-skips but more targeted), and this avoids needing to add them to each
.toml.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20798>
2023-01-24 00:13:02 +00:00
Mike Blumenkrantz
c26306f7d9 radv: stop using radv_pipeline_has_stage() in BindPipeline
this incurs a small amount of unnecessary cpu overhead as compared to just
checking bitflags

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20615>
2023-01-23 21:04:53 +00:00
Sergi Blanch Torne
cce1f1ea70 ci: Uprev kernel to 6.1.7
Once prepared the archive in gfx-ci/linux for kernel 6.1 pointing to 6.1.7 and
with the patches for mesa, update the link. Also, enable some kconfigs needed
for the Adreno and USB.

One job in AMD required an expectation file to be updated with one test. Also,
an mt8192 device tree has been included in the arm64 trees for lava build.

Co-developed-by: Daniel Stone <daniels@collabora.com>
Co-developed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Co-developed-by: Helen Koike <helen.koike@collabora.com>
Co-developed-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20855>
2023-01-23 19:13:13 +00:00
Georg Lehmann
e527f686ca Revert "aco: Combine v_cvt_u32_f32 with insert to v_cvt_pk_u8_f32."
This reverts commit 6d02054047.

v_cvt_pk_u8_f32 returns 0xff instead of v_cvt_u32_f32 & 0xff if the input is
larger than 255.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8128

Cc: mesa-stable
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20829>
2023-01-23 16:22:55 +00:00
Rhys Perry
26e4621fa2 aco/tests: update assembler tests for latest LLVM 16
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20747>
2023-01-23 12:30:28 +00:00
Rhys Perry
b0fa106dc6 aco/tests: fix assembler.gfx11.vop12c_v128 with LLVM 15
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8089
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20747>
2023-01-23 12:30:28 +00:00
Erik Faye-Lund
9f4f131f2e radeonsi: respect smoothing_enabled
When this was last changed, the smoothing_enabled flag seems to have
been forgotten about, breaking line-smoothing (and probably also polygon
smoothing).

Fixes: 4147add280 ("radeonsi: update db_eqaa even if msaa is disabled")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20810>
2023-01-23 08:41:04 +00:00
Mike Blumenkrantz
5bbeb8f507 radv: add an early out in radv_cmd_buffer_flush_dynamic_state()
no point checking all the states if they're known to be unset

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20653>
2023-01-22 13:27:23 +01:00