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radv: fence complete struct is 4 qw size
also libdrm function amdgpu_cs_chunk_fence_info_to_data() has qw multiplier and hence need not do it in radv_amdgpu_cs_submit(). Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18301>
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1 changed files with 8 additions and 2 deletions
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@ -1531,7 +1531,7 @@ radv_amdgpu_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority prior
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}
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ctx->ws = ws;
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assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
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assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * 4 * sizeof(uint64_t) <= 4096);
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result = ws->base.buffer_create(&ws->base, 4096, 8, RADEON_DOMAIN_GTT,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
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RADV_BO_PRIORITY_CS, 0, &ctx->fence_bo);
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@ -1757,7 +1757,13 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_request
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struct amdgpu_cs_fence_info fence_info;
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fence_info.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
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fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * sizeof(uint64_t);
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/* Need to reserve 4 QWORD for user fence:
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* QWORD[0]: completed fence
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* QWORD[1]: preempted fence
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* QWORD[2]: reset fence
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* QWORD[3]: preempted then reset
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*/
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fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * 4;
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amdgpu_cs_chunk_fence_info_to_data(&fence_info, &chunk_data[i]);
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}
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