Commit graph

193799 commits

Author SHA1 Message Date
GKraats
0311159bed i915g: fix count of buffers at i915_drm_batchbuffer_validate_buffers
This commit contains the fix with num_of_buffers at validation-call
at i915_drm_batchbuffer_validate_buffers.

Cc: mesa-stable

Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26769>
2024-08-18 20:19:44 +00:00
GKraats
ed2123158d i915g: Screen corruption with ENOBUFS caused by fence register shortage
This commit solves the shortage-problem at the blit-functions by
checking the number of fence-registers after updating the batch.
If too many registers are used,
the batch-entries and relocs for the current blit function are
removed by setting batch->ptr and reloc_count to value before
the blit call and calling drm_intel_gem_bo_clear_relocs.
This truncated batch is flushed,
and the batch is updated again for the current blit function.

Cc: mesa-stable

Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26769>
2024-08-18 20:19:44 +00:00
Karol Herbst
93e96da945 rusticl: do not use CL vector types in bindings and code
Bindgen seems to miscompile them and I kinda thought I've done this
already in the past, but apparently not.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11722
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30710>
2024-08-18 09:23:22 +00:00
Caio Oliveira
40f77b6936 intel/brw: Avoid modifying the shader in assign_curb_setup if not needed
If there are no uniforms to push, don't emit the AND or invalidate the
shader analysis.  This affects only compute shaders.

Not a significant impact since lots of shaders end up pushing
uniforms.  Fossil-db numbers (restricted to compute pipelines only) for DG2

```
Totals:
Instrs: 3071016 -> 3070894 (-0.00%)
Cycle count: 8320268863 -> 8320264519 (-0.00%)

Totals from 122 (2.70% of 4520) affected shaders:
Instrs: 10675 -> 10553 (-1.14%)
Cycle count: 2060003 -> 2055659 (-0.21%)
```

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30631>
2024-08-17 16:25:01 -07:00
Caio Oliveira
30ecaf6689 meson: Only use fallback for Lua if building freedreno tools
This keeps the allow_fallback behavior for Lua dependency when freedreno
tools are used, like it used to be.  But will disable the fallback
mechanism otherwise.

For Intel, the dependency is optional and the tool that uses is
skipped when Lua is not available, so it is fine we don't use fallback
there.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30693>
2024-08-17 22:04:53 +00:00
Valentine Burley
71a45e4e0f android: Extract version from llvm-project instead of hardcoding it
Stop hardcoding LLVM version as 12, instead read it from external/llvm-project.

In 81e20472a0
the location of the LLVM_VERSION_MAJOR definition was moved. This patch accounts for that
by extracting the version from the new location if it exists. If the new file is not present,
it falls back to the old location.

Backport-to: 24.2
Tested-by: Antonio Ospite <antonio.ospite@collabora.com>
Tested-by: Alessandro Astone <alessandro.astone@canonical.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30598>
2024-08-17 21:11:08 +00:00
Faith Ekstrand
6a84d5439d nvk: Move the ANTI_ALIAS_CONTROL logic to the MME
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
574798a9a8 nvk: Add macros to sort out tess parameters
We need to flip trianges from CW to CCW based on the domain origin
specified as dynamic state.  Instead of tracking all this on the CPU,
add a scratch register and do the conversion in the MME.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
5a2e25db69 nvk/mme: Add helpers for masked scratch updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
954f274c19 nvk: Move setting VB enables and strides into macros
This effectively splits the two states apart so that we can set them
independently.  Inside the macros, we only update states that have
actually changed which should also be a bit more efficient.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
07d7652624 nvk: Move the guts of BindVertexBuffers2 into a macro
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
b47f928f4b nvk: Move the guts of BindIndexBuffer2KHR to a macro
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
5f29edff07 nvk: Increase the context init size
We're about to add a bunch more MMEs and we're going to blow past the
old limit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
00b6635407 nvk: Emit NVK_MME_SCRATCH_DRAW_BEGIN as part of flush_ia_state()
We're always storing it in a scratch register for register pressure
reasons anyway.  We may as well just stash it there as a state reg and
we can avoid emitting it all over the place.  This reduces each draw
call to nvk_flush_gfx_state() followed by the actual draw, which is now
independenty of any dynamic state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
7d6cc15ab8 nvk/mme: Add a unit test framework for driver macros
Also add tests for NVK_MME_CLEAR to demonstrate the framework.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
03f785083f nvk: Reserve MME scratch area for communicating with FALCON
mme_set_priv_reg() needs the first three registers to send data to/from
FALCON04.  If we don't reserve these in the register space, it may stomp
other things.  This only really matters pre-Volta where we need to use
privileged registers for conservative rasterization.  However, it's a
good idea to reserve the space none the less.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
50a030b02a nouveau/mme: Add a generic simulator function
This one takes a devinfo and decodes and simulates the shader with
whichever sim is appropriate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
33315ce136 nouveau/mme/tu104: Properly handle mthd increment
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
4f14349823 nouveau/mme: Add a pluggable state interface
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
4d2d7d6c15 nouveau/mme/fermi: Break the state simulator into a pluggable component
This is equivalent to the previous commit, but for Fermi.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
aabd7941ce nouveau/mme/tu104: Break the state simulator into a pluggable component
Instead of the state part of the simulator being baked in, it's now
broken out into a pluggable component that the simulator talks to via a
function pointer interface.  This will let us run the simulator without
the full state simulator under the hood.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
79e0b632a2 nouveau/mme: Use a designated initializer in mme_fermi_decode()
Otherwise some fields may not be initialized.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
7d4fafb0e9 nouveau/mme: Allow shifting immediates on Fermi
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
c218bd798f nouveau/mme: Add NOT and AND_NOT ops
Fermi has AND_NOT natively and NOT is just AND_NOT(0, x).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
da96084392 nouveau/mme: Disassemble MERGE more like the mme_merge()
In the builder helper, it's (dst_pos, bits, src_pos).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
8d20ade09b nouveau/mme: Don't allow PRMT and MTHD in the same op on Turing+
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
f5507fb69b nouveau/mme: Better handle the too many immedaties case on Turing+
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:27 +00:00
Faith Ekstrand
381be88473 nouveau/mme: Fix add64 of immediates on Fermi
Fixes: 162269f049 ("nouveau/mme: Add Fermi builder")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:26 +00:00
Faith Ekstrand
f2655b10c7 nouveau/winsys: Fix an undefined shift
It was an integer shift twhich sometimes overflowed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:26 +00:00
Faith Ekstrand
742364cc42 nouveau/headers: Add more nv_push asserts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
2024-08-17 20:32:26 +00:00
Friedrich Vock
bd525f4282 aco: Fix 1D->2D dispatch conversion on <gfx9
out_args->scratch_offset and in_wg_id_x will alias on <gfx9.
To avoid the conversion code reading a garbage WG ID, move the
scratch/ring offset writing to the very end.

Fixes: 1e354172 ("radv,aco: Convert 1D ray launches to 2D")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30707>
2024-08-17 17:01:10 +00:00
Rob Clark
563ec4754a nir/opt_loop: Don't peel initial break if loop ends in break
A loop that looks like:

   loop {
      do_work_1();
      if (cond) {
         break;
      } else {
      }
      do_work_2();
      break;
   }

We can't pull that break ahead of do_work_1() after hoisting the initial
do_work_1() out of the loop.  So bail in this case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11711
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30702>
2024-08-17 14:27:02 +00:00
Marek Olšák
665eae51ef amd: update addrlib
There are some changes in ac_surface.c to make this work.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30507>
2024-08-16 21:44:32 +00:00
Guilherme Gallo
8aa52ac666 ci/a618: Fix zink-tu-a618-full rules
We should use `.zink-turnip-collabora-manual-rules` instead of
`.collabora-turnip-manual-rules`, since the former correctly reacts to
the zink+turnip file changes.

Fixes: 69eac6dd15 ("ci/a618: Add zink-tu-a618-full")

Reported-by: Valentine Burley <valentine.burley@gmail.com>
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30698>
2024-08-16 20:08:35 +00:00
José Roberto de Souza
38c989ada2 anv: Nuke anv_utrace_submit::trace_bo
There is no usage for this bo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
2024-08-16 19:38:19 +00:00
José Roberto de Souza
f7b386bd6d anv: Use batch_bo_pool in utrace anv_async_submit_init() calls
In pratical the only change here is that batch_bo_pool
are captured to error dumps.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
2024-08-16 19:38:19 +00:00
José Roberto de Souza
168e26fc04 anv: Add trivial_batch and query-pool to the error capture
Those are batch buffers that are not allocated from batch_bo_pool,
so they were left out of error capture without the capture-all
parameter.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
2024-08-16 19:38:18 +00:00
Sagar Ghuge
c4f2a8d984 intel/compiler: Fix indirect offset in GS input read for Xe2+
Make sure to take new GRF size into consideration and adjust the
indirect offset according to new size so that when we do the indirect
load with address register, we load right values.

This helps pass the following tests:
   - dEQP-VK.binding_model.descriptor_buffer.mutable_descriptor.*geom*
   - dEQP-VK.ray_query.*geometry_shader.*

Backport-to: 24.2
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30679>
2024-08-16 18:40:13 +00:00
Michael Catanzaro
46a8d5e7ef Disk cache should consistently create parent directories when needed
In !25925 I attempted to fix an error spam caused by the disk cache not
creating parent directories of the cache directory when needed,
resulting in failure to create the disk cache. Presumably that is bad
for performance.

Unfortunately I did a really bad job and only fixed the edge case where
the cache dir is given by $MESA_SHADER_CACHE_DIR rather than the general
case. Here I attempt to be more comprehensive.

Fixes #8294

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30160>
2024-08-16 16:39:37 +00:00
Connor Abbott
93b5e08886 ir3: Fix nir_op_vec8/vec16
For simplicity we create a large repeat group and then split it up
before RA.

Fixes: 58d18bc7a8 ("ir3: lower vectorized NIR instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30691>
2024-08-16 15:39:38 +00:00
Ian Romanick
198d8d9c03 nir/algebraic: Improve some find_lsb and ifind_msb patterns
These patterns were observed in shaders from parallel-rdp.

No shader-db changes on any Intel platform.

fossil-db:

Meteor Lake, DG2, Ice Lake had Skylake similar results. (Meteor Lake shown)
Totals:
Instrs: 152535883 -> 152535673 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17112406110 -> 17122827810 (+0.06%); split: -0.01%, +0.07%
Spill count: 78525 -> 78523 (-0.00%)
Fill count: 148132 -> 148127 (-0.00%); split: -0.01%, +0.00%
Max live registers: 31855320 -> 31855314 (-0.00%)

Totals from 206 (0.03% of 633223) affected shaders:
Instrs: 797124 -> 796914 (-0.03%); split: -0.03%, +0.00%
Cycle count: 4716743323 -> 4727165023 (+0.22%); split: -0.05%, +0.27%
Spill count: 18781 -> 18779 (-0.01%)
Fill count: 31381 -> 31376 (-0.02%); split: -0.03%, +0.01%
Max live registers: 31872 -> 31866 (-0.02%)

Tiger Lake
Totals:
Instrs: 150560465 -> 150560343 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15482372893 -> 15479328542 (-0.02%); split: -0.02%, +0.00%
Fill count: 103509 -> 103512 (+0.00%)
Max live registers: 31760378 -> 31760374 (-0.00%)

Totals from 199 (0.03% of 632445) affected shaders:
Instrs: 679513 -> 679391 (-0.02%); split: -0.02%, +0.00%
Cycle count: 4258406125 -> 4255361774 (-0.07%); split: -0.09%, +0.02%
Fill count: 30609 -> 30612 (+0.01%)
Max live registers: 30502 -> 30498 (-0.01%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30650>
2024-08-16 14:52:04 +00:00
Ian Romanick
c8038643b8 intel/brw: Make ifind_msb SSA friendly
No shader-db changes on any Intel platform.

v2: Use negate(tmp) instead of creating a new temporary. Suggested by
Ken.

fossil-db:

Meteor Lake, DG2, and Skylake had similar results. (Meteor Lake shown)
Totals:
Instrs: 152535897 -> 152535883 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17112329592 -> 17112406110 (+0.00%); split: -0.06%, +0.06%

Totals from 40 (0.01% of 633223) affected shaders:
Instrs: 458813 -> 458799 (-0.00%); split: -0.01%, +0.00%
Cycle count: 4358016282 -> 4358092800 (+0.00%); split: -0.23%, +0.24%

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
Totals:
Instrs: 150560511 -> 150560465 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15484534441 -> 15482372893 (-0.01%); split: -0.12%, +0.11%
Spill count: 59795 -> 59794 (-0.00%)
Fill count: 103513 -> 103509 (-0.00%)

Totals from 40 (0.01% of 632445) affected shaders:
Instrs: 368877 -> 368831 (-0.01%); split: -0.01%, +0.00%
Cycle count: 3918398264 -> 3916236716 (-0.06%); split: -0.49%, +0.43%
Spill count: 16896 -> 16895 (-0.01%)
Fill count: 27819 -> 27815 (-0.01%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30650>
2024-08-16 14:52:04 +00:00
Ian Romanick
e9c151fde6 intel/brw: Make 16-bit ishl, ishr, and ushr SSA friendly
No shader-db changes on any Intel platform.

fossil-db:

All Intel platforms had similar results. (Meteor Lake shown)
Totals:
Instrs: 152536266 -> 152535897 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17124901233 -> 17112329592 (-0.07%); split: -0.07%, +0.00%
Spill count: 78571 -> 78525 (-0.06%)
Fill count: 148178 -> 148132 (-0.03%)

Totals from 210 (0.03% of 633223) affected shaders:
Instrs: 514525 -> 514156 (-0.07%); split: -0.16%, +0.08%
Cycle count: 4003540698 -> 3990969057 (-0.31%); split: -0.32%, +0.00%
Spill count: 15632 -> 15586 (-0.29%)
Fill count: 26241 -> 26195 (-0.18%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30650>
2024-08-16 14:52:04 +00:00
Job Noorman
2c47ad7774 ir3: make ir3_const_state less error-prone to use
ir3_const_state is shared between the binning and non-binning variants.
The non-binning variant is compiled first and sets up ir3_const_state
after which the binning variant is not supposed to modify it anymore. If
it would, things may go haywire since the layout of the constant state
will change after the non-binning variant already finished compiling.

Currently, the ir3_const_state() accessor takes care of the sharing
(i.e., it returns the non-binning const state for the binning variant)
but nothing would be prevent the binning variant from accidentally
modifying the state. This is handled by restraint from its users.

This commit tries to make it more difficult to accidentally modify the
const state by the binning shader by making the following changes:
- ir3_const_state(): the same logic as before but now returns a const
  pointer to prevent the binning variant from (accidentally) modifying
  the const state.
- ir3_const_state_mut(): returns a non-const pointer but asserts that it
  is not called by the binning variant.

As a corollary ir3_get_driver_ubo() also had to be split in two variants
(const and non-const) as it is called with a pointer to one of the
fields of ir3_const_state.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
2024-08-16 14:14:29 +00:00
Job Noorman
7036d0fcf7 ir3: don't modify const state for the binning variant in ir3_cp
ir3_cp uses the const state to lower immediates. It doesn't take the
binning variant into account so in theory, it could add immediates to
the const state for the binning variant, modifying the state after its
layout had already been established for the non-binning variant.

In practice, this probably works fine as the immediates are the last
section of the const state so the layout wouldn't be changed by ir3_cp.
However, there is very little benefit in doing this (the chances for an
immediate being necessary in the binning variant but not in the
non-binning variant are small) so it's better to stick to the global
invariant of not changing the const state in the binning variant.

This commit makes sure that immediates are never added by ir3_cp for the
binning variant. Some refactoring was necessary, however, since the
lookup and modification of the const state were a bit intertwined. More
specifically, currently, the immediate storage in the const state would
always be enlarged by ir3_cp whenever its full, even when it might
actually contain the immediate. To fix this, the logic is split in two
functions: ir3_const_find_imm() for lookup (allowed to be called by the
binning variant), and ir3_const_add_imm for adding immediates (not
allowed to be called by the binning variant).

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
2024-08-16 14:14:29 +00:00
Job Noorman
24b422dc3e ir3: remove unused outputs for binning pass in NIR
We used to remove the unused outputs for the binning pass in ir3. Even
though DCE would be able to clean up most of the mess, there could still
be some left: most notably, unused control flow would not be cleaned up
(leaving some weird branches to empty blocks). Instead of teaching ir3
how to clean this up, it makes more sense to do this at the NIR level,
where we can also benefit from other optimizations.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
2024-08-16 14:14:29 +00:00
Job Noorman
bec7e79f33 freedreno: don't require binning and non-binning inputs to match
This shouldn't be necessary anymore since f6f7bc29 ("freedreno/a6xx:
Program VFD_DEST_CNTL from program stateobj").

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
2024-08-16 14:14:29 +00:00
Robert Mader
c738cfe8dd egl: Stop requiring texture_3D_image for EGL 1.5
Neither VK-GL-CTS nor dri2_setup_screen() require it, unlike
texture_2D_image and texture_cubemap_image. Crucially, older etnaviv
generations and vc4 in general do not support 3d textures.

Thus drop the requirement in order to support EGL 1.5 across the board.

Signed-off-by: Robert Mader <robert.mader@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30680>
2024-08-16 13:36:47 +00:00
Karmjit Mahil
3c4fb8f7fa tu: Implement VK_EXT_legacy_dithering
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30536>
2024-08-16 13:05:56 +00:00
Karmjit Mahil
110201cfd8 freedreno: Define SP_DITHER_CNTL (0xA9AC)
Seems to be the same as RB_DITHER_CNTL. Both get set to 0x5555
when dithering is enabled on the proprietary gles driver.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30536>
2024-08-16 13:05:56 +00:00