Commit graph

67634 commits

Author SHA1 Message Date
Xavier Bouchoux
072e2ba8e1 st/nine: Add missing c++ declaration for IDirect3DVolumeTexture9
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
2015-01-22 22:16:17 +00:00
Xavier Bouchoux
8bb550b958 st/nine: Additional defines to d3dtypes.h
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
2015-01-22 22:16:17 +00:00
Axel Davy
3bc75fcf22 st/nine: Fix clip state logic
The clip state was reset everytime, incurring an overhead.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
2015-01-22 22:16:17 +00:00
David Heidelberger
23fae79735 st/nine: query: remove unused variable (trivial)
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: David Heidelberg <david@ixit.cz>
2015-01-22 22:16:16 +00:00
Eric Anholt
fc6938d23e nir: Fix setup of constant bool initializers.
brw_fs_nir has only seen scalar bools so far, thanks to vector splitting,
and the ralloc of in glsl_to_nir.cpp will *usually* get you a 0-filled
chunk of memory, so reading too large of a value will usually get you the
right bool value.  But once we start doing vector bools in a few commits,
we end up getting bad values.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-01-22 13:52:19 -08:00
Eric Anholt
534a4ec82f nir: Make an easier helper for setting up SSA defs.
Almost all instructions we nir_ssa_def_init() for are nir_dests, and you
have to keep from forgetting to set is_ssa when you do.  Just provide the
simpler helper, instead.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-01-22 13:52:19 -08:00
Jonathan Gray
c5be9c126d glsl: Link glsl_test with pthreads library.
Otherwise pthread_mutex_lock will be an undefined reference
on OpenBSD.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88219
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
2015-01-22 21:29:43 +00:00
Vinson Lee
9db7b12cb2 scons: Add X11 include path if X11 is available.
Mac OS X XQuartz places X11 headers at /opt/X11/include.

This patch fixes this Mac OS X SCons build error.

  Compiling src/gallium/state_trackers/glx/xlib/glx_api.c ...
In file included from src/gallium/state_trackers/glx/xlib/glx_api.c:34:
include/GL/glx.h:30:10: fatal error: 'X11/Xlib.h' file not found
         ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-01-22 21:29:43 +00:00
José Fonseca
fea35bbf6d meta: Move loop declaration to top of block.
Fixes MSVC build.

Trvial.
2015-01-22 20:06:17 +00:00
Jason Ekstrand
d5d4ba9139 i965/tex_subimage: use meta instead of the blitter for PBO TexSubImage
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:37:13 -08:00
Jason Ekstrand
779923194c i965/tex_image: Use meta for instead of the blitter PBO TexImage and GetTexImage
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:37:09 -08:00
Jason Ekstrand
ef0499af25 i965/pixel_read: Use meta_pbo_GetTexSubImage for PBO ReadPixels
Since the meta path can do strictly more than the blitter path, we just
remove the blitter path entirely.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:36:25 -08:00
Jason Ekstrand
8546fe900c meta: Add an implementation of GetTexSubImage for PBOs
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:36:24 -08:00
Jason Ekstrand
7f396189f0 meta: Add a BlitFramebuffers-based implementation of TexSubImage
This meta path, designed for use with PBO's, creates a temporary texture
out of the PBO and uses BlitFramebuffers to do the actual texture upload.

v2 Jason Ekstrand <jason.ekstrand@intel.com>:
 - Add support for handling simple packing options

v3 Jason Ekstrand <jason.ekstrand@intel.com>:
 - Refactor to split out the texture-from-pbo code
 - Rename to _mesa_meta_pbo_TexSubImage

Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:36:24 -08:00
Jason Ekstrand
e24d17e08c formats: Use a hash table for _mesa_format_from_array_format
Going through the for loop every time has noticable overhead.  This fixes
things up so we only do that once ever and then just do a hash table lookup
which should be much cheaper.

v2 Jason Ekstrand <jason.ekstrand@intel.com>:
 - Use once_flag and call_once from c11/threads.h instead of pthreads

Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:35:43 -08:00
Jason Ekstrand
333226522c i965: Implement SetTextureStorageForBufferObject
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:21:07 -08:00
Jason Ekstrand
117a1d69de i965: Apply the miptree offset to surface state for renderbuffers
Previously, we were completely ignoring the mt->offset field for
renderbuffers.  While it does have some alignment constraints, it is valid
to use it.  This patch adds the code to each of the 4 surface state setup
functions to handle it.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:21:07 -08:00
Jason Ekstrand
404660e3c7 i965/mipmap_tree: Add a depth parameter to create_for_bo
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:21:07 -08:00
Jason Ekstrand
3298b1235a mesa/dd: Add a function for creating a texture from a buffer object
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2015-01-22 10:21:07 -08:00
Tapani Pälli
adc8cdfa35 glsl: do not allow interface block to have name already taken
Fixes currently failing Piglit case
   interface-blocks-name-reused-globally.vert

v2: combine var declaration with assignment (Ian)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-01-22 07:54:19 +02:00
Matt Turner
28b7c6b285 nir: Replace assert(0) with unreachable().
Fixes a couple of warnings in the process.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-01-21 21:06:37 -08:00
Matt Turner
6de077f01d i965/vec4: Fix fprintf argument ordering.
Introduced in commit 3167a80b.
2015-01-21 20:17:26 -08:00
Jason Ekstrand
f88c6a4997 nir: Stop using designated initializers
Designated initializers with anonymous unions don't work in MSVC or
GCC < 4.6.  With a couple of constructor methods, we don't need them any
more and the code is actually cleaner.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88467
Reviewed-by: Connor Abbot <cwabbott0@gmail.com>
2015-01-21 19:55:02 -08:00
Tobias Klausmann
76086d7120 mesa: change assert to unreachable in two format functions
This fixes two problems reported by osc:
I: Program returns random data in a function
E: Mesa no-return-in-nonvoid-function ../../src/mesa/main/format_utils.c:180
E: Mesa no-return-in-nonvoid-function ../../src/mesa/main/glformats.c:2714

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
2015-01-21 13:17:27 -08:00
Jason Ekstrand
7da60eca4f nir: Add src and dest constructors
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-01-21 12:21:10 -08:00
Jan Vesely
3c3e60e050 mesa: Add assert to check number of vector elements
The below code crashes when vector_elements <= 0
Fixes Warray-bounds warnings

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-01-21 14:06:02 +00:00
Jan Vesely
3cb10cce37 mesa: Fix some signed-unsigned comparison warnings
v2: s/unsigned int/unsigned/ in prog_optimize.c

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-01-21 14:05:52 +00:00
Jan Vesely
da1f92779d mesa: remove comparisons that are always true
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-01-21 14:05:04 +00:00
Jason Ekstrand
194f6235b3 nir: Add a nir_foreach_phi_src helper macro
Reviewed-by: Connor Abbott <cwabbott02gmail.com>
2015-01-20 16:53:29 -08:00
Ben Widawsky
169d7e5cb1 i965: Extract scalar region checking logic
There are currently 2 users of this functionality. I have 2 more users coming
up, and having a simple function makes the results much cleaner. The existing
interface semantics was proposed by Matt.

v2 (Ken): Rename to region_matches()/has_scalar_region().

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-20 15:24:40 -08:00
Ben Widawsky
9394f58383 i965: Add QWORD sizes to type_sz macro
GEN8 added the QWORD as a valid type for certain operations on the EU.
In order to calculate the number of registers used one must have the type
size as part of the equation. Quoting the formula in the code:

   regs_written = (dst.width * dst.stride * type_sz(dst.type) + 31) / 32;

Adding this separately for bisection since there is no simple way to add
an assert in the type_sz function.

NOTE: As a side note, I was confused for a while because it's impossible
to calculate the region, ie. registers needed, without vstride.  However,
at this point these are all part of the IR, and so no vstride must exist.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-20 15:24:40 -08:00
Eric Anholt
b368c91f26 vc4: Fix build since 8ed5305d28 2015-01-20 14:19:29 -08:00
Rob Clark
fd6e18d651 freedreno/a4xx: sysmem bypass
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-01-20 13:27:28 -05:00
Rob Clark
5da3bec44b freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-01-20 13:27:19 -05:00
Tom Stellard
17a2f11a06 radeonsi: Re-enable LLVM IR dumps
This was inadvertently disabled by
761e36b4ca.
2015-01-20 09:55:44 -05:00
Tom Stellard
73bc0fdb6f radeonsi/compute: Use relocs for scratch pointer rather than user sgprs v2
Instead of passing a pointer to the scratch buffer via user sgprs, we
now patch the shader with the buffer address using reloc information
from the LLVM generated ELF.

v2:
  - Make sure not to break older LLVM.
2015-01-20 09:55:44 -05:00
Tom Stellard
dfdaf3eb7e radeon: Teach radeon_elf_read() how to parse reloc information v3
v2:
  - Use strdup for copying reloc names.
  - Free reloc memory.

v3:
  - Add free_relocs parameter to radeon_shader_binary_free_members()
2015-01-20 09:55:43 -05:00
Tom Stellard
5667aa58c4 radeon: Add a helper function for freeing members of radeon_shader_binary 2015-01-20 09:55:43 -05:00
Kenneth Graunke
c4fd0c9052 i965: Work around mysterious Gen4 GPU hangs with minimal state changes.
Gen4 hardware appears to GPU hang frequently when using Chromium, and
also when running 'glmark2 -b ideas'.  Most of the error states contain
3DPRIMITIVE commands in quick succession, with very few state packets
between them - usually VERTEX_BUFFERS/ELEMENTS and CONSTANT_BUFFER.

I trimmed an apitrace of the glmark2 hang down to two draw calls with a
glUniformMatrix4fv call between the two.  Either draw by itself works
fine, but together, they hang the GPU.  Removing the glUniform call
makes the hangs disappear.  In the hardware state, this translates to
removing the CONSTANT_BUFFER packet between the two 3DPRIMITIVE packets.

Flushing before emitting CONSTANT_BUFFER packets also appears to make
the hangs disappear.  I observed a slowdown in glxgears by doing it all
the time, so I've chosen to only do it when BRW_NEW_BATCH and
BRW_NEW_PSP are unset (i.e. we haven't done a CS_URB_STATE change or
already flushed the whole pipeline).

I'd much rather understand the problem, but at this point, I don't see
how we'd ever be able to track it down further.  We have no real tools,
and the hardware people moved on years ago.  I've analyzed 20+ error
states and read every scrap of documentation I could find.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80568
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85367
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
2015-01-19 13:13:51 -08:00
Kenneth Graunke
a5ca86a983 i965/nir: Enable SIMD16 support in the NIR FS backend.
With the previous commits in place, it just works.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-01-19 13:13:50 -08:00
Kenneth Graunke
45123ee818 i965/nir: Use offset() instead of altering reg_offset directly.
offset() properly handles reg_width, so it'll work for SIMD16.

While we're in the area, simplify a few cases, and use retype() to cut a
few more lines of code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-01-19 13:13:48 -08:00
Kenneth Graunke
3f263ffbb3 i965/nir: Replace fs_reg(GRF, virtual_grf_alloc(...)) with vgrf(...).
brw_fs_nir.cpp creates almost all of its registers via:

   fs_reg reg = fs_reg(GRF, virtual_grf_alloc(num_components));

When we add SIMD16 support, we'll need to set reg->width = 16 and
double the VGRF size...on pretty much every VGRF it allocates.

This patch replaces that pattern with a new "vgrf" helper method:

   fs_reg reg = vgrf(num_components);

The new function correctly takes reg_width into account.  For now,
reg_width is always 1, so this should have no functional change.

v2: Just make vgrf() account for reg_width right away, rather than
    changing the behavior in the next patch.

v3: Replace one last virtual_grf_alloc I missed.  It's used in code
    that only runs for dispatch_width == 8, so it doesn't matter,
    but consistency is nice.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-01-19 13:13:46 -08:00
Kenneth Graunke
d1533d87cc i965: Replace fs_reg(fs_visitor, type) with fs_visitor::vgrf(type).
I dislike how fs_reg has a constructor that knows about fs_visitor.
Apart from that, it stands alone, with no need to interact with the
rest of the compiler.  Which is sensible - a class that represents
a register should do just that.  Allocating virtual register numbers
should be left up to the compiler (fs_visitor).

This patch replaces the constructor with a new fs_visitor::vgrf method,
eliminating fs_reg's dependency on fs_visitor.  It ends up being no
more code.

v2: Rebase from May 2014 -> January 2015.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-01-19 13:13:34 -08:00
Marek Olšák
5b01512df3 st/mesa: don't set vs.key.clamp_color if a shader doesn't write any colors
And update some comments.
2015-01-19 20:15:27 +01:00
Marek Olšák
ccc5b60b06 winsys/radeon: increase the size of buffer cache
This should fix this performance regression:
https://bugs.freedesktop.org/show_bug.cgi?id=88227

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-01-19 20:15:27 +01:00
Carl Worth
3b8ccca8a3 Rename sha1.c and sha1.h to mesa-sha1.c and mesa-sha1.h
The filename of sha1.h was conflicting with the system-provided
sha1.h, (and in some confiurations, our sha1.c was unsuccessfully
attemping to include "sha1.h" and <sha1.h> as two different files).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88523
2015-01-19 10:53:07 -08:00
Martin Peres
7a182d2335 mesa: fix a trivial spelling mistake
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-19 01:23:07 -08:00
Tapani Pälli
d74a817b86 mesa: support GL_RGB for GL_EXT_texture_type_2_10_10_10_REV
Commit 8ec6534 changed texture upload path and the way how texture
format is being checked, this commit adds support for GL_RGB with
GL_UNSIGNED_INT_2_10_10_10_REV as specified by the extension
EXT_texture_type_2_10_10_10_REV specification.

This fixes regression in ES3 conformance test
   ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels

v2: add MESA_FORMAT_R10G10B10X2_UNORM format (Iago Toral)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88385
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-01-19 08:11:45 +02:00
Micah Fedke
d36fa60191 mesa: Add ARB_shader_precision infrastructure
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-01-19 16:33:21 +13:00
Kenneth Graunke
461103ef64 i965/fs: Fix the dummy fragment shader.
We hit an assertion that the destination of the FB write should not be
an immediate.  (I don't know what we were thinking.)  Use ARF null.

Trying to substitute real shaders with the dummy shader would crash
when trying to upload non-existent uniforms.  Say there are none.

It also wouldn't generate any code because we didn't compute the CFG,
and code generation now requires it.  Compute it.

Gen4-5 also require a message header to be present.

On Gen6+, there were assertion failures in SF/SBE state because
urb_setup was memset to 0 instad of -1, causing it to think there were
attributes when nothing was set up right.  Set to no attributes.

Finally, you have to ensure "Setup URB Entry Read Length" is non-zero
or you get GPU hangs, at least on Crestline.

It now works on at least Crestline and Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2015-01-17 14:20:41 -08:00