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Author SHA1 Message Date
Samuel Pitoiset
17c5a91028 radv: move event related code to radv_event.c 
radv_device.c is getting too big.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>
 2023-03-08 16:21:10 +00:00
Samuel Pitoiset
4de305cb8a radv: move sampler related code to radv_sampler.c 
radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>
 2023-03-08 16:21:10 +00:00
Samuel Pitoiset
7a157b3a4c radv: move queue related code to radv_queue.c 
radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>
 2023-03-08 16:21:10 +00:00
Samuel Pitoiset
4e5db63482 radv: move physical device related code to radv_physical_device.c 
radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>
 2023-03-08 16:21:10 +00:00
Samuel Pitoiset
06fa90e14e radv: move instance related code to radv_instance.c 
radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>
 2023-03-08 16:21:10 +00:00
Rhys Perry
98cb7e0108 nir: add nir_lower_alu_width_test.fdot_order 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>
 2023-03-08 14:38:26 +00:00
Rhys Perry
50f7e21481 nir: make fdph lowering match fdot 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>
 2023-03-08 14:38:26 +00:00
Rhys Perry
3668da7c83 nir: use xyzw order for precise fdot 
Fixes flickering grass in Immortals Fenyx Rising.

fossil-db (gfx1100):
Totals from 13969 (10.38% of 134574) affected shaders:
MaxWaves: 442794 -> 442878 (+0.02%)
Instrs: 4861105 -> 4901408 (+0.83%); split: -0.02%, +0.85%
CodeSize: 24316100 -> 24396272 (+0.33%); split: -0.03%, +0.35%
VGPRs: 446256 -> 445572 (-0.15%); split: -0.20%, +0.05%
Latency: 28122456 -> 28162233 (+0.14%); split: -0.10%, +0.24%
InvThroughput: 2899673 -> 2904323 (+0.16%); split: -0.07%, +0.23%
VClause: 119599 -> 119631 (+0.03%); split: -0.07%, +0.09%
SClause: 186636 -> 186265 (-0.20%); split: -0.23%, +0.03%
Copies: 301370 -> 300386 (-0.33%); split: -0.75%, +0.42%
Branches: 85066 -> 85047 (-0.02%); split: -0.02%, +0.00%
PreSGPRs: 436167 -> 436137 (-0.01%)
PreVGPRs: 329715 -> 329809 (+0.03%); split: -0.01%, +0.04%

fossil-db (gfx1100, RADV_DEBUG=invariantgeom):
Totals from 43116 (32.04% of 134574) affected shaders:
MaxWaves: 1332938 -> 1333012 (+0.01%); split: +0.01%, -0.00%
Instrs: 16424513 -> 16658021 (+1.42%); split: -0.06%, +1.48%
CodeSize: 81258868 -> 81827860 (+0.70%); split: -0.07%, +0.77%
VGPRs: 1720368 -> 1719648 (-0.04%); split: -0.19%, +0.15%
SpillSGPRs: 1670 -> 1600 (-4.19%); split: -5.27%, +1.08%
Latency: 82063766 -> 82425418 (+0.44%); split: -0.23%, +0.67%
InvThroughput: 9665803 -> 9727810 (+0.64%); split: -0.09%, +0.73%
VClause: 449662 -> 451099 (+0.32%); split: -0.32%, +0.64%
SClause: 498841 -> 498639 (-0.04%); split: -0.24%, +0.20%
Copies: 1001020 -> 1000770 (-0.02%); split: -1.20%, +1.17%
Branches: 237580 -> 239637 (+0.87%); split: -0.01%, +0.88%
PreSGPRs: 1198167 -> 1198024 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 1225202 -> 1225035 (-0.01%); split: -0.06%, +0.05%

fossil-db (navi10):
Totals from 13969 (10.38% of 134563) affected shaders:
MaxWaves: 474386 -> 474508 (+0.03%); split: +0.05%, -0.03%
Instrs: 3740895 -> 3771566 (+0.82%); split: -0.00%, +0.82%
CodeSize: 19426592 -> 19459916 (+0.17%); split: -0.00%, +0.18%
VGPRs: 389916 -> 389852 (-0.02%); split: -0.09%, +0.07%
Latency: 25452927 -> 25502482 (+0.19%); split: -0.14%, +0.34%
InvThroughput: 3880807 -> 3923144 (+1.09%); split: -0.07%, +1.16%
VClause: 66835 -> 66712 (-0.18%); split: -0.38%, +0.20%
SClause: 178805 -> 178802 (-0.00%); split: -0.01%, +0.01%
Copies: 167601 -> 167625 (+0.01%); split: -0.54%, +0.56%
Branches: 83788 -> 83784 (-0.00%)
PreSGPRs: 388229 -> 388216 (-0.00%)
PreVGPRs: 342984 -> 343062 (+0.02%); split: -0.01%, +0.03%

fossil-db (navi10, RADV_DEBUG=invariantgeom):
Totals from 43116 (32.04% of 134563) affected shaders:
MaxWaves: 1260184 -> 1256414 (-0.30%); split: +0.10%, -0.40%
Instrs: 12804951 -> 12983628 (+1.40%); split: -0.01%, +1.41%
CodeSize: 65813224 -> 66137852 (+0.49%); split: -0.03%, +0.52%
VGPRs: 1556396 -> 1561340 (+0.32%); split: -0.09%, +0.41%
SpillSGPRs: 1377 -> 1395 (+1.31%)
Latency: 76095867 -> 76355111 (+0.34%); split: -0.32%, +0.66%
InvThroughput: 13546863 -> 13788789 (+1.79%); split: -0.05%, +1.84%
VClause: 310910 -> 311283 (+0.12%); split: -0.63%, +0.75%
SClause: 474878 -> 474941 (+0.01%); split: -0.09%, +0.10%
Copies: 639367 -> 637610 (-0.27%); split: -1.03%, +0.76%
Branches: 240178 -> 240185 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1056594 -> 1056590 (-0.00%); split: -0.00%, +0.00%
PreVGPRs: 1247950 -> 1247798 (-0.01%); split: -0.05%, +0.04%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7920
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>
 2023-03-08 14:38:26 +00:00
Mike Blumenkrantz
6ee5337d94 aux/tc: fix rp info resizing clobbering current info 
the recording rp_info may be a pointer to a member of the array being
reallocated, so test for this and re-set it to avoid invalid memory
access

found with this caselist:
KHR-GL46.texture_gather.offset-gather-unorm-2darray
KHR-GL46.texture_view.view_sampling

cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21729>
 2023-03-08 14:10:01 +00:00
Lionel Landwerlin
10057d19f2 anv: report max register pressure in pipeline properties 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21756>
 2023-03-08 13:37:07 +00:00
Lionel Landwerlin
09cdb77a92 intel/fs: report max register pressure in shader stats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21756>
 2023-03-08 13:37:07 +00:00
Lionel Landwerlin
8dd960e056 anv/iris: report counter symbols with debug option 
v2: rename to INTEL_DEBUG=perf-symbol-names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17672>
 2023-03-08 12:45:43 +00:00
Samuel Pitoiset
e6735409ee radv: disable DCC with signedness reinterpretation on GFX11 
All formats should be compatible on GFX11 but for some weird reasons
DCC with signedness reinterpretation doesn't work as expected, like
R8_UINT<->R8_SINT. Note that RadeonSI also has issues with this.

This might be a hardware bug on RDNA3.

This fixes DCC issues with Cyberpunk and A Plague Tale: Requiem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8020
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8371
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21755>
 2023-03-08 11:53:25 +00:00
Pierre-Eric Pelloux-Prayer
79ab787a8f radeonsi: fix fast depth_clear_value/stencil_clear_value 
We need to update the when promoting from non-TC-compatible to
TC-compatible or we'll get incorrect values in the buffer.

Fixes: 9defe8aca9 ("radeonsi: implement fast Z/S clears using clear_buffer on HTILE")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8418
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>
 2023-03-08 10:56:21 +00:00
Pierre-Eric Pelloux-Prayer
b75acbf88f radeonsi: don't use PKT3_SET_SH_REG_INDEX on gfx9 and older 
Fixes: ccaaf8fe04 ("amd: massively simplify how info->spi_cu_en is applied")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8464
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>
 2023-03-08 10:56:21 +00:00
Pierre-Eric Pelloux-Prayer
49913fa418 radeonsi/test: update test results 
Depends on https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/779
to fix glx-make-current GLX errors.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>
 2023-03-08 10:56:21 +00:00
Pierre-Eric Pelloux-Prayer
9eb05801ad radeonsi/test: use gbm-skips.txt 
Use shared skips file to avoid running tests that can't pass on gbm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>
 2023-03-08 10:56:21 +00:00
Samuel Pitoiset
f88dbb27d4 radv: enable VK_KHR_fragment_shading_rate on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Samuel Pitoiset
1fb8e0eff2 radv: advertise attachmentFragmentShadingRate on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Samuel Pitoiset
d1e724b952 radv: do not emit PA_SC_VRS_OVERRIDE_CNTL from the pipeline on GFX11 
PA_SC_VRS_OVERRIDE_CNTL is emitted when a framebuffer is bound because
it controls the VRS surface enable bit. Though, if a pipeline is bound
after the framebuffer is emitted, it can override the state. Remove it
completely since VRS for flat shading and RADV_FORCE_VRS are disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Samuel Pitoiset
c186420b26 radv: add support for VRS attachment on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Samuel Pitoiset
31d699106d ac/surface: add RADEON_SURF_VRS_RATE for selecting swizzle mode on GFX11 
On GFX11, VRS rate images can't use linear tiling and the swizzle mode
must be either SW_Z or SW_R.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Samuel Pitoiset
ce4a1b1c3c radv: move disabling DCC for VRS rate images in radv_get_surface_flags() 
On GFX11, the VRS rate image needs a specific swizzle mode and a new
flag will be added here.

gned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
 2023-03-08 10:30:48 +00:00
Lionel Landwerlin
e8793f2a86 anv: enable VK_EXT_pipeline_library_group_handles 
A noop for us.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20929>
 2023-03-08 08:59:52 +00:00
Marek Olšák
461ccb00e1 radeonsi: increase NGG workgroup size to 256 for VS/TES with streamout and GS 
NGG streamout performance is limited by the workgroup size, so make it as
large as possible.

Since this uses si_get_max_workgroup_size() to set the NGG workgroup size,
the side effect is that all GS is also getting an increase to 256, which
is OK.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
43fd552872 radeonsi: allow using 64K LDS for NGG to allow larger workgroups 
This should help with NGG streamout performance, which is limited by
the workgroup size (it should be as large as possible).

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
e01d505291 radeonsi: other cosmetic changes in si_state_shaders.cpp 
VS_W32_EN has no effect on Gfx11, but we better not set it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
ef965d5681 radeonsi: reorganize si_shader_ps 
To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
c9d297fc77 radeonsi: reorganize si_shader_ngg 
To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
1664aad43c radeonsi: reorganize si_shader_hs 
To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
b3459eae7a radeonsi: reindent si_shader_ls, si_shader_es, si_shader_gs, si_shader_vs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
7e0ed2c4f0 radeonsi: set pm4.atom.emit in si_get_shader_pm4_state 
except gfx10_shader_ngg, which isn't as trivial

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
4c1475fc1c radeonsi: lower nir_texop_sampler_descriptor_amd 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
1417ced72c radeonsi: separate nir_texop_descriptor_amd lowering 
This moves the code to a separate branch to make it less intertwined
with the rest to allow sampler descriptor lowering later.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
54ebd90739 radeonsi: merge si_emit_initial_compute_regs with si_init_cs_preamble_state 
It's better to set all immutable registers in one place.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Marek Olšák
ddded6fbb5 radeonsi: emulate VGT_ESGS_RING_ITEMSIZE in the shader on gfx9-11 
The hardware uses the register to premultiply GS vertex indices
in input VGPRs.

This changes the behavior as follows:
- VGT_ESGS_RING_ITEMSIZE is always 1 on gfx9-11, set in the preamble.
- The value is passed to the shader via current_gs_state (vs_state_bits).
- The shader does the multiplication.

The reason is that VGT_ESGS_RING_ITEMSIZE will be removed in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Timur Kristóf
fb819fdb13 ac/nir: clear nir_var_shader_out from TCS barriers 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
 2023-03-08 07:29:09 +00:00
Timur Kristóf
87de5b2b9e aco: Don't include headers from radv. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
a0141c6308 aco, radv: Don't use radv_shader_args in aco. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
e9793331db aco, radv: Move PS epilog and VS prolog args to their info structs. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
84a2cea596 aco, radv: Rename aco_*_key to aco_*_info. 
The naming of aco_*_key didn't make sense because they
were never actually used as cache keys, only radv_*_key
are used as cache keys.

Rename the aco structs to aco_*_info instead.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Qiang Yu
91e68db0e1 aco, radv: Move is_trap_handler_shader to aco info. 
v2 by Timur Kristóf:
- Rebase this patch on latest main.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Qiang Yu
978220c99a aco, radv: Add load_grid_size_from_user_sgpr to aco options. 
v2 by Timur Kristóf:
- Rebase this patch.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
3058ab6090 aco: Generalize vs_inputs to args_pending_vmem. 
Handle arguments that need a waitcnt without relying on
RADV specific VS input information.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
1583bea9da radv: Set pending_vmem on dynamic VS input args. 
These are loaded from VMEM and need a waitcnt before use.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Timur Kristóf
1a7b5979df ac: Add pending_vmem field to args. 
This is to indicate when an argument was loaded from VMEM
and needs a waitcnt before it can be used.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
 2023-03-08 04:39:18 +00:00
Rob Clark
d5376c3feb freedreno: Promote non-drawing batches to sysmem 
Sometimes we can end up with a sequence where we need to flush a batch
with no clears and no draws (for ex, to get a fence).  Promote these to
sysmem.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21747>
 2023-03-08 04:10:45 +00:00
Mike Blumenkrantz
aaed609e57 zink: hook up buffer TRANSFER_DST barrier optimizing 
this should massively optimize e.g., incremental index buffer overwrites

ref #8358

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
 2023-03-08 03:50:33 +00:00
Mike Blumenkrantz
fe469a7618 zink: add a driver workaround to disable copy box optimizations 
turnip is nonconformant regarding cache access (see noted issue),
meaning that any attempt to omit barriers breaks things

qcom proprietary may also be affected

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
 2023-03-08 03:50:33 +00:00
Mike Blumenkrantz
46f98da188 zink: add a mechanism to trigger copy box resets from batch state reset 
the resource isn't available during batch state reset, so a new flag
is needed to force a reset the next time the copy boxes would be used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
 2023-03-08 03:50:33 +00:00