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ac/surface: add RADEON_SURF_VRS_RATE for selecting swizzle mode on GFX11

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On GFX11, VRS rate images can't use linear tiling and the swizzle mode
must be either SW_Z or SW_R.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>
This commit is contained in:
Samuel Pitoiset 2023-02-16 10:44:21 +01:00 • committed by Marge Bot
parent ce4a1b1c3c
commit 31d699106d
2 changed files with 9 additions and 0 deletions
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8
src/amd/common/ac_surface.c
View file

@ -2310,6 +2310,14 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
break;
}
/* On GFX11, the only allowed swizzle mode for VRS rate images is
* 64KB_R_X.
*/
if (info->gfx_level >= GFX11 && surf->flags & RADEON_SURF_VRS_RATE) {
AddrSurfInfoIn.swizzleMode = ADDR_SW_64KB_R_X;
break;
}
r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
&AddrSurfInfoIn.swizzleMode);
if (r)

1
src/amd/common/ac_surface.h
View file

@ -88,6 +88,7 @@ enum radeon_micro_mode
#define RADEON_SURF_NO_HTILE (1ull << 30)
#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31)
#define RADEON_SURF_PRT (1ull << 32)
#define RADEON_SURF_VRS_RATE (1ull << 33)
struct legacy_surf_level {
uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */