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aco: Generalize vs_inputs to args_pending_vmem.
Handle arguments that need a waitcnt without relying on RADV specific VS input information. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
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4 changed files with 17 additions and 28 deletions
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@ -1032,11 +1032,9 @@ insert_wait_states(Program* program)
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std::stack<unsigned, std::vector<unsigned>> loop_header_indices;
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unsigned loop_progress = 0;
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if (program->stage.has(SWStage::VS) && program->info.vs.dynamic_inputs) {
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for (Definition def : program->vs_inputs) {
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update_counters(in_ctx[0], event_vmem);
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insert_wait_entry(in_ctx[0], def, event_vmem);
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}
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for (Definition def : program->args_pending_vmem) {
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update_counters(in_ctx[0], event_vmem);
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insert_wait_entry(in_ctx[0], def, event_vmem);
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}
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for (unsigned i = 0; i < program->blocks.size();) {
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@ -11271,10 +11271,15 @@ add_startpgm(struct isel_context* ctx)
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ctx->arg_temps[i] = create_vec_from_array(ctx, elems, size, RegType::sgpr, 4);
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} else {
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Temp dst = ctx->program->allocateTmp(type);
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Definition def(dst);
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def.setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256});
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ctx->arg_temps[i] = dst;
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startpgm->definitions[arg] = Definition(dst);
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startpgm->definitions[arg].setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256});
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arg++;
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startpgm->definitions[arg++] = def;
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if (ctx->args->ac.args[i].pending_vmem) {
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assert(file == AC_ARG_VGPR);
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ctx->program->args_pending_vmem.push_back(def);
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}
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}
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}
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@ -11294,18 +11299,6 @@ add_startpgm(struct isel_context* ctx)
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}
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}
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if (ctx->stage.has(SWStage::VS) && ctx->program->info.vs.dynamic_inputs) {
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unsigned num_attributes = util_last_bit(ctx->program->info.vs.input_slot_usage_mask);
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for (unsigned i = 0; i < num_attributes; i++) {
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Definition def(get_arg(ctx, ctx->args->vs_inputs[i]));
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unsigned idx = ctx->args->vs_inputs[i].arg_index;
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def.setFixed(PhysReg(256 + ctx->args->ac.args[idx].offset));
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ctx->program->vs_inputs.push_back(def);
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}
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}
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return startpgm;
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}
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@ -2120,7 +2120,7 @@ public:
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unsigned next_divergent_if_logical_depth = 0;
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unsigned next_uniform_if_depth = 0;
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std::vector<Definition> vs_inputs;
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std::vector<Definition> args_pending_vmem;
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struct {
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FILE* output = stderr;
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@ -544,13 +544,11 @@ collect_preasm_stats(Program* program)
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double usage[(int)BlockCycleEstimator::resource_count] = {0};
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std::vector<BlockCycleEstimator> blocks(program->blocks.size(), program);
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if (program->stage.has(SWStage::VS) && program->info.vs.has_prolog) {
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unsigned vs_input_latency = 320;
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for (Definition def : program->vs_inputs) {
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blocks[0].vm.push_back(vs_input_latency);
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for (unsigned i = 0; i < def.size(); i++)
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blocks[0].reg_available[def.physReg().reg() + i] = vs_input_latency;
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}
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constexpr const unsigned vmem_latency = 320;
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for (const Definition def : program->args_pending_vmem) {
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blocks[0].vm.push_back(vmem_latency);
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for (unsigned i = 0; i < def.size(); i++)
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blocks[0].reg_available[def.physReg().reg() + i] = vmem_latency;
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}
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for (Block& block : program->blocks) {
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