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24433 commits 66 branches 934 tags 1 GiB
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Author SHA1 Message Date
Maciej Cencora
12a6d73c75 r300: handle relative addressing in NQSSADCE 2009-07-13 19:28:11 +02:00
Maciej Cencora
96b2eb18c5 r300: handle ARB_vertex_program specific instructions in NQSSADCE 2009-07-13 19:28:07 +02:00
Maciej Cencora
e43cc28c1b r300: move depth output rewrite out of NQSSADCE 2009-07-13 19:25:59 +02:00
Maciej Cencora
f79ef95df4 r300: rewrite FOGC and HPOS attribs handling 
Rewrite vertex and fragment programs so that we don't have to do any hacks on lower level.
 2009-07-13 19:25:59 +02:00
Maciej Cencora
df5fe747fa r300: bind vertex program to fragment program 2009-07-13 19:25:58 +02:00
Maciej Cencora
d1e4caa6e2 r300: recalculate used inputs and outputs after dead code removal 2009-07-13 19:25:58 +02:00
Maciej Cencora
7360f83364 r300: move fragment program selection before vertex program selection 
Prepare for wpos and fogc handling rewrite.
 2009-07-13 19:25:58 +02:00
Maciej Cencora
37c319f62f r300: implement proper IsProgramNative check for vertex programs 2009-07-13 19:25:57 +02:00
Maciej Cencora
bce224c1f1 r300: don't modify original vertex program 
Keep the original vertex program untouched because it may be needed after some state change for generating new r300 specific vertex program.
 2009-07-13 19:25:57 +02:00
Maciej Cencora
7829b7a1b8 r300: cache translated fragment programs 2009-07-13 19:25:56 +02:00
Maciej Cencora
28066ed012 r300: update state parameters only once per rendering operation 2009-07-13 19:25:56 +02:00
Maciej Cencora
21db37d432 r300: translate non native insts earlier for easier debugging 2009-07-13 19:25:55 +02:00
Maciej Cencora
0b411a72f3 r300: print vertex program after adding artificial output insts 2009-07-13 19:25:55 +02:00
Maciej Cencora
4a6899e080 r300: use mesa provided function for adding MVP code 2009-07-13 19:25:54 +02:00
Maciej Cencora
9b781ca2ce r300: simplify insert_wpos a little 2009-07-13 19:25:54 +02:00
Brian Paul
9615daa932 Merge branch 'mesa_7_5_branch' 2009-07-13 08:47:37 -06:00
Dave Airlie
bb4c703587 radeon: port more front fixes from intel. 
Port fixes to read buffer from front.
 2009-07-14 01:23:24 +10:00
Dave Airlie
504d01b275 radeon/r200: fix color masking under dri2 
Need to retrieve the bits from the rrb not from screen struct
 2009-07-14 01:23:24 +10:00
Dave Airlie
a79aefb177 radeon: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers. 
The _Enabled field isn't updated at the point that DrawBuffers is called,
and the Driver.Enable() function does the testing for stencil buffer
presence anyway.
 2009-07-14 01:23:23 +10:00
Dave Airlie
d9913d7c09 radeon/fbo: stencil bits fix from Michel in intel fbo code 2009-07-14 01:23:23 +10:00
Peteri Andras
680f7d09b0 r128: fix two-sided lighting segfault seen in GLUT's olight demo 2009-07-13 08:04:08 -06:00
Ian Romanick
022e8e582e intel: Bump driver data, add RC3 tag 2009-07-12 21:07:38 -07:00
Xiang, Haihao
2995bf0d68 i965: add support for new chipsets 
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
 2009-07-13 11:01:13 +08:00
Dave Airlie
f030e2ba17 r300: move fallback warnings inside fallback debugging 
random output is bad
 2009-07-12 21:37:47 +10:00
Dave Airlie
dfecf217fa r300: fix clear mask to not use sw if not necessary 2009-07-12 21:37:46 +10:00
Nicolai Hähnle
b484c71036 radeon: Fix crash when rendering to incomplete texture and other formats 
It is possible to bind texture images of an incomplete mipmapped texture.
Software fallbacks in this case incorrectly tried to mmap the entire texture.

Additionally, add span functions for 1555 and 4444 formats.

This fixes crashes in piglit's fbo-readpixels test; unfortunately, the test
itself still fails - this needs to be investigated.

Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
 2009-07-12 12:50:36 +02:00
Dave Airlie
a10244453c radeon: update clear code from Intel codebase. 
This updates some of the clear code from Intel gives a 5x clearspd perf
for me here. played openarena also, not sure if the viewport changes
broke anything,
 2009-07-12 17:28:14 +10:00
Dave Airlie
b06cb372bf radeon: fbo fix firecube crashes 
it might still be misrendering not sure
 2009-07-12 12:13:40 +10:00
Michel Dänzer
65059606e9 radeon: Fix scissor rectangle calculation when rendering to FBO. 
fgl_glxgears -fbo runs, though the gears don't look right yet.
 2009-07-11 20:25:09 +02:00
Zack Rusin
1c1307e7c5 gallium: compare the actual register, not all the inputs 
otherwise we decrement indexes for all registers
 2009-07-11 13:48:41 -04:00
Brian Paul
cff2126f52 tgsi: update some assertions 2009-07-10 16:26:09 -06:00
Brian Paul
a79586ce18 tgsi: tgsi: add semantic_names[] string for TGSI_SEMANTIC_FACE 
Same story as in the tgsi_dump.c code (see prev commit).
 2009-07-10 15:44:48 -06:00
Brian Paul
f01af4dbd2 tgsi: add semantic_names[] string for TGSI_SEMANTIC_FACE 
Fixes TGSI dump output when front/back-face register is declared.

Also, add some assertions to make sure the semantic/interpolate string
arrays have as many elements as there are tokens in the p_shader_tokens.h
file.  That should catch problems like this in the future.
 2009-07-10 15:41:26 -06:00
Brian Paul
762c1d11ff st/mesa: implement indirect addressing for destination registers 2009-07-10 13:09:09 -06:00
Brian Paul
baa7ff47d5 tgis: implement indirect addressing for destination registers 
Includes the TGSI interpreter, but not the SSE/PPC/etc code generators.
 2009-07-10 13:09:09 -06:00
Brian Paul
ca1b71b78d vbo: fix vbo/dlist memory leak 
Based on a patch by kristof.ralovich@gmail.com
 2009-07-10 13:09:09 -06:00
Brian Paul
6ff1a5385e demos: set 4th component of texcoord to 1.0 
Avoid potential randomness in resulting texcoords.
 2009-07-10 13:09:09 -06:00
Dave Airlie
db618427ab radeon: enable GL_NV_texture_rectangle under dri2. 2009-07-11 03:17:13 +10:00
Dave Airlie
85957cb512 radeon: set texture in state properly. 
make sure to turn off when no texture is used in hw
 2009-07-11 03:17:12 +10:00
Dave Airlie
a6a11e1dc0 radeon: make swtcl emit size bigger 2009-07-11 03:17:12 +10:00
Alex Deucher
37c0cde80a R6xx/r7xx: use packet 3 for scratch emit 
no need to allow packet 0 scratch regs in the drm
 2009-07-10 12:04:56 -04:00
Michel Dänzer
cade071d52 Remove stale reference to non-Gallium nouveau driver from configure.ac. 2009-07-10 14:49:46 +02:00
Ian Romanick
fcd3572edf mesa: From float type modifier from values to large for singles 
The values 2147483648.0 and 4294967294.0 are too larget to be stored in single
precision floats.  Forcing these to be singles causes bits to be lost, which
results in errors in some pixel transfer tests.

This fixes bug #22344.
(cherry picked from commit 70e72070fc)
 2009-07-09 16:07:05 -07:00
Alex Deucher
0de26dba2e R6xx/r7xx: disable CS dump 
Don't fprintf to a xterm with the lock held.
 2009-07-09 17:15:23 -04:00
Brian Paul
8987410ab6 Merge branch 'mesa_7_5_branch' 2009-07-09 08:05:56 -06:00
Brian Paul
78af70be37 docs: document gl_TextureMatrix[i][j] array indexing bug fix 2009-07-09 08:04:07 -06:00
Brian Paul
c86b076668 glsl: do const parameter optimization for array element actual parameters 
When a function parameter is const-qualified we can avoid making a copy
of the actual parameter (we basically do a search/replace when inlining).
This is now done for array element params too, resulting in better code
(fewer MOV instructions).

We should allow some other types of function arguments here but let's be
conservative for the moment.
 2009-07-09 07:58:50 -06:00
Brian Paul
abdb0fdcc0 glsl: fix incorrect indexing for gl_TextureMatrix[i][j] 
The two indexes were mixed up when accessing a row of a matrix in an array
of matrices.
 2009-07-09 07:57:29 -06:00
Brian Paul
36e906aad6 docs: document glMaterial/glShadeModel display list optimization 2009-07-08 14:14:03 -06:00
Richard Li
93ab69a0ef Fix buffer age implementaion bug. 2009-07-08 14:49:48 -04:00