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mesa/src/intel/genxml/gen8.xml

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genxml: Add XML version tags There's not much point to having them or not having them but this reduces some pointless diff from the version we can auto-generate Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-15 22:33:00 -07:00
<?xml version="1.0" ?>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<genxml name="BDW" gen="8">
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Prim_Topo_Type" prefix="3DPRIM">
<value name="POINTLIST" value="1"/>
<value name="LINELIST" value="2"/>
<value name="LINESTRIP" value="3"/>
<value name="TRILIST" value="4"/>
<value name="TRISTRIP" value="5"/>
<value name="TRIFAN" value="6"/>
<value name="QUADLIST" value="7"/>
<value name="QUADSTRIP" value="8"/>
<value name="LINELIST_ADJ" value="9"/>
<value name="LINESTRIP_ADJ" value="10"/>
<value name="TRILIST_ADJ" value="11"/>
<value name="TRISTRIP_ADJ" value="12"/>
<value name="TRISTRIP_REVERSE" value="13"/>
<value name="POLYGON" value="14"/>
<value name="RECTLIST" value="15"/>
<value name="LINELOOP" value="16"/>
<value name="POINTLIST _BF" value="17"/>
<value name="LINESTRIP_CONT" value="18"/>
<value name="LINESTRIP_BF" value="19"/>
<value name="LINESTRIP_CONT_BF" value="20"/>
<value name="TRIFAN_NOSTIPPLE" value="22"/>
<value name="PATCHLIST_1" value="32"/>
<value name="PATCHLIST_2" value="33"/>
<value name="PATCHLIST_3" value="34"/>
<value name="PATCHLIST_4" value="35"/>
<value name="PATCHLIST_5" value="36"/>
<value name="PATCHLIST_6" value="37"/>
<value name="PATCHLIST_7" value="38"/>
<value name="PATCHLIST_8" value="39"/>
<value name="PATCHLIST_9" value="40"/>
<value name="PATCHLIST_10" value="41"/>
<value name="PATCHLIST_11" value="42"/>
<value name="PATCHLIST_12" value="43"/>
<value name="PATCHLIST_13" value="44"/>
<value name="PATCHLIST_14" value="45"/>
<value name="PATCHLIST_15" value="46"/>
<value name="PATCHLIST_16" value="47"/>
<value name="PATCHLIST_17" value="48"/>
<value name="PATCHLIST_18" value="49"/>
<value name="PATCHLIST_19" value="50"/>
<value name="PATCHLIST_20" value="51"/>
<value name="PATCHLIST_21" value="52"/>
<value name="PATCHLIST_22" value="53"/>
<value name="PATCHLIST_23" value="54"/>
<value name="PATCHLIST_24" value="55"/>
<value name="PATCHLIST_25" value="56"/>
<value name="PATCHLIST_26" value="57"/>
<value name="PATCHLIST_27" value="58"/>
<value name="PATCHLIST_28" value="59"/>
<value name="PATCHLIST_29" value="60"/>
<value name="PATCHLIST_30" value="61"/>
<value name="PATCHLIST_31" value="62"/>
<value name="PATCHLIST_32" value="63"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Vertex_Component_Control" prefix="VFCOMP">
<value name="NOSTORE" value="0"/>
<value name="STORE_SRC" value="1"/>
<value name="STORE_0" value="2"/>
<value name="STORE_1_FP" value="3"/>
<value name="STORE_1_INT" value="4"/>
<value name="STORE_PID" value="7"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="WRAP_SHORTEST_ENABLE" prefix="WSE">
<value name="X" value="1"/>
<value name="Y" value="2"/>
<value name="XY" value="3"/>
<value name="Z" value="4"/>
<value name="XZ" value="5"/>
<value name="YZ" value="6"/>
<value name="XYZ" value="7"/>
<value name="W" value="8"/>
<value name="XW" value="9"/>
<value name="YW" value="10"/>
<value name="XYW" value="11"/>
<value name="ZW" value="12"/>
<value name="XZW" value="13"/>
<value name="YZW" value="14"/>
<value name="XYZW" value="15"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Stencil_Operation" prefix="STENCILOP">
<value name="KEEP" value="0"/>
<value name="ZERO" value="1"/>
<value name="REPLACE" value="2"/>
<value name="INCRSAT" value="3"/>
<value name="DECRSAT" value="4"/>
<value name="INCR" value="5"/>
<value name="DECR" value="6"/>
<value name="INVERT" value="7"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Color_Buffer_Blend_Factor" prefix="BLENDFACTOR">
<value name="ONE" value="1"/>
<value name="SRC_COLOR" value="2"/>
<value name="SRC_ALPHA" value="3"/>
<value name="DST_ALPHA" value="4"/>
<value name="DST_COLOR" value="5"/>
<value name="SRC_ALPHA_SATURATE" value="6"/>
<value name="CONST_COLOR" value="7"/>
<value name="CONST_ALPHA" value="8"/>
<value name="SRC1_COLOR" value="9"/>
<value name="SRC1_ALPHA" value="10"/>
<value name="ZERO" value="17"/>
<value name="INV_SRC_COLOR" value="18"/>
<value name="INV_SRC_ALPHA" value="19"/>
<value name="INV_DST_ALPHA" value="20"/>
<value name="INV_DST_COLOR" value="21"/>
<value name="INV_CONST_COLOR" value="23"/>
<value name="INV_CONST_ALPHA" value="24"/>
<value name="INV_SRC1_COLOR" value="25"/>
<value name="INV_SRC1_ALPHA" value="26"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Color_Buffer_Blend_Function" prefix="BLENDFUNCTION">
<value name="ADD" value="0"/>
<value name="SUBTRACT" value="1"/>
<value name="REVERSE_SUBTRACT" value="2"/>
<value name="MIN" value="3"/>
<value name="MAX" value="4"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Compare_Function" prefix="COMPAREFUNCTION">
<value name="ALWAYS" value="0"/>
<value name="NEVER" value="1"/>
<value name="LESS" value="2"/>
<value name="EQUAL" value="3"/>
<value name="LEQUAL" value="4"/>
<value name="GREATER" value="5"/>
<value name="NOTEQUAL" value="6"/>
<value name="GEQUAL" value="7"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Logic_Op_Function" prefix="LOGICOP">
<value name="CLEAR" value="0"/>
<value name="NOR" value="1"/>
<value name="AND_INVERTED" value="2"/>
<value name="COPY_INVERTED" value="3"/>
<value name="AND_REVERSE" value="4"/>
<value name="INVERT" value="5"/>
<value name="XOR" value="6"/>
<value name="NAND" value="7"/>
<value name="AND" value="8"/>
<value name="EQUIV" value="9"/>
<value name="NOOP" value="10"/>
<value name="OR_INVERTED" value="11"/>
<value name="COPY" value="12"/>
<value name="OR_REVERSE" value="13"/>
<value name="OR" value="14"/>
<value name="SET" value="15"/>
</enum>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="Shader Channel Select" prefix="SCS">
<value name="ZERO" value="0"/>
<value name="ONE" value="1"/>
<value name="RED" value="4"/>
<value name="GREEN" value="5"/>
<value name="BLUE" value="6"/>
<value name="ALPHA" value="7"/>
</enum>
<enum name="Clear Color">
<value name="CC_ZERO" value="0"/>
<value name="CC_ONE" value="1"/>
</enum>
<enum name="Texture Coordinate Mode" prefix="TCM">
<value name="WRAP" value="0"/>
<value name="MIRROR" value="1"/>
<value name="CLAMP" value="2"/>
<value name="CUBE" value="3"/>
<value name="CLAMP_BORDER" value="4"/>
<value name="MIRROR_ONCE" value="5"/>
<value name="HALF_BORDER" value="6"/>
</enum>
<struct name="3DSTATE_CONSTANT_BODY" length="10">
genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays. This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-15 16:15:13 -07:00
<group count="4" start="0" size="16">
<field name="Read Length" start="0" end="15" type="uint"/>
</group>
<group count="4" start="64" size="64">
<field name="Buffer" start="5" end="63" type="address"/>
</group>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
</struct>
<struct name="BINDING_TABLE_EDIT_ENTRY" length="1">
<field name="Binding Table Index" start="16" end="23" type="uint"/>
<field name="Surface State Pointer" start="0" end="15" type="offset"/>
</struct>
<struct name="GATHER_CONSTANT_ENTRY" length="1">
<field name="Constant Buffer Offset" start="8" end="15" type="offset"/>
<field name="Channel Mask" start="4" end="7" type="uint"/>
<field name="Binding Table Index Offset" start="0" end="3" type="uint"/>
</struct>
<struct name="MEMORY_OBJECT_CONTROL_STATE" length="1">
<field name="Memory Type:LLC/eLLC Cacheability Control" start="5" end="6" type="uint">
<value name=" UC with Fence (if coherent cycle)" value="0"/>
<value name="UC (Uncacheable)" value="1"/>
<value name="WT" value="2"/>
<value name="WB" value="3"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Target Cache" start="3" end="4" type="uint">
<value name="eLLC Only (when eDRAM is present, else gets allocated in LLC)" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC Allowed" value="2"/>
<value name="L3 + Defer to PAT for LLC/eLLC selection" value="3"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Age for QUADLRU" start="0" end="1" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</struct>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="VERTEX_BUFFER_STATE" length="4">
<field name="Vertex Buffer Index" start="26" end="31" type="uint"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="16" end="22" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Address Modify Enable" start="14" end="14" type="bool"/>
<field name="Null Vertex Buffer" start="13" end="13" type="bool"/>
<field name="Buffer Pitch" start="0" end="11" type="uint"/>
<field name="Buffer Starting Address" start="32" end="95" type="address"/>
<field name="Buffer Size" start="96" end="127" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</struct>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="VERTEX_ELEMENT_STATE" length="2">
<field name="Vertex Buffer Index" start="26" end="31" type="uint"/>
<field name="Valid" start="25" end="25" type="bool"/>
intel: Drop SURFACE_FORMAT enum from genxml. We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-02-13 18:13:51 -08:00
<field name="Source Element Format" start="16" end="24" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Edge Flag Enable" start="15" end="15" type="bool"/>
<field name="Source Element Offset" start="0" end="11" type="uint"/>
intel/genxml: Use enum 3D_Vertex_Component_Control where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:20:23 -08:00
<field name="Component 0 Control" start="60" end="62" type="3D_Vertex_Component_Control"/>
<field name="Component 1 Control" start="56" end="58" type="3D_Vertex_Component_Control"/>
<field name="Component 2 Control" start="52" end="54" type="3D_Vertex_Component_Control"/>
<field name="Component 3 Control" start="48" end="50" type="3D_Vertex_Component_Control"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
</struct>
intel: genxml: add SAMPLER_BORDER_COLOR_STATE structures Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-10-12 20:04:26 +01:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SO_DECL" length="1">
<field name="Output Buffer Slot" start="12" end="13" type="uint"/>
<field name="Hole Flag" start="11" end="11" type="uint"/>
<field name="Register Index" start="4" end="9" type="uint"/>
<field name="Component Mask" start="0" end="3" type="uint" default="0"/>
intel: genxml: add SAMPLER_BORDER_COLOR_STATE structures Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-10-12 20:04:26 +01:00
</struct>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SO_DECL_ENTRY" length="2">
<field name="Stream 3 Decl" start="48" end="63" type="SO_DECL"/>
<field name="Stream 2 Decl" start="32" end="47" type="SO_DECL"/>
<field name="Stream 1 Decl" start="16" end="31" type="SO_DECL"/>
<field name="Stream 0 Decl" start="0" end="15" type="SO_DECL"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</struct>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SF_OUTPUT_ATTRIBUTE_DETAIL" length="1">
<field name="Component Override W" start="15" end="15" type="bool"/>
<field name="Component Override Z" start="14" end="14" type="bool"/>
<field name="Component Override Y" start="13" end="13" type="bool"/>
<field name="Component Override X" start="12" end="12" type="bool"/>
<field name="Swizzle Control Mode" start="11" end="11" type="uint"/>
<field name="Constant Source" start="9" end="10" type="uint">
<value name="CONST_0000" value="0"/>
<value name="CONST_0001_FLOAT" value="1"/>
<value name="CONST_1111_FLOAT" value="2"/>
<value name="PRIM_ID" value="3"/>
</field>
<field name="Swizzle Select" start="6" end="7" type="uint">
<value name="INPUTATTR" value="0"/>
<value name="INPUTATTR_FACING" value="1"/>
<value name="INPUTATTR_W" value="2"/>
<value name="INPUTATTR_FACING_W" value="3"/>
</field>
<field name="Source Attribute" start="0" end="4" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</struct>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SCISSOR_RECT" length="2">
<field name="Scissor Rectangle Y Min" start="16" end="31" type="uint"/>
<field name="Scissor Rectangle X Min" start="0" end="15" type="uint"/>
<field name="Scissor Rectangle Y Max" start="48" end="63" type="uint"/>
<field name="Scissor Rectangle X Max" start="32" end="47" type="uint"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SF_CLIP_VIEWPORT" length="16">
<field name="Viewport Matrix Element m00" start="0" end="31" type="float"/>
<field name="Viewport Matrix Element m11" start="32" end="63" type="float"/>
<field name="Viewport Matrix Element m22" start="64" end="95" type="float"/>
<field name="Viewport Matrix Element m30" start="96" end="127" type="float"/>
<field name="Viewport Matrix Element m31" start="128" end="159" type="float"/>
<field name="Viewport Matrix Element m32" start="160" end="191" type="float"/>
<field name="X Min Clip Guardband" start="256" end="287" type="float"/>
<field name="X Max Clip Guardband" start="288" end="319" type="float"/>
<field name="Y Min Clip Guardband" start="320" end="351" type="float"/>
<field name="Y Max Clip Guardband" start="352" end="383" type="float"/>
<field name="X Min ViewPort" start="384" end="415" type="float"/>
<field name="X Max ViewPort" start="416" end="447" type="float"/>
<field name="Y Min ViewPort" start="448" end="479" type="float"/>
<field name="Y Max ViewPort" start="480" end="511" type="float"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="BLEND_STATE_ENTRY" length="2">
<field name="Logic Op Enable" start="63" end="63" type="bool"/>
intel/genxml: Use enum 3D_Logic_Op_Function where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:46:05 -08:00
<field name="Logic Op Function" start="59" end="62" type="3D_Logic_Op_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Pre-Blend Source Only Clamp Enable" start="36" end="36" type="bool"/>
<field name="Color Clamp Range" start="34" end="35" type="uint">
<value name="COLORCLAMP_UNORM" value="0"/>
<value name="COLORCLAMP_SNORM" value="1"/>
<value name="COLORCLAMP_RTFORMAT" value="2"/>
</field>
<field name="Pre-Blend Color Clamp Enable" start="33" end="33" type="bool"/>
<field name="Post-Blend Color Clamp Enable" start="32" end="32" type="bool"/>
<field name="Color Buffer Blend Enable" start="31" end="31" type="bool"/>
intel/genxml: Use blend function and factor enums where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:42:46 -08:00
<field name="Source Blend Factor" start="26" end="30" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Destination Blend Factor" start="21" end="25" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Color Blend Function" start="18" end="20" type="3D_Color_Buffer_Blend_Function"/>
<field name="Source Alpha Blend Factor" start="13" end="17" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Destination Alpha Blend Factor" start="8" end="12" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Alpha Blend Function" start="5" end="7" type="3D_Color_Buffer_Blend_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Write Disable Alpha" start="3" end="3" type="bool"/>
<field name="Write Disable Red" start="2" end="2" type="bool"/>
<field name="Write Disable Green" start="1" end="1" type="bool"/>
<field name="Write Disable Blue" start="0" end="0" type="bool"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
genxml: Make BLEND_STATE command support variable length array. We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-30 11:33:05 -07:00
<struct name="BLEND_STATE" length="1">
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Alpha To Coverage Enable" start="31" end="31" type="bool"/>
<field name="Independent Alpha Blend Enable" start="30" end="30" type="bool"/>
<field name="Alpha To One Enable" start="29" end="29" type="bool"/>
<field name="Alpha To Coverage Dither Enable" start="28" end="28" type="bool"/>
<field name="Alpha Test Enable" start="27" end="27" type="bool"/>
intel/genxml: Use 3D_Compare_Function for gen8+ test functions When the state fields where shuffled around for gen8, the compare function enums were downgraded to just uints. Change them to enum 3D_Compare_Function. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:38:04 -08:00
<field name="Alpha Test Function" start="24" end="26" type="3D_Compare_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Color Dither Enable" start="23" end="23" type="bool"/>
<field name="X Dither Offset" start="21" end="22" type="uint"/>
<field name="Y Dither Offset" start="19" end="20" type="uint"/>
genxml: Make BLEND_STATE command support variable length array. We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-30 11:33:05 -07:00
<group count="0" start="32" size="64">
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Entry" start="0" end="63" type="BLEND_STATE_ENTRY"/>
</group>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="CC_VIEWPORT" length="2">
<field name="Minimum Depth" start="0" end="31" type="float"/>
<field name="Maximum Depth" start="32" end="63" type="float"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="COLOR_CALC_STATE" length="6">
<field name="Stencil Reference Value" start="24" end="31" type="uint"/>
genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS. - "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-19 16:13:20 -07:00
<field name="Backface Stencil Reference Value" start="16" end="23" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Round Disable Function Disable" start="15" end="15" type="bool"/>
<field name="Alpha Test Format" start="0" end="0" type="uint">
<value name="ALPHATEST_UNORM8" value="0"/>
<value name="ALPHATEST_FLOAT32" value="1"/>
</field>
<field name="Alpha Reference Value As UNORM8" start="32" end="63" type="uint"/>
<field name="Alpha Reference Value As FLOAT32" start="32" end="63" type="float"/>
<field name="Blend Constant Color Red" start="64" end="95" type="float"/>
<field name="Blend Constant Color Green" start="96" end="127" type="float"/>
<field name="Blend Constant Color Blue" start="128" end="159" type="float"/>
<field name="Blend Constant Color Alpha" start="160" end="191" type="float"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="INTERFACE_DESCRIPTOR_DATA" length="8">
intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATA This one was split across two dwords as "Kernel Start Pointer" and "Kernel Start Pointer High", which looks like it works when the driver only accesses "Kernel Start Pointer". This breaks, of course, with BO offsets > 4G. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 21:00:34 -08:00
<field name="Kernel Start Pointer" start="6" end="47" type="offset"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Denorm Mode" start="83" end="83" type="uint">
<value name="Ftz" value="0"/>
<value name="SetByKernel" value="1"/>
</field>
<field name="Single Program Flow" start="82" end="82" type="bool"/>
<field name="Thread Priority" start="81" end="81" type="uint">
<value name="Normal Priority" value="0"/>
<value name="High Priority" value="1"/>
</field>
<field name="Floating Point Mode" start="80" end="80" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="77" end="77" type="bool"/>
<field name="Mask Stack Exception Enable" start="75" end="75" type="bool"/>
<field name="Software Exception Enable" start="71" end="71" type="bool"/>
<field name="Sampler State Pointer" start="101" end="127" type="offset"/>
<field name="Sampler Count" start="98" end="100" type="uint">
<value name="No samplers used" value="0"/>
<value name="Between 1 and 4 samplers used" value="1"/>
<value name="Between 5 and 8 samplers used" value="2"/>
<value name="Between 9 and 12 samplers used" value="3"/>
<value name="Between 13 and 16 samplers used" value="4"/>
</field>
<field name="Binding Table Pointer" start="133" end="143" type="offset"/>
<field name="Binding Table Entry Count" start="128" end="132" type="uint"/>
<field name="Constant URB Entry Read Length" start="176" end="191" type="uint"/>
<field name="Constant URB Entry Read Offset" start="160" end="175" type="uint"/>
<field name="Rounding Mode" start="214" end="215" type="uint">
<value name="RTNE" value="0"/>
<value name="RU" value="1"/>
<value name="RD" value="2"/>
<value name="RTZ" value="3"/>
</field>
<field name="Barrier Enable" start="213" end="213" type="bool"/>
<field name="Shared Local Memory Size" start="208" end="212" type="uint">
<value name="Encodes 0k" value="0"/>
<value name="Encodes 4k" value="1"/>
<value name="Encodes 8k" value="2"/>
<value name="Encodes 16k" value="4"/>
<value name="Encodes 32k" value="8"/>
<value name="Encodes 64k" value="16"/>
</field>
<field name="Number of Threads in GPGPU Thread Group" start="192" end="201" type="uint"/>
<field name="Cross-Thread Constant Data Read Length" start="224" end="231" type="uint"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="PALETTE_ENTRY" length="1">
<field name="Alpha" start="24" end="31" type="uint"/>
<field name="Red" start="16" end="23" type="uint"/>
<field name="Green" start="8" end="15" type="uint"/>
<field name="Blue" start="0" end="7" type="uint"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="BINDING_TABLE_STATE" length="1">
<field name="Surface State Pointer" start="6" end="31" type="offset"/>
</struct>
<struct name="RENDER_SURFACE_STATE" length="16">
<field name="Surface Type" start="29" end="31" type="uint">
<value name="SURFTYPE_1D" value="0"/>
<value name="SURFTYPE_2D" value="1"/>
<value name="SURFTYPE_3D" value="2"/>
<value name="SURFTYPE_CUBE" value="3"/>
<value name="SURFTYPE_BUFFER" value="4"/>
<value name="SURFTYPE_STRBUF" value="5"/>
<value name="SURFTYPE_NULL" value="7"/>
</field>
<field name="Surface Array" start="28" end="28" type="bool"/>
intel: Drop SURFACE_FORMAT enum from genxml. We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-02-13 18:13:51 -08:00
<field name="Surface Format" start="18" end="26" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Surface Vertical Alignment" start="16" end="17" type="uint">
<value name="VALIGN 4" value="1"/>
<value name="VALIGN 8" value="2"/>
<value name="VALIGN 16" value="3"/>
</field>
<field name="Surface Horizontal Alignment" start="14" end="15" type="uint">
<value name="HALIGN 4" value="1"/>
<value name="HALIGN 8" value="2"/>
<value name="HALIGN 16" value="3"/>
</field>
<field name="Tile Mode" start="12" end="13" type="uint">
<value name="LINEAR" value="0"/>
<value name="WMAJOR" value="1"/>
<value name="XMAJOR" value="2"/>
<value name="YMAJOR" value="3"/>
</field>
<field name="Vertical Line Stride" start="11" end="11" type="uint"/>
<field name="Vertical Line Stride Offset" start="10" end="10" type="uint"/>
<field name="Sampler L2 Bypass Mode Disable" start="9" end="9" type="bool"/>
<field name="Render Cache Read Write Mode" start="8" end="8" type="uint">
<value name="Write-Only Cache" value="0"/>
<value name="Read-Write Cache" value="1"/>
</field>
<field name="Media Boundary Pixel Mode" start="6" end="7" type="uint">
<value name="NORMAL_MODE" value="0"/>
<value name="PROGRESSIVE_FRAME" value="2"/>
<value name="INTERLACED_FRAME" value="3"/>
</field>
<field name="Cube Face Enable - Positive Z" start="0" end="0" type="bool"/>
<field name="Cube Face Enable - Negative Z" start="1" end="1" type="bool"/>
<field name="Cube Face Enable - Positive Y" start="2" end="2" type="bool"/>
<field name="Cube Face Enable - Negative Y" start="3" end="3" type="bool"/>
<field name="Cube Face Enable - Positive X" start="4" end="4" type="bool"/>
<field name="Cube Face Enable - Negative X" start="5" end="5" type="bool"/>
<field name="MOCS" start="56" end="62" type="uint"/>
<field name="Base Mip Level" start="51" end="55" type="u4.1"/>
<field name="Surface QPitch" start="32" end="46" type="uint"/>
<field name="Height" start="80" end="93" type="uint"/>
<field name="Width" start="64" end="77" type="uint"/>
<field name="Depth" start="117" end="127" type="uint"/>
<field name="Surface Pitch" start="96" end="113" type="uint"/>
<field name="Render Target And Sample Unorm Rotation" start="157" end="158" type="uint">
<value name="0DEG" value="0"/>
<value name="90DEG" value="1"/>
<value name="270DEG" value="3"/>
</field>
<field name="Minimum Array Element" start="146" end="156" type="uint"/>
<field name="Render Target View Extent" start="135" end="145" type="uint"/>
<field name="Multisampled Surface Storage Format" start="134" end="134" type="uint">
<value name="MSFMT_MSS" value="0"/>
<value name="MSFMT_DEPTH_STENCIL" value="1"/>
</field>
<field name="Number of Multisamples" start="131" end="133" type="uint">
<value name="MULTISAMPLECOUNT_1" value="0"/>
<value name="MULTISAMPLECOUNT_2" value="1"/>
<value name="MULTISAMPLECOUNT_4" value="2"/>
<value name="MULTISAMPLECOUNT_8" value="3"/>
</field>
<field name="Multisample Position Palette Index" start="128" end="130" type="uint"/>
<field name="X Offset" start="185" end="191" type="uint"/>
<field name="Y Offset" start="181" end="183" type="uint"/>
<field name="EWA Disable For Cube" start="180" end="180" type="bool"/>
<field name="Coherency Type" start="174" end="174" type="uint">
<value name="GPU coherent" value="0"/>
<value name="IA coherent" value="1"/>
</field>
<field name="Surface Min LOD" start="164" end="167" type="uint"/>
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Auxiliary Surface QPitch" start="208" end="222" type="uint"/>
<field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
<field name="Auxiliary Surface Mode" start="192" end="194" type="uint">
<value name="AUX_NONE" value="0"/>
<value name="AUX_MCS" value="1"/>
<value name="AUX_APPEND" value="2"/>
<value name="AUX_HIZ" value="3"/>
</field>
<field name="Separate UV Plane Enable" start="223" end="223" type="bool"/>
<field name="X Offset for U or UV Plane" start="208" end="221" type="uint"/>
<field name="Y Offset for U or UV Plane" start="192" end="205" type="uint"/>
intel: genxml: make a couple of enums show up in aubinator In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-06-30 17:25:43 +01:00
<field name="Red Clear Color" start="255" end="255" type="Clear Color"/>
<field name="Green Clear Color" start="254" end="254" type="Clear Color"/>
<field name="Blue Clear Color" start="253" end="253" type="Clear Color"/>
<field name="Alpha Clear Color" start="252" end="252" type="Clear Color"/>
<field name="Shader Channel Select Red" start="249" end="251" type="Shader Channel Select"/>
<field name="Shader Channel Select Green" start="246" end="248" type="Shader Channel Select"/>
<field name="Shader Channel Select Blue" start="243" end="245" type="Shader Channel Select"/>
<field name="Shader Channel Select Alpha" start="240" end="242" type="Shader Channel Select"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Resource Min LOD" start="224" end="235" type="u4.8"/>
<field name="Surface Base Address" start="256" end="319" type="address"/>
<field name="X Offset for V Plane" start="368" end="381" type="uint"/>
<field name="Y Offset for V Plane" start="352" end="365" type="uint"/>
<field name="Auxiliary Table Index for Media Compressed Surface" start="341" end="351" type="uint"/>
<field name="Auxiliary Surface Base Address" start="332" end="383" type="address"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="FILTER_COEFFICIENT" length="1">
<field name="Filter Coefficient" start="0" end="7" type="s1.6"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<struct name="SAMPLER_BORDER_COLOR_STATE" length="4">
<field name="Border Color Float Red" start="0" end="31" type="float"/>
<field name="Border Color Float Green" start="32" end="63" type="float"/>
<field name="Border Color Float Blue" start="64" end="95" type="float"/>
<field name="Border Color Float Alpha" start="96" end="127" type="float"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Border Color 32bit Red" start="0" end="31" type="uint"/>
<field name="Border Color 32bit Green" start="32" end="63" type="uint"/>
<field name="Border Color 32bit Blue" start="64" end="95" type="uint"/>
<field name="Border Color 32bit Alpha" start="96" end="127" type="uint"/>
</struct>
<struct name="SAMPLER_STATE" length="4">
<field name="Sampler Disable" start="31" end="31" type="bool"/>
<field name="Texture Border Color Mode" start="29" end="29" type="uint">
<value name="DX10/OGL" value="0"/>
<value name="DX9" value="1"/>
</field>
<field name="LOD PreClamp Mode" start="27" end="28" type="uint" prefix="CLAMP_MODE">
<value name="NONE" value="0"/>
<value name="OGL" value="2"/>
</field>
<field name="Base Mip Level" start="22" end="26" type="u4.1"/>
<field name="Mip Mode Filter" start="20" end="21" type="uint" prefix="MIPFILTER">
<value name="NONE" value="0"/>
<value name="NEAREST" value="1"/>
<value name="LINEAR" value="3"/>
</field>
<field name="Mag Mode Filter" start="17" end="19" type="uint" prefix="MAPFILTER">
<value name="NEAREST" value="0"/>
<value name="LINEAR" value="1"/>
<value name="ANISOTROPIC" value="2"/>
<value name="MONO" value="6"/>
</field>
<field name="Min Mode Filter" start="14" end="16" type="uint" prefix="MAPFILTER">
<value name="NEAREST" value="0"/>
<value name="LINEAR" value="1"/>
<value name="ANISOTROPIC" value="2"/>
<value name="MONO" value="6"/>
</field>
<field name="Texture LOD Bias" start="1" end="13" type="s4.8"/>
<field name="Anisotropic Algorithm" start="0" end="0" type="uint">
<value name="LEGACY" value="0"/>
<value name="EWA Approximation" value="1"/>
</field>
<field name="Min LOD" start="52" end="63" type="u4.8"/>
<field name="Max LOD" start="40" end="51" type="u4.8"/>
<field name="ChromaKey Enable" start="39" end="39" type="bool"/>
<field name="ChromaKey Index" start="37" end="38" type="uint"/>
<field name="ChromaKey Mode" start="36" end="36" type="uint">
<value name="KEYFILTER_KILL_ON_ANY_MATCH" value="0"/>
<value name="KEYFILTER_REPLACE_BLACK" value="1"/>
</field>
<field name="Shadow Function" start="33" end="35" type="uint">
<value name="PREFILTEROP ALWAYS" value="0"/>
<value name="PREFILTEROP NEVER" value="1"/>
<value name="PREFILTEROP LESS" value="2"/>
<value name="PREFILTEROP EQUAL" value="3"/>
<value name="PREFILTEROP LEQUAL" value="4"/>
<value name="PREFILTEROP GREATER" value="5"/>
<value name="PREFILTEROP NOTEQUAL" value="6"/>
<value name="PREFILTEROP GEQUAL" value="7"/>
</field>
<field name="Cube Surface Control Mode" start="32" end="32" type="uint">
<value name="PROGRAMMED" value="0"/>
<value name="OVERRIDE" value="1"/>
</field>
<field name="Border Color Pointer" start="70" end="87" type="offset"/>
<field name="LOD Clamp Magnification Mode" start="64" end="64" type="uint">
<value name="MIPNONE" value="0"/>
<value name="MIPFILTER" value="1"/>
</field>
<field name="Maximum Anisotropy" start="115" end="117" type="uint">
<value name="RATIO 2:1" value="0"/>
<value name="RATIO 4:1" value="1"/>
<value name="RATIO 6:1" value="2"/>
<value name="RATIO 8:1" value="3"/>
<value name="RATIO 10:1" value="4"/>
<value name="RATIO 12:1" value="5"/>
<value name="RATIO 14:1" value="6"/>
<value name="RATIO 16:1" value="7"/>
</field>
<field name="R Address Min Filter Rounding Enable" start="109" end="109" type="bool"/>
<field name="R Address Mag Filter Rounding Enable" start="110" end="110" type="bool"/>
<field name="V Address Min Filter Rounding Enable" start="111" end="111" type="bool"/>
<field name="V Address Mag Filter Rounding Enable" start="112" end="112" type="bool"/>
<field name="U Address Min Filter Rounding Enable" start="113" end="113" type="bool"/>
<field name="U Address Mag Filter Rounding Enable" start="114" end="114" type="bool"/>
<field name="Trilinear Filter Quality" start="107" end="108" type="uint">
<value name="FULL" value="0"/>
<value name="HIGH" value="1"/>
<value name="MED" value="2"/>
<value name="LOW" value="3"/>
</field>
<field name="Non-normalized Coordinate Enable" start="106" end="106" type="bool"/>
intel: genxml: make a couple of enums show up in aubinator In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-06-30 17:25:43 +01:00
<field name="TCX Address Control Mode" start="102" end="104" type="Texture Coordinate Mode"/>
<field name="TCY Address Control Mode" start="99" end="101" type="Texture Coordinate Mode"/>
<field name="TCZ Address Control Mode" start="96" end="98" type="Texture Coordinate Mode"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
</struct>
<struct name="SAMPLER_STATE_8X8_AVS_COEFFICIENTS" length="8">
<field name="Table 0Y Filter Coefficient[n,1]" start="24" end="31" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,1]" start="16" end="23" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,0]" start="8" end="15" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,0]" start="0" end="7" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,3]" start="56" end="63" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,3]" start="48" end="55" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,2]" start="40" end="47" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,2]" start="32" end="39" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,5]" start="88" end="95" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,5]" start="80" end="87" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,4]" start="72" end="79" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,4]" start="64" end="71" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,7]" start="120" end="127" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,7]" start="112" end="119" type="s1.6"/>
<field name="Table 0Y Filter Coefficient[n,6]" start="104" end="111" type="s1.6"/>
<field name="Table 0X Filter Coefficient[n,6]" start="96" end="103" type="s1.6"/>
<field name="Table 1X Filter Coefficient[n,3]" start="152" end="159" type="s1.6"/>
<field name="Table 1X Filter Coefficient[n,2]" start="144" end="151" type="s1.6"/>
<field name="Table 1X Filter Coefficient[n,5]" start="168" end="175" type="s1.6"/>
<field name="Table 1X Filter Coefficient[n,4]" start="160" end="167" type="s1.6"/>
<field name="Table 1Y Filter Coefficient[n,3]" start="216" end="223" type="s1.6"/>
<field name="Table 1Y Filter Coefficient[n,2]" start="208" end="215" type="s1.6"/>
<field name="Table 1Y Filter Coefficient[n,5]" start="232" end="239" type="s1.6"/>
<field name="Table 1Y Filter Coefficient[n,4]" start="224" end="231" type="s1.6"/>
</struct>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
genxml: Add better support for MI_MATH This breaks the guts of MI_MATH (the instruction part) out into its own structure with proper named values. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed by: Iago Toral Quiroga <itoral@igalia.com>
2017-04-19 16:21:08 -07:00
<struct name="MI_MATH_ALU_INSTRUCTION" length="1">
<field name="ALU Opcode" start="20" end="31" type="uint" prefix="MI_ALU">
<value name="NOOP" value="0x000"/>
<value name="LOAD" value="0x080"/>
<value name="LOADINV" value="0x480"/>
<value name="LOAD0" value="0x081"/>
<value name="LOAD1" value="0x481"/>
<value name="ADD" value="0x100"/>
<value name="SUB" value="0x101"/>
<value name="AND" value="0x102"/>
<value name="OR" value="0x103"/>
<value name="XOR" value="0x104"/>
<value name="STORE" value="0x180"/>
<value name="STOREINV" value="0x580"/>
</field>
<field name="Operand 1" start="10" end="19" type="uint" prefix="MI_ALU">
<value name="REG0" value="0x00"/>
<value name="REG1" value="0x01"/>
<value name="REG2" value="0x02"/>
<value name="REG3" value="0x03"/>
<value name="REG4" value="0x04"/>
<value name="REG5" value="0x05"/>
<value name="REG6" value="0x06"/>
<value name="REG7" value="0x07"/>
<value name="REG8" value="0x08"/>
<value name="REG9" value="0x09"/>
<value name="REG10" value="0x0a"/>
<value name="REG11" value="0x0b"/>
<value name="REG12" value="0x0c"/>
<value name="REG13" value="0x0d"/>
<value name="REG14" value="0x0e"/>
<value name="REG15" value="0x0f"/>
<value name="SRCA" value="0x20"/>
<value name="SRCB" value="0x21"/>
<value name="ACCU" value="0x31"/>
<value name="ZF" value="0x32"/>
<value name="CF" value="0x33"/>
</field>
<field name="Operand 2" start="0" end="9" type="uint" prefix="MI_ALU">
<value name="REG0" value="0x00"/>
<value name="REG1" value="0x01"/>
<value name="REG2" value="0x02"/>
<value name="REG3" value="0x03"/>
<value name="REG4" value="0x04"/>
<value name="REG5" value="0x05"/>
<value name="REG6" value="0x06"/>
<value name="REG7" value="0x07"/>
<value name="REG8" value="0x08"/>
<value name="REG9" value="0x09"/>
<value name="REG10" value="0x0a"/>
<value name="REG11" value="0x0b"/>
<value name="REG12" value="0x0c"/>
<value name="REG13" value="0x0d"/>
<value name="REG14" value="0x0e"/>
<value name="REG15" value="0x0f"/>
<value name="SRCA" value="0x20"/>
<value name="SRCB" value="0x21"/>
<value name="ACCU" value="0x31"/>
<value name="ZF" value="0x32"/>
<value name="CF" value="0x33"/>
</field>
</struct>
intel/genxml: Media instructions and structures for gen8 v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com> - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:54:25 +02:00
<struct name="INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT" length="3">
<field name="Concealment Method" start="31" end="31" type="uint"/>
<field name="Init Current MB Number" start="30" end="30" type="bool"/>
<field name="Intra PredMode (4x4/8x8 Luma) Error Control" start="29" end="29" type="bool"/>
<field name="MB Error Concealment B Temporal Prediction Mode" start="27" end="28" type="uint"/>
<field name="MB Error Concealment B Temporal Motion Vectors Override Enable" start="25" end="25" type="bool"/>
<field name="MB Error Concealment B Temporal Weight Prediction Disable" start="24" end="24" type="bool"/>
<field name="Concealment Picture ID" start="16" end="21" type="uint"/>
<field name="BSD Premature Complete Error Handling" start="14" end="14" type="bool"/>
<field name="MPR Error Handling" start="12" end="12" type="bool"/>
<field name="Entropy Error Handling" start="10" end="10" type="bool"/>
<field name="MB Header Error Handling" start="8" end="8" type="bool"/>
<field name="MB Error Concealment B Spatial Prediction Mode" start="6" end="7" type="uint"/>
<field name="MB Error Concealment B Spatial Motion Vectors Override Disable" start="4" end="4" type="bool"/>
<field name="MB Error Concealment B Spatial Weight Prediction Disable" start="3" end="3" type="bool"/>
<field name="MB Error Concealment P Slice Motion Vectors Override Disable" start="1" end="1" type="bool"/>
<field name="MB Error Concealment P Slice Weight Prediction Disable" start="0" end="0" type="bool"/>
<field name="First MB Byte Offset of Slice Data or Slice Header" start="48" end="63" type="uint"/>
<field name="Fix Prev MB Skipped" start="39" end="39" type="bool"/>
<field name="Emulation Prevention Byte Present" start="36" end="36" type="bool"/>
<field name="Last Slice" start="35" end="35" type="bool"/>
<field name="First MB Bit Offset" start="32" end="34" type="uint"/>
<field name="I Slice Concealment Mode" start="95" end="95" type="uint">
<value name="Intra Concealment" value="1"/>
<value name="Inter Concealment" value="0"/>
</field>
<field name="Concealment Reference Picture + Field Bit" start="88" end="93" type="uint"/>
<field name="P Slice Concealment Mode" start="87" end="87" type="uint">
<value name="Intra Concealment" value="1"/>
<value name="Inter Concealment" value="0"/>
</field>
<field name="P Slice Inter Concealment Mode" start="80" end="82" type="uint"/>
<field name="B Slice Concealment Mode" start="79" end="79" type="uint">
<value name="Intra Concealment" value="1"/>
<value name="Inter Concealment" value="0"/>
</field>
<field name="B Slice Inter Direct Type Concealment Mode" start="76" end="77" type="uint"/>
<field name="B Slice Spatial Inter Concealment Mode" start="72" end="74" type="uint"/>
<field name="B Slice Temporal Inter Concealment Mode" start="68" end="70" type="uint"/>
<field name="Intra 8x8/4x4 Prediction Error Concealment Control" start="65" end="65" type="bool"/>
<field name="Intra Prediction Error Control" start="64" end="64" type="bool"/>
</struct>
<struct name="MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION" length="2">
<field name="Slice Horizontal Position" start="24" end="31" type="uint"/>
<field name="Slice Vertical Position" start="16" end="23" type="uint"/>
<field name="MB Count" start="8" end="15" type="uint"/>
<field name="Slice Concealment Override" start="7" end="7" type="uint"/>
<field name="Slice Concealment Type" start="6" end="6" type="uint"/>
<field name="Last Pic Slice" start="5" end="5" type="bool"/>
<field name="Last MB" start="3" end="3" type="bool"/>
<field name="First MB Bit Offset" start="0" end="2" type="uint"/>
<field name="Quantizer Scale Code" start="56" end="60" type="uint"/>
<field name="Next Slice Vertical Position" start="40" end="48" type="uint"/>
<field name="Next Slice Horizontal Position" start="32" end="39" type="uint"/>
</struct>
<struct name="MEMORYADDRESSATTRIBUTES" length="1">
<field name="Arbitration Priority Control" start="7" end="8" type="uint"/>
<field name="Target Cache" start="3" end="4" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Age for QUADLRU" start="0" end="1" type="uint"/>
</struct>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DPRIMITIVE" bias="2" length="7" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="Indirect Parameter Enable" start="10" end="10" type="bool"/>
<field name="UAV Coherency Required" start="9" end="9" type="bool"/>
<field name="Predicate Enable" start="8" end="8" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="5"/>
<field name="End Offset Enable" start="41" end="41" type="bool"/>
<field name="Vertex Access Type" start="40" end="40" type="uint">
<value name="SEQUENTIAL" value="0"/>
<value name="RANDOM" value="1"/>
</field>
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:44:22 -08:00
<field name="Primitive Topology Type" start="32" end="37" type="3D_Prim_Topo_Type"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vertex Count Per Instance" start="64" end="95" type="uint"/>
<field name="Start Vertex Location" start="96" end="127" type="uint"/>
<field name="Instance Count" start="128" end="159" type="uint"/>
<field name="Start Instance Location" start="160" end="191" type="uint"/>
<field name="Base Vertex Location" start="192" end="223" type="int"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="10"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="AA Point Coverage Bias" start="56" end="63" type="u0.8"/>
<field name="AA Coverage Bias" start="48" end="55" type="u0.8"/>
<field name="AA Point Coverage Slope" start="40" end="47" type="u0.8"/>
<field name="AA Coverage Slope" start="32" end="39" type="u0.8"/>
<field name="AA Point Coverage EndCap Bias" start="88" end="95" type="u0.8"/>
<field name="AA Coverage EndCap Bias" start="80" end="87" type="u0.8"/>
<field name="AA Point Coverage EndCap Slope" start="72" end="79" type="u0.8"/>
<field name="AA Coverage EndCap Slope" start="64" end="71" type="u0.8"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_EDIT_DS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="70"/>
<field name="DWord Length" start="0" end="8" type="uint" default="0"/>
<field name="Binding Table Block Clear" start="48" end="63" type="uint"/>
<field name="Binding Table Edit Target" start="32" end="33" type="uint">
<value name="All Cores" value="3"/>
<value name="Core 1" value="2"/>
<value name="Core 0" value="1"/>
</field>
<group count="0" start="64" size="32">
<field name="Entry [n]" start="0" end="31" type="BINDING_TABLE_EDIT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_EDIT_GS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="68"/>
<field name="DWord Length" start="0" end="8" type="uint" default="0"/>
<field name="Binding Table Block Clear" start="48" end="63" type="uint"/>
<field name="Binding Table Edit Target" start="32" end="33" type="uint">
<value name="All Cores" value="3"/>
<value name="Core 1" value="2"/>
<value name="Core 0" value="1"/>
</field>
<group count="0" start="64" size="32">
<field name="Entry [n]" start="0" end="31" type="BINDING_TABLE_EDIT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_EDIT_HS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="69"/>
<field name="DWord Length" start="0" end="8" type="uint" default="0"/>
<field name="Binding Table Block Clear" start="48" end="63" type="uint"/>
<field name="Binding Table Edit Target" start="32" end="33" type="uint">
<value name="All Cores" value="3"/>
<value name="Core 1" value="2"/>
<value name="Core 0" value="1"/>
</field>
<group count="0" start="64" size="32">
<field name="Entry [n]" start="0" end="31" type="BINDING_TABLE_EDIT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_EDIT_PS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="71"/>
<field name="DWord Length" start="0" end="8" type="uint" default="0"/>
<field name="Binding Table Block Clear" start="48" end="63" type="uint"/>
<field name="Binding Table Edit Target" start="32" end="33" type="uint">
<value name="All Cores" value="3"/>
<value name="Core 1" value="2"/>
<value name="Core 0" value="1"/>
</field>
<group count="0" start="64" size="32">
<field name="Entry [n]" start="0" end="31" type="BINDING_TABLE_EDIT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_EDIT_VS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="67"/>
<field name="DWord Length" start="0" end="8" type="uint" default="0"/>
<field name="Binding Table Block Clear" start="48" end="63" type="uint"/>
<field name="Binding Table Edit Target" start="32" end="33" type="uint">
<value name="All Cores" value="3"/>
<value name="Core 1" value="2"/>
<value name="Core 0" value="1"/>
</field>
<group count="0" start="64" size="32">
<field name="Entry [n]" start="0" end="31" type="BINDING_TABLE_EDIT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS_DS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="40"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to DS Binding Table" start="37" end="47" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS_GS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="41"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to GS Binding Table" start="37" end="47" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS_HS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="39"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to HS Binding Table" start="37" end="47" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS_PS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to PS Binding Table" start="37" end="47" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS_VS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="38"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to VS Binding Table" start="37" end="47" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POOL_ALLOC" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="25"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Binding Table Pool Base Address" start="44" end="95" type="address"/>
<field name="Binding Table Pool Enable" start="43" end="43" type="uint"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="32" end="38" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Binding Table Pool Buffer Size" start="108" end="127" type="uint">
<value name="No Valid Data" value="0"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_BLEND_STATE_POINTERS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="36"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Blend State Pointer" start="38" end="63" type="offset"/>
<field name="Blend State Pointer Valid" start="32" end="32" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CC_STATE_POINTERS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="14"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Color Calc State Pointer" start="38" end="63" type="offset"/>
<field name="Color Calc State Pointer Valid" start="32" end="32" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CHROMA_KEY" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="ChromaKey Table Index" start="62" end="63" type="uint"/>
<field name="ChromaKey Low Value" start="64" end="95" type="uint"/>
<field name="ChromaKey High Value" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CLEAR_PARAMS" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Depth Clear Value" start="32" end="63" type="float"/>
<field name="Depth Clear Value Valid" start="64" end="64" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CLIP" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="18"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Force User Clip Distance Cull Test Enable Bitmask" start="52" end="52" type="bool"/>
<field name="Vertex Sub Pixel Precision Select" start="51" end="51" type="uint">
<value name="8 Bit" value="0"/>
<value name="4 Bit" value="1"/>
</field>
<field name="Early Cull Enable" start="50" end="50" type="bool"/>
<field name="Force User Clip Distance Clip Test Enable Bitmask" start="49" end="49" type="bool"/>
<field name="Force Clip Mode" start="48" end="48" type="bool"/>
genxml: s/Clipper Statistics Enable/Statistics Enable/ It's in 3DSTATE_CLIP, so it doesn't really need the extra detail. This matches what we do for VS, FS, etc. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-16 12:31:42 -07:00
<field name="Statistics Enable" start="42" end="42" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="User Clip Distance Cull Test Enable Bitmask" start="32" end="39" type="uint"/>
<field name="Clip Enable" start="95" end="95" type="bool"/>
<field name="API Mode" start="94" end="94" type="uint">
genxml: Add APIMODE_D3D missing enum values and improve consistency. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-18 13:56:23 -07:00
<value name="APIMODE_OGL" value="0"/>
<value name="APIMODE_D3D" value="1"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
<field name="Viewport XY Clip Test Enable" start="92" end="92" type="bool"/>
<field name="Guardband Clip Test Enable" start="90" end="90" type="bool"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="80" end="87" type="uint"/>
<field name="Clip Mode" start="77" end="79" type="uint">
genxml: Add CLIPMODE_* prefix to 3DSTATE_CLIP's "Clip Mode" enum values. Gen6-7.5 use CLIPMODE_REJECT_ALL, while Gen8+ just used REJECT_ALL. Being consistent will let me unify code, and I prefer having the prefix. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-18 15:36:43 -07:00
<value name="CLIPMODE_NORMAL" value="0"/>
<value name="CLIPMODE_REJECT_ALL" value="3"/>
<value name="CLIPMODE_ACCEPT_ALL" value="4"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
<field name="Perspective Divide Disable" start="73" end="73" type="bool"/>
<field name="Non-Perspective Barycentric Enable" start="72" end="72" type="bool"/>
<field name="Triangle Strip/List Provoking Vertex Select" start="68" end="69" type="uint"/>
<field name="Line Strip/List Provoking Vertex Select" start="66" end="67" type="uint"/>
<field name="Triangle Fan Provoking Vertex Select" start="64" end="65" type="uint"/>
<field name="Minimum Point Width" start="113" end="123" type="u8.3"/>
<field name="Maximum Point Width" start="102" end="112" type="u8.3"/>
<field name="Force Zero RTA Index Enable" start="101" end="101" type="bool"/>
<field name="Maximum VP Index" start="96" end="99" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CONSTANT_DS" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="26"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="14" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<field name="Constant Body" start="32" end="351" type="3DSTATE_CONSTANT_BODY"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CONSTANT_GS" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="22"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="14" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<field name="Constant Body" start="32" end="351" type="3DSTATE_CONSTANT_BODY"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CONSTANT_HS" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="25"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="14" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<field name="Constant Body" start="32" end="351" type="3DSTATE_CONSTANT_BODY"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CONSTANT_PS" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="23"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="14" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<field name="Constant Body" start="32" end="351" type="3DSTATE_CONSTANT_BODY"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_CONSTANT_VS" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="21"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="14" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<field name="Constant Body" start="32" end="351" type="3DSTATE_CONSTANT_BODY"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_DEPTH_BUFFER" bias="2" length="8" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="5"/>
<field name="DWord Length" start="0" end="7" type="uint" default="6"/>
<field name="Surface Type" start="61" end="63" type="uint">
<value name="SURFTYPE_1D" value="0"/>
<value name="SURFTYPE_2D" value="1"/>
<value name="SURFTYPE_3D" value="2"/>
<value name="SURFTYPE_CUBE" value="3"/>
<value name="SURFTYPE_NULL" value="7"/>
</field>
<field name="Depth Write Enable" start="60" end="60" type="bool"/>
<field name="Stencil Write Enable" start="59" end="59" type="bool"/>
<field name="Hierarchical Depth Buffer Enable" start="54" end="54" type="bool"/>
<field name="Surface Format" start="50" end="52" type="uint">
<value name="D32_FLOAT" value="1"/>
<value name="D24_UNORM_X8_UINT" value="3"/>
<value name="D16_UNORM" value="5"/>
</field>
<field name="Surface Pitch" start="32" end="49" type="uint"/>
<field name="Surface Base Address" start="64" end="127" type="address"/>
<field name="Height" start="146" end="159" type="uint"/>
<field name="Width" start="132" end="145" type="uint"/>
<field name="LOD" start="128" end="131" type="uint"/>
<field name="Depth" start="181" end="191" type="uint"/>
<field name="Minimum Array Element" start="170" end="180" type="uint"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="160" end="166" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Render Target View Extent" start="245" end="255" type="uint"/>
<field name="Surface QPitch" start="224" end="238" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_DRAWING_RECTANGLE" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="Core Mode Select" start="14" end="15" type="uint">
<value name="Legacy" value="0"/>
<value name="Core 0 Enabled" value="1"/>
<value name="Core 1 Enabled" value="2"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Clipped Drawing Rectangle Y Min" start="48" end="63" type="uint"/>
<field name="Clipped Drawing Rectangle X Min" start="32" end="47" type="uint"/>
<field name="Clipped Drawing Rectangle Y Max" start="80" end="95" type="uint"/>
<field name="Clipped Drawing Rectangle X Max" start="64" end="79" type="uint"/>
<field name="Drawing Rectangle Origin Y" start="112" end="127" type="int"/>
<field name="Drawing Rectangle Origin X" start="96" end="111" type="int"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_DS" bias="2" length="9" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="29"/>
<field name="DWord Length" start="0" end="7" type="uint" default="7"/>
<field name="Kernel Start Pointer" start="38" end="95" type="offset"/>
<field name="Single Domain Point Dispatch" start="127" end="127" type="uint"/>
<field name="Vector Mask Enable" start="126" end="126" type="bool"/>
<field name="Sampler Count" start="123" end="125" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="114" end="121" type="uint"/>
<field name="Thread Dispatch Priority" start="113" end="113" type="uint">
<value name="High" value="1"/>
</field>
<field name="Floating Point Mode" start="112" end="112" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Accesses UAV" start="110" end="110" type="bool"/>
<field name="Illegal Opcode Exception Enable" start="109" end="109" type="bool"/>
<field name="Software Exception Enable" start="103" end="103" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="138" end="191" type="address"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Per-Thread Scratch Space" start="128" end="131" type="uint"/>
<field name="Dispatch GRF Start Register For URB Data" start="212" end="216" type="uint"/>
<field name="Patch URB Entry Read Length" start="203" end="209" type="uint"/>
<field name="Patch URB Entry Read Offset" start="196" end="201" type="uint"/>
<field name="Maximum Number of Threads" start="245" end="253" type="uint"/>
<field name="Statistics Enable" start="234" end="234" type="bool"/>
genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+. This will let us avoid ifdefs. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-21 00:11:57 -08:00
<field name="Dispatch Mode" start="227" end="227" type="uint" prefix="DISPATCH_MODE">
<value name="SIMD4X2" value="0"/>
<value name="SIMD8_SINGLE_PATCH" value="1"/>
</field>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Compute W Coordinate Enable" start="226" end="226" type="bool"/>
<field name="Cache Disable" start="225" end="225" type="bool"/>
genxml: Rename "Function Enable" to "Enable". Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:30:49 -07:00
<field name="Enable" start="224" end="224" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vertex URB Entry Output Read Offset" start="277" end="282" type="uint"/>
<field name="Vertex URB Entry Output Length" start="272" end="276" type="uint"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="264" end="271" type="uint"/>
<field name="User Clip Distance Cull Test Enable Bitmask" start="256" end="263" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_CONSTANT_DS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="55"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Constant Buffer Valid" start="48" end="63" type="uint"/>
<field name="Constant Buffer Binding Table Block" start="44" end="47" type="uint"/>
<field name="Gather Buffer Offset" start="70" end="86" type="offset"/>
<field name="Constant Buffer Dx9 Generate Stall" start="69" end="69" type="bool"/>
<group count="0" start="96" size="32">
<field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
<field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_CONSTANT_GS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="53"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Constant Buffer Valid" start="48" end="63" type="uint"/>
<field name="Constant Buffer Binding Table Block" start="44" end="47" type="uint"/>
<field name="Gather Buffer Offset" start="70" end="86" type="offset"/>
<field name="Constant Buffer Dx9 Generate Stall" start="69" end="69" type="bool"/>
<group count="0" start="96" size="32">
<field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
<field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_CONSTANT_HS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="54"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Constant Buffer Valid" start="48" end="63" type="uint"/>
<field name="Constant Buffer Binding Table Block" start="44" end="47" type="uint"/>
<field name="Gather Buffer Offset" start="70" end="86" type="offset"/>
<field name="Constant Buffer Dx9 Generate Stall" start="69" end="69" type="bool"/>
<group count="0" start="96" size="32">
<field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
<field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_CONSTANT_PS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="56"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Constant Buffer Valid" start="48" end="63" type="uint"/>
<field name="Constant Buffer Binding Table Block" start="44" end="47" type="uint"/>
<field name="Gather Buffer Offset" start="70" end="86" type="offset"/>
<field name="Constant Buffer Dx9 Generate Stall" start="69" end="69" type="bool"/>
<field name="Constant Buffer Dx9 Enable" start="68" end="68" type="bool"/>
<group count="0" start="96" size="32">
<field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
<field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_CONSTANT_VS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="52"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Valid" start="48" end="63" type="uint"/>
<field name="Constant Buffer Binding Table Block" start="44" end="47" type="uint"/>
<field name="Gather Buffer Offset" start="70" end="86" type="offset"/>
<field name="Constant Buffer Dx9 Generate Stall" start="69" end="69" type="bool"/>
<field name="Constant Buffer Dx9 Enable" start="68" end="68" type="bool"/>
<group count="0" start="96" size="32">
<field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/>
<field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GATHER_POOL_ALLOC" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="26"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Gather Pool Base Address" start="44" end="95" type="address"/>
<field name="Gather Pool Enable" start="43" end="43" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="32" end="38" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Gather Pool Buffer Size" start="108" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_GS" bias="2" length="10" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="17"/>
<field name="DWord Length" start="0" end="7" type="uint" default="8"/>
<field name="Kernel Start Pointer" start="38" end="95" type="offset"/>
intel/genxml: Make "Single Program Flow" a boolean We also get rid of the "(SPF)" a few places. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:23:16 -07:00
<field name="Single Program Flow" start="127" end="127" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vector Mask Enable" start="126" end="126" type="bool"/>
<field name="Sampler Count" start="123" end="125" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="114" end="121" type="uint"/>
<field name="Thread Dispatch Priority" start="113" end="113" type="uint">
<value name="High" value="1"/>
</field>
<field name="Floating Point Mode" start="112" end="112" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="109" end="109" type="bool"/>
<field name="Accesses UAV" start="108" end="108" type="bool"/>
<field name="Mask Stack Exception Enable" start="107" end="107" type="bool"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Software Exception Enable" start="103" end="103" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Expected Vertex Count" start="96" end="101" type="uint"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="138" end="191" type="address"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Per-Thread Scratch Space" start="128" end="131" type="uint"/>
<field name="Output Vertex Size" start="215" end="220" type="uint"/>
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:44:22 -08:00
<field name="Output Topology" start="209" end="214" type="3D_Prim_Topo_Type"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vertex URB Entry Read Length" start="203" end="208" type="uint"/>
intel/genxml: Make "Include Vertex Handles" and "Include Primitive ID" booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:31:48 -07:00
<field name="Include Vertex Handles" start="202" end="202" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vertex URB Entry Read Offset" start="196" end="201" type="uint"/>
<field name="Dispatch GRF Start Register For URB Data" start="192" end="195" type="uint"/>
<field name="Maximum Number of Threads" start="248" end="255" type="uint"/>
<field name="Control Data Header Size" start="244" end="247" type="uint"/>
<field name="Instance Control" start="239" end="243" type="uint"/>
<field name="Default Stream Id" start="237" end="238" type="uint"/>
<field name="Dispatch Mode" start="235" end="236" type="uint" prefix="DISPATCH_MODE">
<value name="Dual Instance" value="1"/>
<value name="Dual Object" value="2"/>
<value name="SIMD8" value="3"/>
</field>
<field name="Statistics Enable" start="234" end="234" type="bool"/>
<field name="Invocations Increment Value" start="229" end="233" type="uint"/>
intel/genxml: Make "Include Vertex Handles" and "Include Primitive ID" booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:31:48 -07:00
<field name="Include Primitive ID" start="228" end="228" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Hint" start="227" end="227" type="uint"/>
<field name="Reorder Mode" start="226" end="226" type="uint">
<value name="LEADING" value="0"/>
<value name="TRAILING" value="1"/>
</field>
<field name="Discard Adjacency" start="225" end="225" type="bool"/>
genxml: Rename "Function Enable" to "Enable". Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:30:49 -07:00
<field name="Enable" start="224" end="224" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Control Data Format" start="287" end="287" type="uint">
<value name="CUT" value="0"/>
<value name="SID" value="1"/>
</field>
<field name="Static Output" start="286" end="286" type="bool"/>
<field name="Static Output Vertex Count" start="272" end="282" type="uint"/>
<field name="Vertex URB Entry Output Read Offset" start="309" end="314" type="uint"/>
<field name="Vertex URB Entry Output Length" start="304" end="308" type="uint"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="296" end="303" type="uint"/>
<field name="User Clip Distance Cull Test Enable Bitmask" start="288" end="295" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_HIER_DEPTH_BUFFER" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="7"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="57" end="63" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Surface Base Address" start="64" end="127" type="address"/>
<field name="Surface QPitch" start="128" end="142" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_HS" bias="2" length="9" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="27"/>
<field name="DWord Length" start="0" end="7" type="uint" default="7"/>
<field name="Sampler Count" start="59" end="61" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="50" end="57" type="uint"/>
<field name="Thread Dispatch Priority" start="49" end="49" type="uint">
<value name="High" value="1"/>
</field>
<field name="Floating Point Mode" start="48" end="48" type="uint">
<value name="IEEE-754" value="0"/>
<value name="alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="45" end="45" type="bool"/>
<field name="Software Exception Enable" start="44" end="44" type="bool"/>
genxml: Rename "Function Enable" to "Enable". Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:30:49 -07:00
<field name="Enable" start="95" end="95" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Statistics Enable" start="93" end="93" type="bool"/>
<field name="Maximum Number of Threads" start="72" end="80" type="uint"/>
<field name="Instance Count" start="64" end="67" type="uint"/>
<field name="Kernel Start Pointer" start="102" end="159" type="offset"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="170" end="223" type="address"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Per-Thread Scratch Space" start="160" end="163" type="uint"/>
<field name="Single Program Flow" start="251" end="251" type="bool"/>
<field name="Vector Mask Enable" start="250" end="250" type="bool"/>
<field name="Accesses UAV" start="249" end="249" type="bool"/>
intel/genxml: Make "Include Vertex Handles" and "Include Primitive ID" booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:31:48 -07:00
<field name="Include Vertex Handles" start="248" end="248" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Dispatch GRF Start Register For URB Data" start="243" end="247" type="uint"/>
<field name="Vertex URB Entry Read Length" start="235" end="240" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="228" end="233" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_INDEX_BUFFER" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="10"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<field name="Index Format" start="40" end="41" type="uint" prefix="INDEX">
<value name="BYTE" value="0"/>
<value name="WORD" value="1"/>
<value name="DWORD" value="2"/>
</field>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="32" end="38" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Buffer Starting Address" start="64" end="127" type="address"/>
<field name="Buffer Size" start="128" end="159" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_LINE_STIPPLE" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="8"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Modify Enable (Current Repeat Counter, Current Stipple Index)" start="63" end="63" type="bool"/>
<field name="Current Repeat Counter" start="53" end="61" type="uint"/>
<field name="Current Stipple Index" start="48" end="51" type="uint"/>
<field name="Line Stipple Pattern" start="32" end="47" type="uint"/>
<field name="Line Stipple Inverse Repeat Count" start="79" end="95" type="u1.16"/>
<field name="Line Stipple Repeat Count" start="64" end="72" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_MONOFILTER_SIZE" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="17"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Monochrome Filter Width" start="35" end="37" type="uint"/>
<field name="Monochrome Filter Height" start="32" end="34" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_MULTISAMPLE" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="13"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pixel Position Offset Enable" start="37" end="37" type="bool"/>
<field name="Pixel Location" start="36" end="36" type="uint">
<value name="CENTER" value="0"/>
<value name="UL_CORNER" value="1"/>
</field>
<field name="Number of Multisamples" start="33" end="35" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_POLY_STIPPLE_OFFSET" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="6"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Polygon Stipple X Offset" start="40" end="44" type="uint"/>
<field name="Polygon Stipple Y Offset" start="32" end="36" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_POLY_STIPPLE_PATTERN" bias="2" length="33" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="7"/>
<field name="DWord Length" start="0" end="7" type="uint" default="31"/>
<group count="32" start="32" size="32">
<field name="Pattern Row" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PS" bias="2" length="12" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="32"/>
<field name="DWord Length" start="0" end="7" type="uint" default="10"/>
<field name="Kernel Start Pointer 0" start="38" end="95" type="offset"/>
intel/genxml: Make "Single Program Flow" a boolean We also get rid of the "(SPF)" a few places. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:23:16 -07:00
<field name="Single Program Flow" start="127" end="127" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vector Mask Enable" start="126" end="126" type="bool"/>
<field name="Sampler Count" start="123" end="125" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Single Precision Denormal Mode" start="122" end="122" type="uint">
<value name="Flushed to Zero" value="0"/>
<value name="Retained" value="1"/>
</field>
<field name="Binding Table Entry Count" start="114" end="121" type="uint"/>
<field name="Thread Dispatch Priority" start="113" end="113" type="uint">
<value name="High" value="1"/>
</field>
<field name="Floating Point Mode" start="112" end="112" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Rounding Mode" start="110" end="111" type="uint">
<value name="RTNE" value="0"/>
<value name="RU" value="1"/>
<value name="RD" value="2"/>
<value name="RTZ" value="3"/>
</field>
<field name="Illegal Opcode Exception Enable" start="109" end="109" type="bool"/>
<field name="Mask Stack Exception Enable" start="107" end="107" type="bool"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Software Exception Enable" start="103" end="103" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="138" end="191" type="address"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Per Thread Scratch Space" start="128" end="131" type="uint"/>
<field name="Maximum Number of Threads Per PSD" start="215" end="223" type="uint"/>
<field name="Push Constant Enable" start="203" end="203" type="bool"/>
<field name="Render Target Fast Clear Enable" start="200" end="200" type="bool"/>
<field name="Render Target Resolve Enable" start="198" end="198" type="bool"/>
<field name="Position XY Offset Select" start="195" end="196" type="uint">
<value name="POSOFFSET_NONE" value="0"/>
<value name="POSOFFSET_CENTROID" value="2"/>
<value name="POSOFFSET_SAMPLE" value="3"/>
</field>
<field name="32 Pixel Dispatch Enable" start="194" end="194" type="bool"/>
<field name="16 Pixel Dispatch Enable" start="193" end="193" type="bool"/>
<field name="8 Pixel Dispatch Enable" start="192" end="192" type="bool"/>
<field name="Dispatch GRF Start Register For Constant/Setup Data 0" start="240" end="246" type="uint"/>
<field name="Dispatch GRF Start Register For Constant/Setup Data 1" start="232" end="238" type="uint"/>
<field name="Dispatch GRF Start Register For Constant/Setup Data 2" start="224" end="230" type="uint"/>
<field name="Kernel Start Pointer 1" start="262" end="319" type="offset"/>
<field name="Kernel Start Pointer 2" start="326" end="383" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PS_BLEND" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="77"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Alpha To Coverage Enable" start="63" end="63" type="bool"/>
<field name="Has Writeable RT" start="62" end="62" type="bool"/>
<field name="Color Buffer Blend Enable" start="61" end="61" type="bool"/>
<field name="Source Alpha Blend Factor" start="56" end="60" type="uint"/>
<field name="Destination Alpha Blend Factor" start="51" end="55" type="uint"/>
<field name="Source Blend Factor" start="46" end="50" type="uint"/>
<field name="Destination Blend Factor" start="41" end="45" type="uint"/>
<field name="Alpha Test Enable" start="40" end="40" type="bool"/>
<field name="Independent Alpha Blend Enable" start="39" end="39" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PS_EXTRA" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="79"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pixel Shader Valid" start="63" end="63" type="bool"/>
<field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool"/>
<field name="oMask Present to Render Target" start="61" end="61" type="bool"/>
<field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool"/>
<field name="Pixel Shader Computed Depth Mode" start="58" end="59" type="uint">
<value name="PSCDEPTH_OFF" value="0"/>
<value name="PSCDEPTH_ON" value="1"/>
<value name="PSCDEPTH_ON_GE" value="2"/>
<value name="PSCDEPTH_ON_LE" value="3"/>
</field>
<field name="Force Computed Depth" start="57" end="57" type="bool"/>
<field name="Pixel Shader Uses Source Depth" start="56" end="56" type="bool"/>
<field name="Pixel Shader Uses Source W" start="55" end="55" type="bool"/>
<field name="Attribute Enable" start="40" end="40" type="bool"/>
<field name="Pixel Shader Disables Alpha To Coverage" start="39" end="39" type="bool"/>
<field name="Pixel Shader Is Per Sample" start="38" end="38" type="bool"/>
<field name="Pixel Shader Has UAV" start="34" end="34" type="bool"/>
<field name="Pixel Shader Uses Input Coverage Mask" start="33" end="33" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="20"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Offset" start="48" end="52" type="uint"/>
<field name="Constant Buffer Size" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_GS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="21"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Offset" start="48" end="52" type="uint"/>
<field name="Constant Buffer Size" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_HS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="19"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Offset" start="48" end="52" type="uint"/>
<field name="Constant Buffer Size" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_PS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="22"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Offset" start="48" end="52" type="uint"/>
<field name="Constant Buffer Size" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_VS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="18"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Constant Buffer Offset" start="48" end="52" type="uint"/>
<field name="Constant Buffer Size" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_RASTER" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="80"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<field name="API Mode" start="54" end="55" type="uint">
<value name="DX9/OGL" value="0"/>
<value name="DX10.0" value="1"/>
<value name="DX10.1+" value="2"/>
</field>
<field name="Front Winding" start="53" end="53" type="uint">
<value name="Clockwise" value="0"/>
<value name="Counter Clockwise" value="1"/>
</field>
<field name="Forced Sample Count" start="50" end="52" type="uint" prefix="FSC">
<value name="NUMRASTSAMPLES_0" value="0"/>
<value name="NUMRASTSAMPLES_1" value="1"/>
<value name="NUMRASTSAMPLES_2" value="2"/>
<value name="NUMRASTSAMPLES_4" value="3"/>
<value name="NUMRASTSAMPLES_8" value="4"/>
<value name="NUMRASTSAMPLES_16" value="5"/>
</field>
<field name="Cull Mode" start="48" end="49" type="uint" prefix="CULLMODE">
<value name="BOTH" value="0"/>
<value name="NONE" value="1"/>
<value name="FRONT" value="2"/>
<value name="BACK" value="3"/>
</field>
<field name="Force Multisampling" start="46" end="46" type="uint"/>
<field name="Smooth Point Enable" start="45" end="45" type="bool"/>
<field name="DX Multisample Rasterization Enable" start="44" end="44" type="bool"/>
<field name="DX Multisample Rasterization Mode" start="42" end="43" type="uint">
<value name="MSRASTMODE_ OFF_PIXEL" value="0"/>
<value name="MSRASTMODE_ OFF_PATTERN" value="1"/>
<value name="MSRASTMODE_ ON_PIXEL" value="2"/>
<value name="MSRASTMODE_ ON_PATTERN" value="3"/>
</field>
<field name="Global Depth Offset Enable Solid" start="41" end="41" type="bool"/>
<field name="Global Depth Offset Enable Wireframe" start="40" end="40" type="bool"/>
<field name="Global Depth Offset Enable Point" start="39" end="39" type="bool"/>
<field name="Front Face Fill Mode" start="37" end="38" type="uint" prefix="FILL_MODE">
<value name="SOLID" value="0"/>
<value name="WIREFRAME" value="1"/>
<value name="POINT" value="2"/>
</field>
<field name="Back Face Fill Mode" start="35" end="36" type="uint" prefix="FILL_MODE">
<value name="SOLID" value="0"/>
<value name="WIREFRAME" value="1"/>
<value name="POINT" value="2"/>
</field>
<field name="Antialiasing Enable" start="34" end="34" type="bool"/>
<field name="Scissor Rectangle Enable" start="33" end="33" type="bool"/>
<field name="Viewport Z Clip Test Enable" start="32" end="32" type="bool"/>
<field name="Global Depth Offset Constant" start="64" end="95" type="float"/>
<field name="Global Depth Offset Scale" start="96" end="127" type="float"/>
<field name="Global Depth Offset Clamp" start="128" end="159" type="float"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_PALETTE_LOAD0" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="7" type="uint"/>
<group count="0" start="32" size="32">
<field name="Entry" start="0" end="31" type="PALETTE_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_PALETTE_LOAD1" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="12"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<group count="0" start="32" size="32">
<field name="Palette Alpha[0:N-1]" start="24" end="31" type="uint"/>
<field name="Palette Red[0:N-1]" start="16" end="23" type="uint"/>
<field name="Palette Green[0:N-1]" start="8" end="15" type="uint"/>
<field name="Palette Blue[0:N-1]" start="0" end="7" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS_DS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="45"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to DS Sampler State" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS_GS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="46"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to GS Sampler State" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS_HS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="44"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to HS Sampler State" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS_PS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="47"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to PS Sampler State" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS_VS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="43"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Pointer to VS Sampler State" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLE_MASK" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="24"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Sample Mask" start="32" end="47" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SAMPLE_PATTERN" bias="2" length="9" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="28"/>
<field name="DWord Length" start="0" end="7" type="uint" default="7"/>
<field name="8x Sample7 X Offset" start="188" end="191" type="u0.4"/>
<field name="8x Sample7 Y Offset" start="184" end="187" type="u0.4"/>
<field name="8x Sample6 X Offset" start="180" end="183" type="u0.4"/>
<field name="8x Sample6 Y Offset" start="176" end="179" type="u0.4"/>
<field name="8x Sample5 X Offset" start="172" end="175" type="u0.4"/>
<field name="8x Sample5 Y Offset" start="168" end="171" type="u0.4"/>
<field name="8x Sample4 X Offset" start="164" end="167" type="u0.4"/>
<field name="8x Sample4 Y Offset" start="160" end="163" type="u0.4"/>
<field name="8x Sample3 X Offset" start="220" end="223" type="u0.4"/>
<field name="8x Sample3 Y Offset" start="216" end="219" type="u0.4"/>
<field name="8x Sample2 X Offset" start="212" end="215" type="u0.4"/>
<field name="8x Sample2 Y Offset" start="208" end="211" type="u0.4"/>
<field name="8x Sample1 X Offset" start="204" end="207" type="u0.4"/>
<field name="8x Sample1 Y Offset" start="200" end="203" type="u0.4"/>
<field name="8x Sample0 X Offset" start="196" end="199" type="u0.4"/>
<field name="8x Sample0 Y Offset" start="192" end="195" type="u0.4"/>
<field name="4x Sample3 X Offset" start="252" end="255" type="u0.4"/>
<field name="4x Sample3 Y Offset" start="248" end="251" type="u0.4"/>
<field name="4x Sample2 X Offset" start="244" end="247" type="u0.4"/>
<field name="4x Sample2 Y Offset" start="240" end="243" type="u0.4"/>
<field name="4x Sample1 X Offset" start="236" end="239" type="u0.4"/>
<field name="4x Sample1 Y Offset" start="232" end="235" type="u0.4"/>
<field name="4x Sample0 X Offset" start="228" end="231" type="u0.4"/>
<field name="4x Sample0 Y Offset" start="224" end="227" type="u0.4"/>
<field name="1x Sample0 X Offset" start="276" end="279" type="u0.4"/>
<field name="1x Sample0 Y Offset" start="272" end="275" type="u0.4"/>
<field name="2x Sample1 X Offset" start="268" end="271" type="u0.4"/>
<field name="2x Sample1 Y Offset" start="264" end="267" type="u0.4"/>
<field name="2x Sample0 X Offset" start="260" end="263" type="u0.4"/>
<field name="2x Sample0 Y Offset" start="256" end="259" type="u0.4"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SBE" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="31"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Force Vertex URB Entry Read Length" start="61" end="61" type="bool"/>
<field name="Force Vertex URB Entry Read Offset" start="60" end="60" type="bool"/>
<field name="Number of SF Output Attributes" start="54" end="59" type="uint"/>
<field name="Attribute Swizzle Enable" start="53" end="53" type="bool"/>
<field name="Point Sprite Texture Coordinate Origin" start="52" end="52" type="uint">
<value name="UPPERLEFT" value="0"/>
<value name="LOWERLEFT" value="1"/>
</field>
<field name="Primitive ID Override Component W" start="51" end="51" type="bool"/>
<field name="Primitive ID Override Component Z" start="50" end="50" type="bool"/>
<field name="Primitive ID Override Component Y" start="49" end="49" type="bool"/>
<field name="Primitive ID Override Component X" start="48" end="48" type="bool"/>
<field name="Vertex URB Entry Read Length" start="43" end="47" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="37" end="42" type="uint"/>
<field name="Primitive ID Override Attribute Select" start="32" end="36" type="uint"/>
<field name="Point Sprite Texture Coordinate Enable" start="64" end="95" type="uint"/>
<field name="Constant Interpolation Enable" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SBE_SWIZ" bias="2" length="11" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="81"/>
<field name="DWord Length" start="0" end="7" type="uint" default="9"/>
<group count="16" start="32" size="16">
<field name="Attribute" start="0" end="15" type="SF_OUTPUT_ATTRIBUTE_DETAIL"/>
</group>
<group count="16" start="288" size="4">
<field name="Attribute Wrap Shortest Enables" start="0" end="3" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SCISSOR_STATE_POINTERS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="15"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Scissor Rect Pointer" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SF" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="19"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Legacy Global Depth Bias Enable" start="43" end="43" type="bool"/>
<field name="Statistics Enable" start="42" end="42" type="bool"/>
<field name="Viewport Transform Enable" start="33" end="33" type="bool"/>
i965: Fix line width on Cherryview. We just add another field to gen8.xml for the Cherryview line width, rather than trying to replicate the gymnastics done in the Vulkan driver to use gen9 SF pack functions. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-04 11:03:47 -07:00
<field name="CHV Line Width" start="44" end="61" type="u11.7"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Line Width" start="82" end="91" type="u3.7"/>
<field name="Line End Cap Antialiasing Region Width" start="80" end="81" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
<field name="Last Pixel Enable" start="127" end="127" type="bool"/>
<field name="Triangle Strip/List Provoking Vertex Select" start="125" end="126" type="uint"/>
<field name="Line Strip/List Provoking Vertex Select" start="123" end="124" type="uint"/>
<field name="Triangle Fan Provoking Vertex Select" start="121" end="122" type="uint"/>
<field name="AA Line Distance Mode" start="110" end="110" type="uint">
<value name="AALINEDISTANCE_TRUE" value="1"/>
</field>
<field name="Smooth Point Enable" start="109" end="109" type="bool"/>
genxml: add missing field values for 3DSTATE_SF Fill out "Vertex Sub Pixel Precision Select" possible values. CC: 18.3 19.0 <mesa-stable@lists.freedesktop.org> Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-02-22 16:16:24 +01:00
<field name="Vertex Sub Pixel Precision Select" start="108" end="108" type="uint">
<value name="8 Bit" value="0"/>
<value name="4 Bit" value="1"/>
</field>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Point Width Source" start="107" end="107" type="uint">
<value name="Vertex" value="0"/>
<value name="State" value="1"/>
</field>
<field name="Point Width" start="96" end="106" type="u8.3"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SO_BUFFER" bias="2" length="8" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="24"/>
<field name="DWord Length" start="0" end="7" type="uint" default="6"/>
<field name="SO Buffer Enable" start="63" end="63" type="bool"/>
<field name="SO Buffer Index" start="61" end="62" type="uint"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="54" end="60" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Stream Offset Write Enable" start="53" end="53" type="bool"/>
<field name="Stream Output Buffer Offset Address Enable" start="52" end="52" type="bool"/>
<field name="Surface Base Address" start="66" end="111" type="address"/>
<field name="Surface Size" start="128" end="157" type="uint"/>
<field name="Stream Output Buffer Offset Address" start="162" end="207" type="address"/>
<field name="Stream Offset" start="224" end="255" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_SO_DECL_LIST" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="23"/>
<field name="DWord Length" start="0" end="8" type="uint"/>
<field name="Stream to Buffer Selects [3]" start="44" end="47" type="uint"/>
<field name="Stream to Buffer Selects [2]" start="40" end="43" type="uint"/>
<field name="Stream to Buffer Selects [1]" start="36" end="39" type="uint"/>
<field name="Stream to Buffer Selects [0]" start="32" end="35" type="uint"/>
<field name="Num Entries [3]" start="88" end="95" type="uint"/>
<field name="Num Entries [2]" start="80" end="87" type="uint"/>
<field name="Num Entries [1]" start="72" end="79" type="uint"/>
<field name="Num Entries [0]" start="64" end="71" type="uint"/>
<group count="0" start="96" size="64">
<field name="Entry" start="0" end="63" type="SO_DECL_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_STENCIL_BUFFER" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="6"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
intel/genxml: Make "Stencil Buffer Enable" a boolean Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:37:40 -07:00
<field name="Stencil Buffer Enable" start="63" end="63" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="54" end="60" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Surface Base Address" start="64" end="127" type="address"/>
<field name="Surface QPitch" start="128" end="142" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_STREAMOUT" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="30"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
intel/genxml: Make a couple of STREAMOUT fields booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:35:36 -07:00
<field name="SO Function Enable" start="63" end="63" type="bool"/>
<field name="Rendering Disable" start="62" end="62" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Render Stream Select" start="59" end="60" type="uint"/>
<field name="Reorder Mode" start="58" end="58" type="uint">
<value name="LEADING" value="0"/>
<value name="TRAILING" value="1"/>
</field>
<field name="SO Statistics Enable" start="57" end="57" type="bool"/>
<field name="Force Rendering" start="55" end="56" type="uint">
<value name="Resreved" value="1"/>
<value name="Force_Off" value="2"/>
<value name="Force_on" value="3"/>
</field>
<field name="Stream 3 Vertex Read Offset" start="93" end="93" type="uint"/>
<field name="Stream 3 Vertex Read Length" start="88" end="92" type="uint"/>
<field name="Stream 2 Vertex Read Offset" start="85" end="85" type="uint"/>
<field name="Stream 2 Vertex Read Length" start="80" end="84" type="uint"/>
<field name="Stream 1 Vertex Read Offset" start="77" end="77" type="uint"/>
<field name="Stream 1 Vertex Read Length" start="72" end="76" type="uint"/>
<field name="Stream 0 Vertex Read Offset" start="69" end="69" type="uint"/>
<field name="Stream 0 Vertex Read Length" start="64" end="68" type="uint"/>
<field name="Buffer 1 Surface Pitch" start="112" end="123" type="uint"/>
<field name="Buffer 0 Surface Pitch" start="96" end="107" type="uint"/>
<field name="Buffer 3 Surface Pitch" start="144" end="155" type="uint"/>
<field name="Buffer 2 Surface Pitch" start="128" end="139" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_TE" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="28"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Partitioning" start="44" end="45" type="uint">
<value name="INTEGER" value="0"/>
<value name="ODD_FRACTIONAL" value="1"/>
<value name="EVEN_FRACTIONAL" value="2"/>
</field>
<field name="Output Topology" start="40" end="41" type="uint" prefix="OUTPUT">
<value name="POINT" value="0"/>
<value name="LINE" value="1"/>
<value name="TRI_CW" value="2"/>
<value name="TRI_CCW" value="3"/>
</field>
<field name="TE Domain" start="36" end="37" type="uint">
<value name="QUAD" value="0"/>
<value name="TRI" value="1"/>
<value name="ISOLINE" value="2"/>
</field>
<field name="TE Mode" start="33" end="34" type="uint">
<value name="HW_TESS" value="0"/>
<value name="SW_TESS" value="1"/>
</field>
<field name="TE Enable" start="32" end="32" type="bool"/>
<field name="Maximum Tessellation Factor Odd" start="64" end="95" type="float"/>
<field name="Maximum Tessellation Factor Not Odd" start="96" end="127" type="float"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_URB_DS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="50"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="DS URB Starting Address" start="57" end="63" type="uint"/>
<field name="DS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="DS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_URB_GS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="51"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="GS URB Starting Address" start="57" end="63" type="uint"/>
<field name="GS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="GS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_URB_HS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="49"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="HS URB Starting Address" start="57" end="63" type="uint"/>
<field name="HS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="HS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_URB_VS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="48"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="VS URB Starting Address" start="57" end="63" type="uint"/>
<field name="VS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="VS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VERTEX_BUFFERS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="8"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<group count="0" start="32" size="128">
<field name="Vertex Buffer State" start="0" end="127" type="VERTEX_BUFFER_STATE"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VERTEX_ELEMENTS" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="9"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<group count="0" start="32" size="64">
<field name="Element" start="0" end="63" type="VERTEX_ELEMENT_STATE"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VF" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="12"/>
<field name="Indexed Draw Cut Index Enable" start="8" end="8" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Cut Index" start="32" end="63" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VF_INSTANCING" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="73"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Instancing Enable" start="40" end="40" type="bool"/>
<field name="Vertex Element Index" start="32" end="37" type="uint"/>
<field name="Instance Data Step Rate" start="64" end="95" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VF_SGVS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="74"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="InstanceID Enable" start="63" end="63" type="bool"/>
<field name="InstanceID Component Number" start="61" end="62" type="uint">
<value name="COMP_0" value="0"/>
<value name="COMP_1" value="1"/>
<value name="COMP_2" value="2"/>
<value name="COMP_3" value="3"/>
</field>
<field name="InstanceID Element Offset" start="48" end="53" type="uint"/>
<field name="VertexID Enable" start="47" end="47" type="bool"/>
<field name="VertexID Component Number" start="45" end="46" type="uint">
<value name="COMP_0" value="0"/>
<value name="COMP_1" value="1"/>
<value name="COMP_2" value="2"/>
<value name="COMP_3" value="3"/>
</field>
<field name="VertexID Element Offset" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VF_STATISTICS" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="1"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="11"/>
<field name="Statistics Enable" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VF_TOPOLOGY" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="75"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:44:22 -08:00
<field name="Primitive Topology Type" start="32" end="37" type="3D_Prim_Topo_Type"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VIEWPORT_STATE_POINTERS_CC" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="35"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="CC Viewport Pointer" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="33"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="SF Clip Viewport Pointer" start="38" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_VS" bias="2" length="9" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="16"/>
<field name="DWord Length" start="0" end="7" type="uint" default="7"/>
<field name="Kernel Start Pointer" start="38" end="95" type="offset"/>
<field name="Single Vertex Dispatch" start="127" end="127" type="bool"/>
<field name="Vector Mask Enable" start="126" end="126" type="bool"/>
<field name="Sampler Count" start="123" end="125" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="114" end="121" type="uint"/>
<field name="Thread Dispatch Priority" start="113" end="113" type="uint">
<value name="High" value="1"/>
</field>
<field name="Floating Point Mode" start="112" end="112" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="109" end="109" type="bool"/>
<field name="Accesses UAV" start="108" end="108" type="bool"/>
<field name="Software Exception Enable" start="103" end="103" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="138" end="191" type="address"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Per-Thread Scratch Space" start="128" end="131" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Dispatch GRF Start Register For URB Data" start="212" end="216" type="uint"/>
<field name="Vertex URB Entry Read Length" start="203" end="208" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="196" end="201" type="uint"/>
<field name="Maximum Number of Threads" start="247" end="255" type="uint"/>
<field name="Statistics Enable" start="234" end="234" type="bool"/>
<field name="SIMD8 Dispatch Enable" start="226" end="226" type="bool"/>
<field name="Vertex Cache Disable" start="225" end="225" type="bool"/>
genxml: 3DSTATE_VS rename Function Enable to Enable. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-22 16:26:07 -07:00
<field name="Enable" start="224" end="224" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Vertex URB Entry Output Read Offset" start="277" end="282" type="uint"/>
<field name="Vertex URB Entry Output Length" start="272" end="276" type="uint"/>
<field name="User Clip Distance Clip Test Enable Bitmask" start="264" end="271" type="uint"/>
<field name="User Clip Distance Cull Test Enable Bitmask" start="256" end="263" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_WM" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="20"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Statistics Enable" start="63" end="63" type="bool"/>
<field name="Legacy Depth Buffer Clear Enable" start="62" end="62" type="bool"/>
<field name="Legacy Depth Buffer Resolve Enable" start="60" end="60" type="bool"/>
<field name="Legacy Hierarchical Depth Buffer Resolve Enable" start="59" end="59" type="bool"/>
<field name="Legacy Diamond Line Rasterization" start="58" end="58" type="bool"/>
<field name="Early Depth/Stencil Control" start="53" end="54" type="uint">
intel/genxml: Make 3DSTATE_WM more consistent across gens Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 10:46:02 -08:00
<value name="EDSC_NORMAL" value="0"/>
<value name="EDSC_PSEXEC" value="1"/>
<value name="EDSC_PREPS" value="2"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
<field name="Force Thread Dispatch Enable" start="51" end="52" type="uint">
<value name="ForceOff" value="1"/>
<value name="ForceON" value="2"/>
</field>
<field name="Position ZW Interpolation Mode" start="49" end="50" type="uint">
<value name="INTERP_PIXEL" value="0"/>
<value name="INTERP_CENTROID" value="2"/>
<value name="INTERP_SAMPLE" value="3"/>
</field>
genxml: Add values for Barycentric Interpolation Mode Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-14 21:10:11 -08:00
<field name="Barycentric Interpolation Mode" start="43" end="48" type="uint">
<value name="BIM_PERSPECTIVE_PIXEL" value="1"/>
<value name="BIM_PERSPECTIVE_CENTROID" value ="2"/>
<value name="BIM_PERSPECTIVE_SAMPLE" value="4"/>
<value name="BIM_LINEAR_PIXEL" value="8"/>
<value name="BIM_LINEAR_CENTROID" value="16"/>
<value name="BIM_LINEAR_SAMPLE" value="32"/>
</field>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Line End Cap Antialiasing Region Width" start="40" end="41" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
<field name="Line Antialiasing Region Width" start="38" end="39" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
<field name="Polygon Stipple Enable" start="36" end="36" type="bool"/>
<field name="Line Stipple Enable" start="35" end="35" type="bool"/>
<field name="Point Rasterization Rule" start="34" end="34" type="uint">
<value name="RASTRULE_UPPER_LEFT" value="0"/>
<value name="RASTRULE_UPPER_RIGHT" value="1"/>
</field>
<field name="Force Kill Pixel Enable" start="32" end="33" type="uint">
<value name="ForceOff" value="1"/>
<value name="ForceON" value="2"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_WM_CHROMAKEY" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="76"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="ChromaKey Kill Enable" start="63" end="63" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_WM_DEPTH_STENCIL" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="78"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
intel/genxml: Use enum 3D_Stencil_Operation where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:10:57 -08:00
<field name="Stencil Fail Op" start="61" end="63" type="3D_Stencil_Operation"/>
<field name="Stencil Pass Depth Fail Op" start="58" end="60" type="3D_Stencil_Operation"/>
<field name="Stencil Pass Depth Pass Op" start="55" end="57" type="3D_Stencil_Operation"/>
intel/genxml: Use 3D_Compare_Function for gen8+ test functions When the state fields where shuffled around for gen8, the compare function enums were downgraded to just uints. Change them to enum 3D_Compare_Function. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:38:04 -08:00
<field name="Backface Stencil Test Function" start="52" end="54" type="3D_Compare_Function"/>
intel/genxml: Use enum 3D_Stencil_Operation where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:10:57 -08:00
<field name="Backface Stencil Fail Op" start="49" end="51" type="3D_Stencil_Operation"/>
<field name="Backface Stencil Pass Depth Fail Op" start="46" end="48" type="3D_Stencil_Operation"/>
<field name="Backface Stencil Pass Depth Pass Op" start="43" end="45" type="3D_Stencil_Operation"/>
intel/genxml: Use 3D_Compare_Function for gen8+ test functions When the state fields where shuffled around for gen8, the compare function enums were downgraded to just uints. Change them to enum 3D_Compare_Function. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:38:04 -08:00
<field name="Stencil Test Function" start="40" end="42" type="3D_Compare_Function"/>
<field name="Depth Test Function" start="37" end="39" type="3D_Compare_Function"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Double Sided Stencil Enable" start="36" end="36" type="bool"/>
<field name="Stencil Test Enable" start="35" end="35" type="bool"/>
<field name="Stencil Buffer Write Enable" start="34" end="34" type="bool"/>
<field name="Depth Test Enable" start="33" end="33" type="bool"/>
<field name="Depth Buffer Write Enable" start="32" end="32" type="bool"/>
<field name="Stencil Test Mask" start="88" end="95" type="uint"/>
<field name="Stencil Write Mask" start="80" end="87" type="uint"/>
<field name="Backface Stencil Test Mask" start="72" end="79" type="uint"/>
<field name="Backface Stencil Write Mask" start="64" end="71" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="3DSTATE_WM_HZ_OP" bias="2" length="5" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="82"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<field name="Stencil Buffer Clear Enable" start="63" end="63" type="bool"/>
<field name="Depth Buffer Clear Enable" start="62" end="62" type="bool"/>
<field name="Scissor Rectangle Enable" start="61" end="61" type="bool"/>
<field name="Depth Buffer Resolve Enable" start="60" end="60" type="bool"/>
<field name="Hierarchical Depth Buffer Resolve Enable" start="59" end="59" type="bool"/>
<field name="Pixel Position Offset Enable" start="58" end="58" type="bool"/>
<field name="Full Surface Depth and Stencil Clear" start="57" end="57" type="bool"/>
<field name="Stencil Clear Value" start="48" end="55" type="uint"/>
<field name="Number of Multisamples" start="45" end="47" type="uint"/>
<field name="Clear Rectangle Y Min" start="80" end="95" type="uint"/>
<field name="Clear Rectangle X Min" start="64" end="79" type="uint"/>
<field name="Clear Rectangle Y Max" start="112" end="127" type="uint"/>
<field name="Clear Rectangle X Max" start="96" end="111" type="uint"/>
<field name="Sample Mask" start="128" end="143" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="GPGPU_CSR_BASE_ADDRESS" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="GPGPU CSR Base Address" start="44" end="95" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="GPGPU_WALKER" bias="2" length="15" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="5"/>
<field name="Indirect Parameter Enable" start="10" end="10" type="bool"/>
<field name="Predicate Enable" start="8" end="8" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="13"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="102" end="127" type="offset"/>
<field name="SIMD Size" start="158" end="159" type="uint">
<value name="SIMD8" value="0"/>
<value name="SIMD16" value="1"/>
<value name="SIMD32" value="2"/>
</field>
<field name="Thread Depth Counter Maximum" start="144" end="149" type="uint"/>
<field name="Thread Height Counter Maximum" start="136" end="141" type="uint"/>
<field name="Thread Width Counter Maximum" start="128" end="133" type="uint"/>
<field name="Thread Group ID Starting X" start="160" end="191" type="uint"/>
<field name="Thread Group ID X Dimension" start="224" end="255" type="uint"/>
<field name="Thread Group ID Starting Y" start="256" end="287" type="uint"/>
<field name="Thread Group ID Y Dimension" start="320" end="351" type="uint"/>
<field name="Thread Group ID Starting/Resume Z" start="352" end="383" type="uint"/>
<field name="Thread Group ID Z Dimension" start="384" end="415" type="uint"/>
<field name="Right Execution Mask" start="416" end="447" type="uint"/>
<field name="Bottom Execution Mask" start="448" end="479" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_CURBE_LOAD" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="1"/>
<field name="DWord Length" start="0" end="15" type="uint" default="2"/>
<field name="CURBE Total Data Length" start="64" end="80" type="uint"/>
<field name="CURBE Data Start Address" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_INTERFACE_DESCRIPTOR_LOAD" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="15" type="uint" default="2"/>
<field name="Interface Descriptor Total Length" start="64" end="80" type="uint"/>
<field name="Interface Descriptor Data Start Address" start="96" end="127" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_OBJECT" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Media Command Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="Media Command Sub-Opcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="15" type="uint" default="4"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
<field name="Children Present" start="95" end="95" type="bool"/>
<field name="Thread Synchronization" start="88" end="88" type="uint">
<value name="No thread synchronization" value="0"/>
<value name="Thread dispatch is synchronized by the 'spawn root thread' message" value="1"/>
</field>
<field name="Force Destination" start="86" end="86" type="uint"/>
<field name="Use Scoreboard" start="85" end="85" type="uint">
<value name="Not using scoreboard" value="0"/>
<value name="Using scoreboard" value="1"/>
</field>
<field name="Slice Destination Select" start="83" end="84" type="uint">
<value name="Slice 0" value="0"/>
<value name="Slice 1" value="1"/>
<value name="Slice 2" value="2"/>
</field>
<field name="SubSlice Destination Select" start="81" end="82" type="uint">
<value name="SubSlice 2" value="2"/>
<value name="SubSlice 1" value="1"/>
<value name="SubSlice 0" value="0"/>
</field>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="address"/>
<field name="Scoredboard Y" start="144" end="152" type="uint"/>
<field name="Scoreboard X" start="128" end="136" type="uint"/>
<field name="Scoreboard Color" start="176" end="179" type="uint"/>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<group count="0" start="192" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_OBJECT_GRPID" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Media Command Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="Media Command Sub-Opcode" start="16" end="23" type="uint" default="6"/>
<field name="DWord Length" start="0" end="15" type="uint" default="5"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
<field name="End of Thread Group" start="87" end="87" type="uint"/>
<field name="Force Destination" start="86" end="86" type="uint"/>
<field name="Use Scoreboard" start="85" end="85" type="uint">
<value name="Not using scoreboard" value="0"/>
<value name="Using scoreboard" value="1"/>
</field>
<field name="Slice Destination Select" start="83" end="84" type="uint">
<value name="Slice 0" value="0"/>
<value name="Slice 1" value="1"/>
<value name="Slice 2" value="2"/>
</field>
<field name="SubSlice Destination Select" start="81" end="82" type="uint">
<value name="SubSlice 2" value="2"/>
<value name="SubSlice 1" value="1"/>
<value name="SubSlice 0" value="0"/>
</field>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="address"/>
<field name="Scoreboard Y" start="144" end="152" type="uint"/>
<field name="Scoreboard X" start="128" end="136" type="uint"/>
<field name="Scoreboard Color" start="176" end="179" type="uint"/>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<field name="GroupID" start="192" end="223" type="uint"/>
<group count="0" start="224" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_OBJECT_PRT" bias="2" length="16" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="15" type="uint" default="14"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
<field name="Children Present" start="95" end="95" type="bool"/>
<field name="PRT_Fence Needed" start="87" end="87" type="bool"/>
<field name="PRT_FenceType" start="86" end="86" type="uint">
<value name="Root thread queue" value="0"/>
<value name="VFE state flush" value="1"/>
</field>
<group count="12" start="128" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_OBJECT_WALKER" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="15" type="uint" default="15"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
<field name="Children Present" start="95" end="95" type="uint"/>
<field name="Thread Synchronization" start="88" end="88" type="uint">
<value name="No thread synchronization" value="0"/>
<value name="Thread dispatch is synchronized by the 'spawn root thread' message" value="1"/>
</field>
<field name="Use Scoreboard" start="85" end="85" type="uint">
<value name="Not using scoreboard" value="0"/>
<value name="Using scoreboard" value="1"/>
</field>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="offset"/>
<field name="Group ID Loop Select" start="168" end="191" type="uint"/>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<field name="Color Count Minus One" start="216" end="219" type="uint"/>
<field name="Middle Loop Extra Steps" start="208" end="212" type="uint"/>
<field name="Local Mid-Loop Unit Y" start="204" end="205" type="int"/>
<field name="Mid-Loop Unit X" start="200" end="201" type="int"/>
<field name="Global Loop Exec Count" start="240" end="249" type="uint"/>
<field name="Local Loop Exec Count" start="224" end="233" type="uint"/>
<field name="Block Resolution Y" start="272" end="280" type="uint"/>
<field name="Block Resolution X" start="256" end="264" type="uint"/>
<field name="Local Start Y" start="304" end="312" type="uint"/>
<field name="Local Start X" start="288" end="296" type="uint"/>
<field name="Local Outer Loop Stride Y" start="368" end="377" type="int"/>
<field name="Local Outer Loop Stride X" start="352" end="361" type="int"/>
<field name="Local Inner Loop Unit Y" start="400" end="409" type="int"/>
<field name="Local Inner Loop Unit X" start="384" end="393" type="int"/>
<field name="Global Resolution Y" start="432" end="440" type="uint"/>
<field name="Global Resolution X" start="416" end="424" type="uint"/>
<field name="Global Start Y" start="464" end="473" type="int"/>
<field name="Global Start X" start="448" end="457" type="int"/>
<field name="Global Outer Loop Stride Y" start="496" end="505" type="int"/>
<field name="Global Outer Loop Stride X" start="480" end="489" type="int"/>
<field name="Global Inner Loop Unit Y" start="528" end="537" type="int"/>
<field name="Global Inner Loop Unit X" start="512" end="521" type="int"/>
<group count="0" start="544" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_STATE_FLUSH" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="15" type="uint" default="0"/>
<field name="Flush to GO" start="39" end="39" type="bool"/>
<field name="Watermark Required" start="38" end="38" type="uint"/>
<field name="Interface Descriptor Offset" start="32" end="37" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MEDIA_VFE_STATE" bias="2" length="9" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="15" type="uint" default="7"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="42" end="79" type="address"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Stack Size" start="36" end="39" type="uint"/>
<field name="Per Thread Scratch Space" start="32" end="35" type="uint"/>
<field name="Maximum Number of Threads" start="112" end="127" type="uint"/>
<field name="Number of URB Entries" start="104" end="111" type="uint"/>
<field name="Reset Gateway Timer" start="103" end="103" type="uint">
<value name="Maintaining the existing timestamp state" value="0"/>
<value name="Resetting relative timer and latching the global timestamp" value="1"/>
</field>
<field name="Bypass Gateway Control" start="102" end="102" type="uint">
<value name="Maintaining OpenGateway/ForwardMsg/CloseGateway protocol (legacy mode)" value="0"/>
<value name="Bypassing OpenGateway/CloseGateway protocol" value="1"/>
</field>
<field name="Slice Disable" start="128" end="129" type="uint">
<value name="All Subslices Enabled" value="0"/>
<value name="Only Slice 0 Enabled" value="1"/>
<value name="Only Slice 0 Subslice 0 Enabled" value="3"/>
</field>
<field name="URB Entry Allocation Size" start="176" end="191" type="uint"/>
<field name="CURBE Allocation Size" start="160" end="175" type="uint"/>
<field name="Scoreboard Enable" start="223" end="223" type="bool"/>
<field name="Scoreboard Type" start="222" end="222" type="uint">
<value name="Stalling Scoreboard" value="0"/>
<value name="Non-Stalling Scoreboard" value="1"/>
</field>
<field name="Scoreboard Mask" start="192" end="199" type="uint"/>
<field name="Scoreboard 3 Delta Y" start="252" end="255" type="int"/>
<field name="Scoreboard 3 Delta X" start="248" end="251" type="int"/>
<field name="Scoreboard 2 Delta Y" start="244" end="247" type="int"/>
<field name="Scoreboard 2 Delta X" start="240" end="243" type="int"/>
<field name="Scoreboard 1 Delta Y" start="236" end="239" type="int"/>
<field name="Scoreboard 1 Delta X" start="232" end="235" type="int"/>
<field name="Scoreboard 0 Delta Y" start="228" end="231" type="int"/>
<field name="Scoreboard 0 Delta X" start="224" end="227" type="int"/>
<field name="Scoreboard 7 Delta Y" start="284" end="287" type="int"/>
<field name="Scoreboard 7 Delta X" start="280" end="283" type="int"/>
<field name="Scoreboard 6 Delta Y" start="276" end="279" type="int"/>
<field name="Scoreboard 6 Delta X" start="272" end="275" type="int"/>
<field name="Scoreboard 5 Delta Y" start="268" end="271" type="int"/>
<field name="Scoreboard 5 Delta X" start="264" end="267" type="int"/>
<field name="Scoreboard 4 Delta Y" start="260" end="263" type="int"/>
<field name="Scoreboard 4 Delta X" start="256" end="259" type="int"/>
</instruction>
intel/genxml: Media instructions and structures for gen8 v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com> - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:54:25 +02:00
<instruction name="MFC_AVC_PAK_OBJECT" bias="2" length="12" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="10"/>
<field name="Indirect PAK-MV Data Length" start="32" end="41" type="uint"/>
<field name="Indirect PAK-MV Data Start Address Offset" start="64" end="92" type="offset"/>
<group count="8" start="96" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFC_MPEG2_PAK_OBJECT" bias="2" length="9" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="7"/>
<group count="8" start="32" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFC_MPEG2_SLICEGROUP_STATE" bias="2" length="8" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="3"/>
<field name="DWord Length" start="0" end="11" type="uint" default="6"/>
<field name="Rate Control Counter Enable" start="63" end="63" type="bool"/>
<field name="Reset Rate Control Counter" start="62" end="62" type="bool"/>
<field name="Rate Control Triggle Mode" start="60" end="61" type="uint">
<value name="Always Rate Control" value="0"/>
<value name="Gentle Rate Control" value="1"/>
<value name="Loose Rate Control" value="2"/>
</field>
<field name="Rate Control Stable Tolerance" start="56" end="59" type="uint"/>
<field name="Rate Control Panic Enable" start="55" end="55" type="bool"/>
<field name="Rate Control Panic Type" start="54" end="54" type="uint">
<value name="QP Panic" value="0"/>
<value name="CBP Panic" value="1"/>
</field>
<field name="MB Type Skip Conversion Disable" start="52" end="52" type="bool"/>
<field name="Last Slice" start="51" end="51" type="bool"/>
<field name="Compressed BitStream Output Disable" start="50" end="50" type="bool"/>
<field name="Header Insertion Present" start="49" end="49" type="bool"/>
<field name="Slice Data Insertion Present" start="48" end="48" type="bool"/>
<field name="Tail Insertion Present" start="47" end="47" type="bool"/>
<field name="First Slice Header Disable" start="46" end="46" type="bool"/>
<field name="Intra Slice" start="45" end="45" type="bool"/>
<field name="Intra Slice Flag" start="44" end="44" type="bool"/>
<field name="Slice ID" start="36" end="39" type="uint"/>
<field name="Stream ID" start="32" end="33" type="uint"/>
<field name="Next Slice Group MB Y Count" start="88" end="95" type="uint"/>
<field name="Next Slice Group MB X Count" start="80" end="87" type="uint"/>
<field name="First MB Y Count" start="72" end="79" type="uint"/>
<field name="First MB X Count" start="64" end="71" type="uint"/>
<field name="Slice Group Skip" start="104" end="104" type="bool"/>
<field name="Slice Group QP" start="96" end="101" type="uint"/>
<field name="Indirect PAK-BSE Data Start Address" start="128" end="156" type="offset"/>
<field name="QP Max Negative Modifier Magnitude" start="184" end="191" type="uint"/>
<field name="QP Max Positive Modifier Magnitude" start="176" end="183" type="uint"/>
<field name="Shrink Resistance" start="172" end="175" type="uint"/>
<field name="Shrink Init" start="168" end="171" type="uint"/>
<field name="Grow Resistance" start="164" end="167" type="uint"/>
<field name="Grow Init" start="160" end="163" type="uint"/>
<field name="Correct 6" start="212" end="215" type="uint"/>
<field name="Correct 5" start="208" end="211" type="uint"/>
<field name="Correct 4" start="204" end="207" type="uint"/>
<field name="Correct 3" start="200" end="203" type="uint"/>
<field name="Correct 2" start="196" end="199" type="uint"/>
<field name="Correct 1" start="192" end="195" type="uint"/>
<field name="CV7" start="252" end="255" type="uint"/>
<field name="CV6" start="248" end="251" type="uint"/>
<field name="CV5" start="244" end="247" type="uint"/>
<field name="CV4" start="240" end="243" type="uint"/>
<field name="CV3" start="236" end="239" type="uint"/>
<field name="CV2" start="232" end="235" type="uint"/>
<field name="CV1" start="228" end="231" type="uint"/>
<field name="CV0" start="224" end="227" type="uint"/>
</instruction>
<instruction name="MFD_AVC_BSD_OBJECT" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Indirect BSD Data Length" start="32" end="63" type="uint"/>
<field name="Indirect BSD Data Start Address" start="64" end="92" type="address"/>
<field name="Inline Data" start="96" end="191" type="INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT"/>
</instruction>
<instruction name="MFD_AVC_DPB_STATE" bias="2" length="27" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="6"/>
<field name="DWord Length" start="0" end="11" type="uint" default="9"/>
<group count="16" start="48" size="1">
<field name="Long Term Frame" start="0" end="0" type="uint"/>
</group>
<group count="16" start="32" size="1">
<field name="Non-Existing Frame" start="0" end="0" type="uint">
<value name="INVALID" value="1"/>
<value name="VALID" value="0"/>
</field>
</group>
<group count="16" start="64" size="2">
<field name="Used for Reference" start="0" end="1" type="uint">
<value name="NOT_REFERENCE" value="0"/>
<value name="TOP_FIELD" value="1"/>
<value name="BOTTOM_FIELD" value="2"/>
<value name="FRAME" value="3"/>
</field>
</group>
<group count="16" start="96" size="16">
<field name="LTST Frame Number List" start="0" end="15" type="uint" prefix="LTST">
<value name="Long Term Frame" value="1"/>
<value name="Short Term Frame" value="0"/>
</field>
</group>
<group count="16" start="352" size="16">
<field name="View ID" start="0" end="15" type="uint"/>
</group>
<group count="16" start="608" size="8">
<field name="L0 View Order" start="0" end="7" type="uint"/>
</group>
<group count="16" start="736" size="8">
<field name="L1 View Order" start="0" end="7" type="uint"/>
</group>
</instruction>
<instruction name="MFD_AVC_PICID_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="5"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="PictureID Remapping Disable" start="32" end="32" type="uint">
<value name="Use 16 bits Picture ID" value="0"/>
<value name="Use 4 bits FrameStoreID" value="1"/>
</field>
<group count="16" start="64" size="16">
<field name="Picture ID" start="0" end="15" type="uint"/>
</group>
</instruction>
<instruction name="MFD_AVC_SLICEADDR" bias="2" length="3" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="7"/>
<field name="DWord Length" start="0" end="11" type="uint" default="1"/>
<field name="Indirect BSD Data Length" start="32" end="63" type="uint"/>
<field name="Indirect BSD Data Start Address" start="64" end="92" type="address"/>
</instruction>
<instruction name="MFD_IT_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="6"/>
<field name="Indirect IT-MV Data Length" start="32" end="41" type="uint"/>
<field name="Indirect IT-MV Data Start Address Offset" start="64" end="92" type="offset"/>
<field name="Indirect IT-COEFF Data Length" start="96" end="107" type="uint"/>
<field name="Indirect IT-COEFF Data Start Address Offset" start="128" end="156" type="offset"/>
<field name="Indirect IT-DBLK Control Data Length" start="160" end="165" type="uint"/>
<field name="Indirect IT-DBLK Control Data Start Address Offset" start="192" end="220" type="offset"/>
<group count="0" start="224" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFD_JPEG_BSD_OBJECT" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="7"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Indirect Data Length" start="32" end="63" type="uint"/>
<field name="Indirect Data Start Address" start="64" end="92" type="offset"/>
<field name="Scan Horizontal Position" start="112" end="124" type="uint"/>
<field name="Scan Vertical Position" start="96" end="108" type="uint"/>
<field name="Interleaved" start="158" end="158" type="bool"/>
<field name="Scan Components" start="155" end="157" type="uint"/>
<field name="MCU Count" start="128" end="153" type="uint"/>
<field name="Restart Interval" start="160" end="175" type="uint"/>
</instruction>
<instruction name="MFD_MPEG2_BSD_OBJECT" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="3"/>
<field name="Indirect BSD Data Length" start="32" end="63" type="uint"/>
<field name="Indirect BSD Data Start Address" start="64" end="92" type="offset"/>
<field name="Inline Data" start="96" end="159" type="MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION"/>
</instruction>
<instruction name="MFD_VC1_BSD_OBJECT" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="3"/>
<field name="Indirect BSD Data Length" start="32" end="55" type="uint"/>
<field name="Indirect BSD Data Start Address" start="64" end="92" type="offset"/>
<field name="Slice Start Vertical Position" start="112" end="119" type="uint"/>
<field name="Next Slice Vertical Position" start="96" end="104" type="uint"/>
<field name="First MB Byte Offset of Slice Data or Slice Header" start="144" end="159" type="uint"/>
<field name="Emulation Prevention Byte Present" start="132" end="132" type="uint"/>
<field name="First MB Bit Offset" start="128" end="130" type="uint"/>
</instruction>
<instruction name="MFD_VC1_LONG_PIC_STATE" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Picture Height In MBs" start="48" end="55" type="uint"/>
<field name="Picture Width In MBs" start="32" end="39" type="uint"/>
<field name="Bitplane Buffer Pitch" start="88" end="95" type="uint"/>
<field name="DMV Surface Valid" start="79" end="79" type="bool"/>
<field name="Implicit Quantizer" start="78" end="78" type="bool"/>
<field name="Interpolation Rounder Control" start="77" end="77" type="bool"/>
<field name="Sync Marker" start="76" end="76" type="bool"/>
<field name="MV Mode" start="72" end="75" type="uint"/>
<field name="Range Reduction Scale" start="71" end="71" type="uint"/>
<field name="Range Reduction Enable" start="70" end="70" type="bool"/>
<field name="Loop Filter Enable" start="69" end="69" type="bool"/>
<field name="Overlap Smoothing Enable" start="68" end="68" type="bool"/>
<field name="Second Field" start="67" end="67" type="bool"/>
<field name="VC1 Profile" start="64" end="64" type="uint">
<value name="Simple/Main Profile" value="0"/>
<value name="Advanced Profile" value="1"/>
</field>
<field name="CONDOVER" start="125" end="126" type="uint"/>
<field name="Picure Type" start="122" end="124" type="uint"/>
<field name="Frame Coding Mode" start="120" end="121" type="uint">
<value name="Progressive Frame Picture" value="0"/>
<value name="Interlaced Frame Picture" value="1"/>
<value name="Field Picture with Top Field First" value="2"/>
<value name="Field Picture with Bottom Field First" value="3"/>
</field>
<field name="Alternative PQ Value" start="112" end="116" type="uint"/>
<field name="PQ Value" start="104" end="108" type="uint"/>
<field name="B Scale Factor" start="96" end="103" type="uint"/>
<field name="Unified MV Mode" start="156" end="157" type="uint">
<value name="1-MV half-pel bilinear" value="3"/>
<value name="1-MV" value="1"/>
<value name="1-MV half-pel" value="2"/>
<value name="Mixed MV" value="0"/>
</field>
<field name="Four MV Switch" start="155" end="155" type="uint">
<value name="Only 1-MV" value="0"/>
<value name="1, 2, or 4 MVs" value="1"/>
</field>
<field name="Fast UV Motion Compensation" start="154" end="154" type="uint">
<value name="No Rounding" value="0"/>
<value name="Quarter-Pel offsets to Half/Full pel positions" value="1"/>
</field>
<field name="Reference Field Picture Polarity" start="153" end="153" type="uint">
<value name="Top (even) Field" value="0"/>
<value name="Bottom (odd) Field" value="1"/>
</field>
<field name="Number of References" start="152" end="152" type="uint">
<value name="One field referenced" value="0"/>
<value name="Two fields referenced" value="1"/>
</field>
<field name="Backward Reference Distance" start="148" end="151" type="uint"/>
<field name="Forward Reference Distance" start="144" end="147" type="uint"/>
<field name="Extended DMV Range" start="138" end="139" type="uint"/>
<field name="Extended MV Range" start="136" end="137" type="uint"/>
<field name="Alternative PQ Edge Mask" start="132" end="135" type="uint"/>
<field name="Alternative PQ Configuration" start="130" end="131" type="uint"/>
<field name="Half QP" start="129" end="129" type="bool"/>
<field name="PQ Uniform" start="128" end="128" type="bool"/>
<field name="Bitplane Buffer Present" start="191" end="191" type="bool"/>
<field name="FORWARDMB Raw" start="190" end="190" type="bool"/>
<field name="MVTYPEMB Raw" start="189" end="189" type="bool"/>
<field name="SKIPMB Raw" start="188" end="188" type="bool"/>
<field name="DIRECTMB Raw" start="187" end="187" type="bool"/>
<field name="OVERFLAGS Raw" start="186" end="186" type="bool"/>
<field name="ACPRED Raw" start="185" end="185" type="bool"/>
<field name="FIELDTX Raw" start="184" end="184" type="bool"/>
<field name="MV Table" start="180" end="182" type="uint"/>
<field name="4-MV Block Pattern Table" start="178" end="179" type="uint"/>
<field name="2-MV Block Pattern Table" start="176" end="177" type="uint"/>
<field name="Picture-level Transform Type" start="172" end="173" type="uint">
<value name="8x8 Transform" value="0"/>
<value name="8x4 Transform" value="1"/>
<value name="4x8 Transform" value="2"/>
<value name="4x4 Transform" value="3"/>
</field>
<field name="MB Transform Type" start="171" end="171" type="bool"/>
<field name="MB Mode Table" start="168" end="170" type="uint"/>
<field name="Picture-level Transform Luma AC Coding Set Index" start="166" end="167" type="uint"/>
<field name="Picture-level Transform Chroma AC Coding Set Index" start="164" end="165" type="uint"/>
<field name="Intra Transform DC Table" start="163" end="163" type="uint"/>
<field name="Coded Block Pattern Table" start="160" end="162" type="uint"/>
</instruction>
<instruction name="MFD_VC1_SHORT_PIC_STATE" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="3"/>
<field name="Picture Height" start="48" end="55" type="uint"/>
<field name="Picture Width" start="32" end="39" type="uint"/>
<field name="Bitplane Buffer Pitch" start="88" end="95" type="uint"/>
<field name="Interpolation Rounder Control" start="87" end="87" type="bool"/>
<field name="MV Mode" start="80" end="83" type="uint"/>
<field name="DMV Surface Valid" start="79" end="79" type="bool"/>
<field name="VC1 Profile" start="75" end="75" type="uint">
<value name="Simple/Main Profile" value="0"/>
<value name="Advanced Profile" value="1"/>
</field>
<field name="Backward Prediction Present" start="69" end="69" type="bool"/>
<field name="Intra Picture" start="68" end="68" type="bool"/>
<field name="Second Field" start="67" end="67" type="bool"/>
<field name="Picture Structure" start="64" end="65" type="uint"/>
<field name="Overlap Smoothing Enable" start="126" end="126" type="bool"/>
<field name="Range Reduction Scale" start="125" end="125" type="uint"/>
<field name="Range Reduction Enable" start="124" end="124" type="uint"/>
<field name="Progressive Pic Type" start="118" end="119" type="uint"/>
<field name="P-Pic Ref Distance" start="112" end="116" type="uint"/>
<field name="QUANTIZER" start="110" end="111" type="uint"/>
<field name="MULTIRES Present" start="109" end="109" type="bool"/>
<field name="SYNCMARKER Present" start="108" end="108" type="bool"/>
<field name="RANGERED Present" start="107" end="107" type="bool"/>
<field name="MAXBFRAMES" start="104" end="106" type="uint"/>
<field name="PANSCAN Present" start="103" end="103" type="bool"/>
<field name="REFDIST_FLAG" start="102" end="102" type="bool"/>
<field name="Loop Filter Enable" start="101" end="101" type="bool"/>
<field name="Fast UV Motion Compensation" start="100" end="100" type="uint">
<value name="No Rounding" value="0"/>
<value name="Quarter-Pel offsets to Half/Full pel positions" value="1"/>
</field>
<field name="EXTENDED_MV Present" start="99" end="99" type="bool"/>
<field name="DQUANT" start="97" end="98" type="uint"/>
<field name="variable-sized transform coding" start="96" end="96" type="bool"/>
<field name="BFraction Enumeration" start="152" end="156" type="uint"/>
<field name="4-MV Allowed" start="136" end="136" type="bool"/>
<field name="POSTPROC" start="135" end="135" type="bool"/>
<field name="PULLDOWN" start="134" end="134" type="bool"/>
<field name="INTERLACE" start="133" end="133" type="bool"/>
<field name="TFCNTRFLAG" start="132" end="132" type="bool"/>
<field name="FINTERFLAG" start="131" end="131" type="bool"/>
<field name="REFPIC" start="130" end="130" type="bool"/>
<field name="PSF" start="129" end="129" type="bool"/>
<field name="EXTENDED_DMV Present" start="128" end="128" type="bool"/>
</instruction>
<instruction name="MFD_VP8_BSD_OBJECT" bias="2" length="22" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command OpCode" start="24" end="26" type="uint" default="4"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="20"/>
<field name="Partition0 CPBAC Entropy Count" start="48" end="52" type="uint"/>
<field name="Partition0 CPBAC Entropy Range" start="40" end="47" type="uint"/>
<field name="Coded Num of Coeff Token Partitions" start="36" end="37" type="uint"/>
<field name="Partition0 First MB Bit Offset from Frame Header" start="32" end="34" type="uint"/>
<field name="Partition0 CPBAC Entropy Value" start="88" end="95" type="uint"/>
<field name="Indirect Partition0 Data Length" start="96" end="119" type="uint"/>
<field name="Indirect Partition0 Data Start Offset" start="128" end="159" type="uint"/>
<field name="Indirect Partition1 Data Length" start="160" end="183" type="uint"/>
<field name="Indirect Partition1 Data Start Offset" start="192" end="223" type="uint"/>
<field name="Indirect Partition2 Data Length" start="224" end="247" type="uint"/>
<field name="Indirect Partition2 Data Start Offset" start="256" end="287" type="uint"/>
<field name="Indirect Partition3 Data Length" start="288" end="311" type="uint"/>
<field name="Indirect Partition3 Data Start Offset" start="320" end="351" type="uint"/>
<field name="Indirect Partition4 Data Length" start="352" end="375" type="uint"/>
<field name="Indirect Partition4 Data Start Offset" start="384" end="415" type="uint"/>
<field name="Indirect Partition5 Data Length" start="416" end="439" type="uint"/>
<field name="Indirect Partition5 Data Start Offset" start="448" end="479" type="uint"/>
<field name="Indirect Partition6 Data Length" start="480" end="503" type="uint"/>
<field name="Indirect Partition6 Data Start Offset" start="512" end="543" type="uint"/>
<field name="Indirect Partition7 Data Length" start="544" end="567" type="uint"/>
<field name="Indirect Partition7 Data Start Offset" start="576" end="607" type="uint"/>
<field name="Indirect Partition8 Data Length" start="608" end="631" type="uint"/>
<field name="Indirect Partition8 Data Start Offset" start="640" end="671" type="uint"/>
<field name="Concealment Method" start="703" end="703" type="uint">
<value name="Intra 16x16 Prediction" value="0"/>
<value name="Inter P Copy" value="1"/>
</field>
<field name="Concealment Picture ID" start="688" end="689" type="uint"/>
<field name="BSD Premature Complete Error Handling" start="686" end="686" type="uint"/>
<field name="MPR Error (MV out of range) Handling" start="684" end="684" type="uint"/>
<field name="Entropy Error Handling" start="682" end="682" type="uint"/>
<field name="MB Header Error Handling" start="680" end="680" type="uint"/>
</instruction>
<instruction name="MFX_AVC_DIRECTMODE_STATE" bias="2" length="71" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="69"/>
<group count="16" start="32" size="64">
<field name="Direct MV Buffer - Address" start="0" end="63" type="address"/>
</group>
<field name="Direct MV Buffer - Attributes" start="1056" end="1087" type="MEMORYADDRESSATTRIBUTES"/>
<field name="Direct MV Buffer (Write) - Address" start="1088" end="1151" type="address"/>
<field name="Direct MV Buffer (Write) - Attributes" start="1152" end="1183" type="MEMORYADDRESSATTRIBUTES"/>
<group count="34" start="1184" size="32">
<field name="POC List" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_AVC_IMG_STATE" bias="2" length="14" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="12"/>
<field name="Frame Size" start="32" end="47" type="uint"/>
<field name="Frame Height" start="80" end="87" type="uint"/>
<field name="Frame Width" start="64" end="71" type="uint"/>
<field name="Second Chroma QP Offset" start="120" end="124" type="uint"/>
<field name="First Chroma QP Offset" start="112" end="116" type="uint"/>
<field name="Weighted Prediction Enable" start="108" end="108" type="bool"/>
<field name="Weighted BiPrediction IDC" start="106" end="107" type="uint">
<value name="DEFAULT" value="0"/>
<value name="EXPLICIT" value="1"/>
<value name="IMPLICIT" value="2"/>
</field>
<field name="Image Structure" start="104" end="105" type="uint">
<value name="Frame Picture" value="0"/>
<value name="Top Field Picture" value="1"/>
<value name="Bottom Field Picture" value="3"/>
<value name="Invalid, not allowed." value="2"/>
</field>
<field name="Minimum Frame Size" start="144" end="159" type="uint"/>
<field name="MB Status Read" start="143" end="143" type="bool"/>
<field name="Load Bitstream Pointer Per Slice" start="142" end="142" type="bool"/>
<field name="MV Unpacked Enable" start="140" end="140" type="bool"/>
<field name="Chroma Format IDC" start="138" end="139" type="uint">
<value name="Monochrome picture" value="0"/>
<value name="4:2:0 picture" value="1"/>
<value name="4:2:2 picture (not supported)" value="2"/>
<value name="4:4:4 picture (not supported)" value="3"/>
</field>
<field name="MB MV Format" start="136" end="136" type="uint">
<value name="IGNORE" value="0"/>
<value name="FOLLOW" value="1"/>
</field>
<field name="Entropy Coding Sync Enable" start="135" end="135" type="bool"/>
<field name="Non-Reference Picture" start="134" end="134" type="bool"/>
<field name="Constrained Intra Prediction" start="133" end="133" type="bool"/>
<field name="Direct 8x8 Inference" start="132" end="132" type="bool"/>
<field name="8x8 IDCT Transform Mode" start="131" end="131" type="bool"/>
<field name="Frame MB Only" start="130" end="130" type="bool"/>
<field name="MBAFF Mode" start="129" end="129" type="bool"/>
<field name="Field Picure" start="128" end="128" type="bool"/>
<field name="Trellis Quantization Enable" start="191" end="191" type="bool"/>
<field name="Trellis Quantization Rounding" start="188" end="190" type="uint"/>
<field name="Trellis Quantization Chroma Disable" start="187" end="187" type="bool"/>
<field name="Non First Pass" start="176" end="176" type="uint"/>
<field name="Minimum Frame Size Units" start="170" end="171" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="16 bytes" value="1"/>
<value name="4Kb" value="2"/>
<value name="16Kb" value="3"/>
</field>
<field name="MB Level Rate Control" start="169" end="169" type="bool"/>
<field name="Force IPCM Control" start="167" end="167" type="bool"/>
<field name="Frame Bitrate Min Report" start="163" end="163" type="bool"/>
<field name="Frame Bitrate Max Report" start="162" end="162" type="bool"/>
<field name="Inter MB Max Bit Control" start="161" end="161" type="bool"/>
<field name="Intra MB Max Bit Control" start="160" end="160" type="bool"/>
<field name="Inter MB Conformance Max Size" start="208" end="219" type="uint"/>
<field name="Intra MB Conformance Max Size" start="192" end="203" type="uint"/>
<field name="Slice Delta QP Max[3]" start="280" end="287" type="int"/>
<field name="Slice Delta QP Max[2]" start="272" end="279" type="uint"/>
<field name="Slice Delta QP Max[1]" start="264" end="271" type="int"/>
<field name="Slice Delta QP Max[0]" start="256" end="263" type="int"/>
<field name="Slice Delta QP Min[3]" start="312" end="319" type="int"/>
<field name="Slice Delta QP Min[2]" start="304" end="311" type="int"/>
<field name="Slice Delta QP Min[1]" start="296" end="303" type="int"/>
<field name="Slice Delta QP Min[0]" start="288" end="295" type="int"/>
<field name="Frame Bitrate Max Unit" start="351" end="351" type="uint"/>
<field name="Frame Bitrate Max Unit Mode" start="350" end="350" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="New mode" value="1"/>
</field>
<field name="Frame Bitrate Max" start="336" end="349" type="uint"/>
<field name="Frame Bitrate Min Unit" start="335" end="335" type="uint"/>
<field name="Frame Bitrate Min Unit Mode" start="334" end="334" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="New mode" value="1"/>
</field>
<field name="Frame Bitrate Min" start="320" end="333" type="uint"/>
<field name="Slice Stats Stream-Out Enable" start="383" end="383" type="bool"/>
<field name="Frame Bitrate Max Delta" start="368" end="382" type="uint"/>
<field name="Frame Bitrate Min Delta" start="352" end="366" type="uint"/>
<field name="Current Picture Has Performed MMCO5" start="445" end="445" type="bool"/>
<field name="Number of Reference Frames" start="440" end="444" type="uint"/>
<field name="Number of Active Reference Pictures from L1" start="432" end="437" type="uint"/>
<field name="Number of Active Reference Pictures from L0" start="424" end="429" type="uint"/>
<field name="Initial QP Value" start="416" end="423" type="int"/>
<field name="Log2 Max Pic Order Count LSB" start="472" end="479" type="uint"/>
<field name="Log2 Max Frame Number" start="464" end="471" type="uint"/>
<field name="Deblocking Filter Control Present" start="463" end="463" type="bool"/>
<field name="Number of Slice Groups" start="460" end="462" type="uint"/>
<field name="Redundant Pic Count Present" start="459" end="459" type="bool"/>
<field name="Slice Group Map Type" start="456" end="458" type="uint"/>
<field name="Pic Order Count Type" start="450" end="451" type="uint"/>
<field name="Delta Pic Order Always Zero" start="449" end="449" type="bool"/>
<field name="Pic Order Present" start="448" end="448" type="bool"/>
<field name="Current Picture Frame Number" start="496" end="511" type="uint"/>
<field name="Slice Group Change Rate" start="480" end="495" type="uint"/>
<field name="Inter View Order Disable" start="543" end="543" type="bool"/>
<field name="Max View IDXL1" start="530" end="533" type="uint"/>
<field name="Max View IDXL0" start="524" end="527" type="uint"/>
<field name="Current Frame View ID" start="512" end="521" type="uint"/>
</instruction>
<instruction name="MFX_AVC_REF_IDX_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="4"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="Reference Picture List Select" start="32" end="32" type="uint"/>
<group count="32" start="64" size="8">
<field name="Reference List Entry" start="0" end="7" type="uint"/>
</group>
</instruction>
<instruction name="MFX_AVC_SLICE_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="3"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="Slice Type" start="32" end="35" type="uint">
<value name="P Slice" value="0"/>
<value name="B Slice" value="1"/>
<value name="I Slice" value="2"/>
</field>
<field name="Number of Reference Pictures in Inter-prediction List 1" start="88" end="93" type="uint"/>
<field name="Number of Reference Pictures in Inter-prediction List 0" start="80" end="85" type="uint"/>
<field name="Log2 Weight Denominator Chroma" start="72" end="74" type="uint"/>
<field name="Log2 Weight Denominator Luma" start="64" end="66" type="uint"/>
<field name="Weighted Prediction Indicator" start="126" end="127" type="uint"/>
<field name="Direct Prediction Type" start="125" end="125" type="uint">
<value name="Temporal" value="0"/>
<value name="Spatial" value="1"/>
</field>
<field name="Disable Deblocking Filter Indicator" start="123" end="124" type="uint"/>
<field name="CABAC Init IDC" start="120" end="121" type="uint"/>
<field name="Slice Quantization Parameter" start="112" end="117" type="uint"/>
<field name="Slice Beta Offset Div2" start="104" end="107" type="int"/>
<field name="Slice Alpha C0 Offset Div2" start="96" end="99" type="int"/>
<field name="Slice Vertical Position" start="152" end="159" type="uint"/>
<field name="Slice Horizontal Position" start="144" end="151" type="uint"/>
<field name="Slice Start MB Number" start="128" end="142" type="uint"/>
<field name="Next Slice Vertical Position" start="176" end="183" type="uint"/>
<field name="Next Slice Horizontal Position" start="160" end="167" type="uint"/>
<field name="Rate Control Counter Enable" start="223" end="223" type="uint"/>
<field name="Reset Rate Control Counter" start="222" end="222" type="bool"/>
<field name="Rate Control Triggle Mode" start="220" end="221" type="uint">
<value name="Always Rate Control" value="0"/>
<value name="Gentle Rate Control" value="1"/>
<value name="Loose Rate Control" value="2"/>
</field>
<field name="Rate Control Stable Tolerance" start="216" end="219" type="uint"/>
<field name="Rate Control Panic Enable" start="215" end="215" type="bool"/>
<field name="Rate Control Panic Type" start="214" end="214" type="uint">
<value name="QP Panic" value="0"/>
<value name="CBP Panic" value="1"/>
</field>
<field name="MB Type Direct Conversion Disable" start="213" end="213" type="bool"/>
<field name="MB Type Skip Conversion Disable" start="212" end="212" type="bool"/>
<field name="Last Slice Group" start="211" end="211" type="bool"/>
<field name="Header Insertion Present" start="209" end="209" type="bool"/>
<field name="Slice Data Insertion Present" start="208" end="208" type="bool"/>
<field name="Tail Insertion Present" start="207" end="207" type="bool"/>
<field name="Emulation Byte Slice Insert Enable" start="205" end="205" type="bool"/>
<field name="CABAC Zero Word Insertion Enable" start="204" end="204" type="bool"/>
<field name="Slice ID" start="196" end="199" type="uint"/>
<field name="Stream ID" start="192" end="193" type="uint"/>
<field name="Indirect PAK-BSE Data Start Address" start="224" end="252" type="offset"/>
<field name="QP Max Negative Modifier Magnitude" start="280" end="287" type="uint"/>
<field name="QP Max Positive Modifier Magnitude" start="272" end="279" type="uint"/>
<field name="Shrink Resistance" start="268" end="271" type="uint"/>
<field name="Shrink Init" start="264" end="267" type="uint"/>
<field name="Grow Resistance" start="260" end="263" type="uint"/>
<field name="Grow Init" start="256" end="259" type="uint"/>
<field name="Round Inter Enable" start="319" end="319" type="bool"/>
<field name="Round Inter" start="316" end="318" type="uint">
<value name="+1/16" value="0"/>
<value name="+2/16" value="1"/>
<value name="+3/16" value="2"/>
<value name="+4/16" value="3"/>
<value name="+5/16" value="4"/>
<value name="+6/16" value="5"/>
<value name="+7/16" value="6"/>
<value name="+8/16" value="7"/>
</field>
<field name="Round Intra Enable" start="315" end="315" type="bool"/>
<field name="Round Intra" start="312" end="314" type="uint">
<value name="+1/16" value="0"/>
<value name="+2/16" value="1"/>
<value name="+3/16" value="2"/>
<value name="+4/16" value="3"/>
<value name="+5/16" value="4"/>
<value name="+6/16" value="5"/>
<value name="+7/16" value="6"/>
<value name="+8/16" value="7"/>
</field>
<field name="Correct 6" start="308" end="311" type="uint"/>
<field name="Correct 5" start="304" end="307" type="uint"/>
<field name="Correct 4" start="300" end="303" type="uint"/>
<field name="Correct 3" start="296" end="299" type="uint"/>
<field name="Correct 2" start="292" end="295" type="uint"/>
<field name="Correct 1" start="288" end="291" type="uint"/>
<field name="CV7" start="348" end="351" type="uint"/>
<field name="CV6" start="344" end="347" type="uint"/>
<field name="CV5" start="340" end="343" type="uint"/>
<field name="CV4" start="336" end="339" type="uint"/>
<field name="CV3" start="332" end="335" type="uint"/>
<field name="CV2" start="328" end="331" type="uint"/>
<field name="CV1" start="324" end="327" type="uint"/>
<field name="CV0" start="320" end="323" type="uint"/>
</instruction>
<instruction name="MFX_AVC_WEIGHTOFFSET_STATE" bias="2" length="98" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="5"/>
<field name="DWord Length" start="0" end="11" type="uint" default="96"/>
<field name="Weight and Offset Select" start="32" end="32" type="uint">
<value name="L0 table" value="0"/>
<value name="L1 table" value="1"/>
</field>
<group count="96" start="64" size="32">
<field name="Weight Offset" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_BSP_BUF_BASE_ADDR_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="4"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="BSD/MPC Row Store Scratch Buffer - Address" start="38" end="79" type="address"/>
<field name="BSD/MPC Row Store Scratch Buffer - Arbitration Priority Control" start="103" end="104" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="BSD/MPC Row Store Scratch Buffer - Cacheability Control" start="101" end="102" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="BSD/MPC Row Store Scratch Buffer - Target Cache" start="99" end="100" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="BSD/MPC Row Store Scratch Buffer - Age for QUADLRU" start="96" end="97" type="uint"/>
<field name="MPR Row Store Scratch Buffer - Address" start="134" end="175" type="address"/>
<field name="MPR Row Store Scratch Buffer - Arbitration Priority Control" start="199" end="200" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MPR Row Store Scratch Buffer - Cacheability Control" start="197" end="198" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="MPR Row Store Scratch Buffer - Target Cache" start="195" end="196" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="MPR Row Store Scratch Buffer - Age for QUADLRU" start="192" end="193" type="uint"/>
<field name="Bitplane Read Buffer - Address" start="230" end="271" type="uint"/>
<field name="Bitplane Read Buffer - Arbitration Priority Control" start="295" end="296" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Bitplane Read Buffer - Cacheability Control" start="293" end="294" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence (if coherent cycle)" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Bitplane Read Buffer - Target Cache" start="291" end="292" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Bitplane Read Buffer - Age for QUADLRU" start="288" end="289" type="uint"/>
</instruction>
<instruction name="MFX_DBK_OBJECT" bias="2" length="13" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="11"/>
<field name="Pre Deblocking Source - Address" start="38" end="79" type="address"/>
<field name="Pre Deblocking Source - Arbitration Priority Control" start="103" end="104" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Pre Deblocking Source - Cacheability Control" start="101" end="102" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Pre Deblocking Source - Target Cache" start="99" end="100" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Pre Deblocking Source - Age for QUADLRU" start="96" end="97" type="uint"/>
<field name="Deblocking Control - Address" start="134" end="175" type="address"/>
<field name="Deblocking Control - Arbitration Priority Control" start="199" end="200" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Deblocking Control - Cacheability Control" start="197" end="198" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Deblocking Control - Target Cache" start="195" end="196" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Deblocking Control - Age for QUADLRU" start="192" end="193" type="uint"/>
<field name="Deblocking Destination - Address" start="230" end="271" type="address"/>
<field name="Deblocking Destination - Arbitration Priority Control" start="295" end="296" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Deblocking Destination - Cacheability Control" start="293" end="294" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Deblocking Destination - Target Cache" start="291" end="292" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Deblocking Destination - Age for QUADLRU" start="288" end="289" type="uint"/>
<field name="Deblock Row Store - Address" start="326" end="367" type="address"/>
<field name="Deblock Row Store - Arbitration Priority Control" start="391" end="392" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Deblock Row Store - Cacheability Control" start="389" end="390" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Deblock Row Store - Target Cache" start="387" end="388" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="Deblock Row Store - Age for QUADLRU" start="384" end="385" type="uint"/>
</instruction>
<instruction name="MFX_FQM_STATE" bias="2" length="34" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="32"/>
<field name="AVC" start="32" end="33" type="uint">
<value name="AVC_4x4_Intra_MATRIX" value="0"/>
<value name="AVC_4x4_Inter_MATRIX" value="1"/>
<value name="AVC_8x8_Intra_MATRIX" value="2"/>
<value name="AVC_8x8_Inter_MATRIX" value="3"/>
</field>
<field name="MPEG2" start="32" end="33" type="uint">
<value name="MPEG_INTRA_QUANTIZER_MATRIX" value="0"/>
<value name="MPEG_NON_INTRA_QUANTIZER_MATRIX" value="1"/>
</field>
<field name="Forward Quantizer Matrix" start="64" end="1087" type="uint"/>
</instruction>
<instruction name="MFX_IND_OBJ_BASE_ADDR_STATE" bias="2" length="26" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="3"/>
<field name="DWord Length" start="0" end="11" type="uint" default="24"/>
<field name="MFX Indirect Bitstream Object - Address" start="32" end="95" type="address"/>
<field name="MFX Indirect Bitstream Object - Attributes" start="96" end="127" type="MEMORYADDRESSATTRIBUTES"/>
<field name="MFX Indirect Bitstream Object - Upper Bound" start="128" end="191" type="address"/>
<field name="MFX Indirect MV Object - Address" start="192" end="255" type="address"/>
<field name="MFX Indirect MV Object - Attributes" start="256" end="287" type="MEMORYADDRESSATTRIBUTES"/>
<field name="MFX Indirect MV Object - Upper Bound" start="288" end="351" type="address"/>
<field name="MFD Indirect IT-COEFF Object - Address" start="352" end="415" type="address"/>
<field name="MFD Indirect IT-COEFF Object - Attributes" start="416" end="447" type="MEMORYADDRESSATTRIBUTES"/>
<field name="MFD Indirect IT-COEFF Object - Upper Bound" start="448" end="511" type="address"/>
<field name="MFD Indirect IT-DBLK Object - Address" start="512" end="575" type="address"/>
<field name="MFD Indirect IT-DBLK Object - Attributes" start="576" end="607" type="MEMORYADDRESSATTRIBUTES"/>
<field name="MFD Indirect IT-DBLK Object - Upper Bound" start="608" end="671" type="address"/>
<field name="MFC Indirect PAK-BSE Object - Address" start="672" end="735" type="address"/>
<field name="MFC Indirect PAK-BSE Object - Attributes" start="736" end="767" type="MEMORYADDRESSATTRIBUTES"/>
<field name="MFC Indirect PAK-BSE Object - Upper Bound" start="768" end="831" type="address"/>
</instruction>
<instruction name="MFX_JPEG_HUFF_TABLE_STATE" bias="2" length="831" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="7"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="829"/>
<field name="Huffman Table ID" start="32" end="32" type="uint"/>
<group count="12" start="64" size="8">
<field name="DC_BITS" start="0" end="7" type="uint"/>
</group>
<group count="12" start="160" size="8">
<field name="DC_HUFFVAL" start="0" end="7" type="uint"/>
</group>
<group count="16" start="256" size="8">
<field name="AC_BITS" start="0" end="15" type="uint"/>
</group>
<group count="160" start="384" size="8">
<field name="AC_HUFFVAL" start="0" end="7" type="uint"/>
</group>
<group count="2" start="1664" size="8">
<field name="AC_HUFFVAL2" start="0" end="7" type="uint"/>
</group>
</instruction>
<instruction name="MFX_JPEG_PIC_STATE" bias="2" length="3" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="7"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="1"/>
<field name="Vertical Up-Sampling Enable" start="52" end="52" type="bool"/>
<field name="Horizontal Down-Sampling Enable" start="50" end="50" type="bool"/>
<field name="Vertical Down-Sampling Enable" start="49" end="49" type="bool"/>
<field name="Average Down Sampling" start="48" end="48" type="uint"/>
<field name="Output Format YUV" start="40" end="43" type="uint"/>
<field name="Rotation" start="36" end="37" type="uint"/>
<field name="Input Format YUV" start="32" end="34" type="uint"/>
<field name="Frame Height In Blocks" start="80" end="92" type="uint"/>
<field name="Frame Width In Blocks" start="64" end="76" type="uint"/>
</instruction>
<instruction name="MFX_MPEG2_PIC_STATE" bias="2" length="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="F_code[1][1]" start="60" end="63" type="uint"/>
<field name="F_code[1][0]" start="56" end="59" type="uint"/>
<field name="F_code[0][1]" start="52" end="55" type="uint"/>
<field name="F_code[0][0]" start="48" end="51" type="uint"/>
<field name="Intra DC Precision" start="46" end="47" type="uint"/>
<field name="Picture Structure" start="44" end="45" type="uint">
<value name="MPEG_TOP_FIELD" value="1"/>
<value name="MPEG_BOTTOM_FIELD" value="2"/>
<value name="MPEG_FRAME" value="3"/>
</field>
<field name="Top Field First" start="43" end="43" type="bool"/>
<field name="Frame Prediction Frame DCT" start="42" end="42" type="uint"/>
<field name="Concealment MV" start="41" end="41" type="bool"/>
<field name="Quantizer Scale Type" start="40" end="40" type="uint">
<value name="MPEG_QSCALE_LINEAR" value="0"/>
<value name="MPEG_QSCALE_NONLINEAR" value="1"/>
</field>
<field name="Intra VLC Format" start="39" end="39" type="uint"/>
<field name="Scan Order" start="38" end="38" type="uint">
<value name="MPEG_ZIGZAG_SCAN" value="0"/>
<value name="MPEG_ALTERNATE_VERTICAL_SCAN" value="1"/>
</field>
<field name="I Slice Concealment Mode" start="95" end="95" type="uint" prefix="MPEG2_CM">
<value name="Intra Concealment" value="0"/>
<value name="Inter Concealment" value="1"/>
</field>
<field name="P/B Slice Concealment Mode" start="92" end="93" type="uint" prefix="MPEG2_CM">
<value name="INTER" value="0"/>
<value name="LEFT" value="1"/>
<value name="ZERO" value="2"/>
<value name="INTRA" value="3"/>
</field>
<field name="P/B Slice Predicted Bi-direction MV Type Override" start="89" end="90" type="uint" prefix="MPEG2_MVTO">
<value name="BID" value="0"/>
<value name="RESERVED" value="1"/>
<value name="FWD" value="2"/>
<value name="BWD" value="3"/>
</field>
<field name="P/B Slice Predicted MV Override" start="88" end="88" type="uint">
<value name="Predicted" value="0"/>
<value name="ZERO" value="1"/>
</field>
<field name="Load Bitstream Pointer Per Slice" start="78" end="78" type="bool"/>
<field name="Picture Coding Type" start="73" end="74" type="uint">
<value name="MPEG_I_PICTURE" value="1"/>
<value name="MPEG_P_PICTURE" value="2"/>
<value name="MPEG_B_PICTURE" value="3"/>
</field>
<field name="Mismatch Control Disable" start="65" end="65" type="bool"/>
<field name="Disable Mismatch" start="64" end="64" type="bool"/>
<field name="Slice Concealment Disable" start="127" end="127" type="bool"/>
<field name="Frame Height In MBs" start="112" end="119" type="uint"/>
<field name="Frame Width In MBs" start="96" end="103" type="uint"/>
<field name="Minimum Frame Size" start="144" end="159" type="uint"/>
<field name="Round Inter AC," start="140" end="142" type="uint"/>
<field name="Round Intra AC" start="136" end="138" type="uint"/>
<field name="Round Inter DC" start="132" end="134" type="uint"/>
<field name="Round Intra DC" start="129" end="130" type="uint"/>
<field name="Frame Size Control" start="176" end="176" type="uint"/>
<field name="Inter MB Force CBP to Zero Control" start="172" end="172" type="uint"/>
<field name="Minimum Frame Size Units" start="170" end="171" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="16 bytes" value="1"/>
<value name="4Kb" value="2"/>
<value name="16Kb" value="3"/>
</field>
<field name="MBRateControlMask" start="169" end="169" type="uint"/>
<field name="Frame Bitrate Min Report" start="163" end="163" type="uint"/>
<field name="Frame Bitrate Max Report" start="162" end="162" type="uint"/>
<field name="Inter MB Max Bit Control" start="161" end="161" type="uint"/>
<field name="Intra MB Max Bit Control" start="160" end="160" type="uint"/>
<field name="Inter MB Conformance Max Size" start="208" end="219" type="uint"/>
<field name="Intra MB Conformance Max Size" start="192" end="203" type="uint"/>
<field name="Slice Delta QP Max[3]" start="280" end="287" type="int"/>
<field name="Slice Delta QP Max[2]" start="272" end="279" type="int"/>
<field name="Slice Delta QP Max[1]" start="264" end="271" type="int"/>
<field name="Slice Delta QP Max[0]" start="256" end="263" type="int"/>
<field name="Slice Delta QP Min[3]" start="312" end="319" type="int"/>
<field name="Slice Delta QP Min[2]" start="304" end="311" type="int"/>
<field name="Slice Delta QP Min[1]" start="296" end="303" type="int"/>
<field name="Slice Delta QP Min[0]" start="288" end="295" type="int"/>
<field name="Frame Bitrate Max Unit" start="351" end="351" type="uint"/>
<field name="Frame Bitrate Max Unit Mode" start="350" end="350" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="New mode" value="1"/>
</field>
<field name="Frame Bitrate Max" start="336" end="349" type="uint"/>
<field name="Frame Bitrate Min Unit" start="335" end="335" type="uint"/>
<field name="Frame Bitrate Min Unit Mode" start="334" end="334" type="uint">
<value name="Compatibility mode" value="0"/>
<value name="New Mode" value="1"/>
</field>
<field name="Frame Bitrate Min" start="320" end="333" type="uint"/>
<field name="Frame Bitrate Max Delta" start="368" end="382" type="uint"/>
<field name="Frame Bitrate Min Delta" start="352" end="366" type="uint"/>
</instruction>
<instruction name="MFX_PAK_INSERT_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="Data Byte Offset" start="48" end="49" type="uint"/>
<field name="Header Length Excluded From Size" start="47" end="47" type="uint">
<value name="NO_ACCUMULATION" value="1"/>
<value name="ACCUMULATE" value="0"/>
</field>
<field name="Slice Header Indicator" start="46" end="46" type="uint">
<value name="SLICE_HEADER" value="1"/>
<value name="LEGACY" value="0"/>
</field>
<field name="Data Bits In Last DW" start="40" end="45" type="uint"/>
<field name="Skip Emulation Byte Count" start="36" end="39" type="uint"/>
<field name="Emulation Byte Bits Insert Enable" start="35" end="35" type="bool"/>
<field name="Last Header" start="34" end="34" type="bool"/>
<field name="End of Slice" start="33" end="33" type="bool"/>
<field name="Bitstream Start Reset" start="32" end="32" type="bool"/>
<group count="0" start="64" size="32">
<field name="Insert Data PayLoad" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_PIPE_BUF_ADDR_STATE" bias="2" length="61" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="59"/>
<field name="Pre Deblocking Destination - Address" start="38" end="79" type="address"/>
<field name="Pre Deblocking Destination - Arbitration Priority Control" start="103" end="104" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Pre Deblocking Destination - MOCS" start="96" end="102" type="uint"/>
<field name="Post Deblocking Destination - Address" start="134" end="175" type="address"/>
<field name="Post Deblocking Destination - Arbitration Priority Control" start="199" end="200" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Post Deblocking Destination - MOCS" start="192" end="198" type="uint"/>
<field name="Original Uncompressed Picture Source - Address" start="230" end="271" type="address"/>
<field name="Original Uncompressed Picture Source - Arbitration Priority Control" start="295" end="296" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Original Uncompressed Picture Source - MOCS" start="288" end="294" type="uint"/>
<field name="Stream-Out Data Destination - Address" start="326" end="367" type="address"/>
<field name="Stream-Out Data Destination - Arbitration Priority Control" start="391" end="392" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Stream-Out Data Destination - MOCS" start="384" end="390" type="uint"/>
<field name="Intra Row Store Scratch Buffer - Address High" start="422" end="463" type="address"/>
<field name="Intra Row Store Scratch Buffer - Arbitration Priority Control" start="487" end="488" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Intra Row Store Scratch Buffer - MOCS" start="480" end="486" type="uint"/>
<field name="Deblocking Filter Row Store Scratch - Address High" start="518" end="559" type="address"/>
<field name="Deblocking Filter Row Store Scratch - Arbitration Priority Control" start="583" end="584" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Deblocking Filter Row Store Scratch - MOCS" start="576" end="582" type="uint"/>
<group count="16" start="608" size="64">
<field name="Reference Picture - Address" start="0" end="63" type="address"/>
</group>
<field name="Reference Picture - Arbitration Priority Control" start="1639" end="1640" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Reference Picture - MOCS" start="1632" end="1638" type="uint"/>
<field name="MB Status Buffer - Address" start="1670" end="1711" type="address"/>
<field name="MB Status Buffer - Arbitration Priority Control" start="1735" end="1736" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MB Status Buffer - MOCS" start="1728" end="1734" type="uint"/>
<field name="MB ILDB Stream-Out Buffer - Address" start="1766" end="1807" type="address"/>
<field name="MB ILDB Stream-Out Buffer - Arbitration Priority Control" start="1831" end="1832" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MB ILDB Stream-Out Buffer - MOCS" start="1824" end="1830" type="uint"/>
<field name="Second MB ILDB Stream-Out Buffer - Address High" start="1862" end="1903" type="address"/>
<field name="Second MB ILDB Stream-Out Buffer - Arbitration Priority Control" start="1927" end="1928" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Second MB ILDB Stream-Out Buffer - MOCS" start="1920" end="1926" type="uint"/>
</instruction>
<instruction name="MFX_PIPE_MODE_SELECT" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="3"/>
<field name="Extended Stream-Out Enable" start="50" end="50" type="bool"/>
<field name="Decoder Short Format Mode" start="49" end="49" type="uint">
<value name="Short Format Driver Interface" value="0"/>
<value name="Long Format Driver Interface" value="1"/>
</field>
<field name="Decoder Mode select" start="47" end="48" type="uint">
<value name="VLD Mode" value="0"/>
<value name="IT Mode" value="1"/>
<value name="Deblocker Mode" value="2"/>
<value name="Interlayer Mode" value="3"/>
</field>
<field name="Deblocker Stream-Out Enable" start="44" end="44" type="bool"/>
<field name="Pic Error/Status Report Enable" start="43" end="43" type="bool"/>
<field name="Stream-Out Enable" start="42" end="42" type="bool"/>
<field name="Post Deblocking Output Enable" start="41" end="41" type="bool"/>
<field name="Pre Deblocking Output Enable" start="40" end="40" type="bool"/>
<field name="Stitch Mode" start="37" end="37" type="bool"/>
<field name="Codec Select" start="36" end="36" type="uint">
<value name="Decode" value="0"/>
<value name="Encode" value="1"/>
</field>
<field name="Standard Select" start="32" end="35" type="uint" prefix="SS">
<value name="MPEG2" value="0"/>
<value name="VC1" value="1"/>
<value name="AVC" value="2"/>
<value name="JPEG" value="3"/>
<value name="VP8" value="5"/>
<value name="UVLD" value="15"/>
</field>
<field name="Pic Status/Error Report ID" start="96" end="127" type="uint"/>
</instruction>
<instruction name="MFX_QM_STATE" bias="2" length="34" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="7"/>
<field name="DWord Length" start="0" end="11" type="uint" default="32"/>
<field name="AVC" start="32" end="33" type="uint">
<value name="AVC_4x4_Intra_MATRIX" value="0"/>
<value name="AVC_4x4_Inter_MATRIX" value="1"/>
<value name="AVC_8x8_Intra_MATRIX" value="2"/>
<value name="AVC_8x8_Inter_MATRIX" value="3"/>
</field>
<field name="MPEG2" start="32" end="33" type="uint">
<value name="MPEG_INTRA_QUANTIZER_MATRIX" value="0"/>
<value name="MPEG_NON_INTRA_QUANTIZER_MATRIX" value="1"/>
</field>
<field name="Forward Quantizer Matrix" start="64" end="1087" type="uint"/>
</instruction>
<instruction name="MFX_STATE_POINTER" bias="2" length="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="6"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="State Pointer" start="37" end="63" type="uint"/>
<field name="State Pointer Index" start="32" end="33" type="uint"/>
</instruction>
<instruction name="MFX_STITCH_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="10"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="Source Data Starting Byte Offset" start="48" end="49" type="uint"/>
<field name="Source Data Ending Bit Inclusion" start="40" end="45" type="uint"/>
<field name="Last Header" start="34" end="34" type="bool"/>
<field name="End of Slice" start="33" end="33" type="bool"/>
<field name="Indirect Data Length" start="64" end="82" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="offset"/>
<group count="0" start="128" size="32">
<field name="Insert Data PayLoad" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_SURFACE_STATE" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Surface ID" start="32" end="35" type="uint">
<value name="Source Input Picture" value="4"/>
<value name="Reconstructed Scaled Reference Picture" value="5"/>
</field>
<field name="Height" start="82" end="95" type="uint"/>
<field name="Width" start="68" end="81" type="uint"/>
<field name="Cr(V)/Cb(U) Pixel Offset V Direction" start="64" end="65" type="u0.2"/>
<field name="Surface Format" start="124" end="127" type="uint">
<value name="YCRCB_NORMAL" value="0"/>
<value name="YCRCB_SWAPUVY" value="1"/>
<value name="YCRCB_SWAPUV" value="2"/>
<value name="YCRCB_SWAPY" value="3"/>
<value name="PLANAR_420_8" value="4"/>
<value name="PLANAR_411_8" value="5"/>
<value name="PLANAR_422_8" value="6"/>
<value name="STMM_DN_STATISTICS" value="7"/>
<value name="R10G10B10A2_UNORM" value="8"/>
<value name="R8G8B8A8_UNORM" value="9"/>
<value name="R8B8_UNORM (CrCb)" value="10"/>
<value name="R8_UNORM (Cr/Cb)" value="11"/>
<value name="Y8_UNORM" value="12"/>
</field>
<field name="Interleave Chroma" start="123" end="123" type="bool"/>
<field name="Surface Pitch" start="99" end="115" type="uint"/>
<field name="Half Pitch for Chroma" start="98" end="98" type="bool"/>
<field name="Tiled Surface" start="97" end="97" type="bool"/>
<field name="Tile Walk" start="96" end="96" type="uint" prefix="TW">
<value name="XMAJOR" value="0"/>
<value name="YMAJOR" value="1"/>
</field>
<field name="X Offset for U(Cb)" start="144" end="158" type="uint"/>
<field name="Y Offset for U(Cb)" start="128" end="142" type="uint"/>
<field name="X Offset for V(Cr)" start="176" end="188" type="uint"/>
<field name="Y Offset for V(Cr)" start="160" end="175" type="uint"/>
</instruction>
<instruction name="MFX_VC1_DIRECTMODE_STATE" bias="2" length="7" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="5"/>
<field name="Direct MV Write Buffer - Address" start="32" end="95" type="address"/>
<field name="Direct MV Write Buffer - Attributes" start="96" end="127" type="MEMORYADDRESSATTRIBUTES"/>
<field name="Direct MV Read Buffer - Address" start="128" end="191" type="address"/>
<field name="Direct MV Read Buffer - Attributes" start="192" end="223" type="MEMORYADDRESSATTRIBUTES"/>
</instruction>
<instruction name="MFX_VC1_PRED_PIPE_STATE" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Vin_intensitycomp_Double_FWDen" start="46" end="47" type="uint"/>
<field name="Vin_intensitycomp_Double_BWDen" start="44" end="45" type="uint"/>
<field name="Vin_intensitycomp_Single_FWDen" start="42" end="43" type="uint"/>
<field name="Vin_intensitycomp_Single_BWDen" start="40" end="41" type="uint"/>
<field name="Reference Frame Boundary Replication Mode" start="36" end="39" type="uint"/>
<field name="LumShift2 - single - FWD" start="88" end="93" type="uint"/>
<field name="LumShift1 - single - FWD" start="80" end="85" type="uint"/>
<field name="LumScale2 - single - FWD" start="72" end="77" type="uint"/>
<field name="LumScale1 - single - FWD" start="64" end="69" type="uint"/>
<field name="LumShift2 - double - FWD" start="120" end="125" type="uint"/>
<field name="LumShift1 - double - FWD" start="112" end="117" type="uint"/>
<field name="LumScale2 - double - FWD" start="104" end="109" type="uint"/>
<field name="LumScale1 - double - FWD" start="96" end="101" type="uint"/>
<field name="LumShift2 - single - BWD" start="152" end="157" type="uint"/>
<field name="LumShift1 - single - BWD" start="144" end="149" type="uint"/>
<field name="LumScale2 - single - BWD" start="136" end="141" type="uint"/>
<field name="LumScale1 - single - BWD" start="128" end="133" type="uint"/>
<field name="LumShift2 - double - BWD" start="184" end="189" type="uint"/>
<field name="LumShift1 - double - BWD" start="176" end="181" type="uint"/>
<field name="LumScale2 - double - BWD" start="168" end="173" type="uint"/>
<field name="LumScale1 - double - BWD" start="160" end="165" type="uint"/>
</instruction>
<instruction name="MFX_VP8_PAK_OBJECT" bias="2" length="7" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="4"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="5"/>
<field name="Indirect PAK-MV Data Length" start="32" end="41" type="uint"/>
<field name="Indirect PAK-MV Data Start Address Offset" start="64" end="92" type="offset"/>
<field name="Inline Data" start="96" end="223" type="uint"/>
</instruction>
<instruction name="MFX_VP8_PIC_STATE" bias="2" length="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command OpCode" start="24" end="26" type="uint" default="4"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="Frame Height" start="48" end="55" type="uint"/>
<field name="Frame Width" start="32" end="39" type="uint"/>
<field name="Log2 Num of Partition" start="88" end="89" type="uint">
<value name="1 Token partition" value="0"/>
<value name="2 Token partition" value="1"/>
<value name="4 Token partition" value="2"/>
<value name="8 Token partition" value="3"/>
</field>
<field name="Deblock Sharpness Level" start="80" end="82" type="uint"/>
<field name="Alternate Ref Pic MV Sign Bias" start="77" end="77" type="bool"/>
<field name="Golden Ref Picture MV Sign Bias" start="76" end="76" type="bool"/>
<field name="Mode Reference Loop Filter Delta Enable" start="75" end="75" type="bool"/>
<field name="MB NoCoeff Skip" start="74" end="74" type="bool"/>
<field name="Update MB Segment Map" start="73" end="73" type="bool"/>
<field name="Segment Enable" start="72" end="72" type="bool"/>
<field name="Segmentation ID Stream-In Enable" start="71" end="71" type="bool"/>
<field name="Segmentation ID Stream-Out Enable" start="70" end="70" type="bool"/>
<field name="Key Frame" start="69" end="69" type="bool"/>
<field name="DBLK Filter Type" start="68" end="68" type="uint"/>
<field name="Chroma Full Pixel MC Filter Mode" start="65" end="65" type="uint"/>
<field name="MC Filter Select" start="64" end="64" type="uint"/>
<field name="DBLK Filter Level for Segment3" start="120" end="125" type="uint"/>
<field name="DBLK Filter Level for Segment2" start="112" end="117" type="uint"/>
<field name="DBLK Filter Level for Segment1" start="104" end="109" type="uint"/>
<field name="DBLK Filter Level for Segment0" start="96" end="101" type="uint"/>
<field name="Quantizer Value [0][Y1AC]" start="144" end="152" type="uint"/>
<field name="Quantizer Value [0][Y1DC]" start="128" end="136" type="uint"/>
<field name="Quantizer Value [0][UVAC]" start="176" end="184" type="uint"/>
<field name="Quantizer Value [0][UVDC]" start="160" end="168" type="uint"/>
<field name="Quantizer Value [0][Y2AC]" start="208" end="216" type="uint"/>
<field name="Quantizer Value [0][Y2DC]" start="192" end="200" type="uint"/>
<field name="Quantizer Value [1][Y1AC]" start="240" end="248" type="uint"/>
<field name="Quantizer Value [1][Y1DC]" start="224" end="232" type="uint"/>
<field name="Quantizer Value [1][UVAC]" start="272" end="280" type="uint"/>
<field name="Quantizer Value [1][UVDC]" start="256" end="264" type="uint"/>
<field name="Quantizer Value [1][Y2AC]" start="304" end="312" type="uint"/>
<field name="Quantizer Value [1][Y2DC]" start="288" end="296" type="uint"/>
<field name="Quantizer Value [2][Y1AC]" start="336" end="344" type="uint"/>
<field name="Quantizer Value [2][Y1DC]" start="320" end="328" type="uint"/>
<field name="Quantizer Value [2][UVAC]" start="368" end="376" type="uint"/>
<field name="Quantizer Value [2][UVDC]" start="352" end="360" type="uint"/>
<field name="Quantizer Value [2][Y2AC]" start="400" end="408" type="uint"/>
<field name="Quantizer Value [2][Y2DC]" start="384" end="392" type="uint"/>
<field name="Quantizer Value [3][Y1AC]" start="432" end="440" type="uint"/>
<field name="Quantizer Value [3][Y1DC]" start="416" end="424" type="uint"/>
<field name="Quantizer Value [3][UVAC]" start="464" end="472" type="uint"/>
<field name="Quantizer Value [3][UVDC]" start="448" end="456" type="uint"/>
<field name="Quantizer Value [3][Y2AC]" start="496" end="504" type="uint"/>
<field name="Quantizer Value [3][Y2DC]" start="480" end="488" type="uint"/>
<field name="CoeffProbability Stream-In - Address" start="518" end="559" type="address"/>
<field name="CoeffProbability Stream-In - Arbitration Priority Control" start="583" end="584" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="CoeffProbability Stream-In - Cacheability Control" start="581" end="582" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="CoeffProbability Stream-In - Target Cache" start="579" end="580" type="uint">
<value name="eLLC Only" value="0"/>
<value name="LLC Only" value="1"/>
<value name="LLC/eLLC" value="2"/>
<value name="L3, LLC, eLLC" value="3"/>
</field>
<field name="CoeffProbability Stream-In - Age for QUADLRU" start="576" end="577" type="uint"/>
<field name="MBSegmentIDTreeProbs[2]" start="624" end="631" type="uint"/>
<field name="MBSegmentIDTreeProbs[1]" start="616" end="623" type="uint"/>
<field name="MBSegmentIDTreeProbs[0]" start="608" end="615" type="uint"/>
<field name="MBNoCoeffSkipFalseProb" start="664" end="671" type="uint"/>
<field name="IntraMBProb" start="656" end="663" type="uint"/>
<field name="InterPredFromLastRefProb" start="648" end="655" type="uint"/>
<field name="InterPredFromGRefRefProb" start="640" end="647" type="uint"/>
<field name="YModeProb[3]" start="696" end="703" type="uint"/>
<field name="YModeProb[2]" start="688" end="695" type="uint"/>
<field name="YModeProb[1]" start="680" end="687" type="uint"/>
<field name="YModeProb[0]" start="672" end="679" type="uint"/>
<field name="UVModeProb[2]" start="720" end="727" type="uint"/>
<field name="UVModeProb[1]" start="712" end="719" type="uint"/>
<field name="UVModeProb[0]" start="704" end="711" type="uint"/>
<field name="MVUpdateProbs[0][3]" start="760" end="767" type="uint"/>
<field name="MVUpdateProbs[0][2]" start="752" end="759" type="uint"/>
<field name="MVUpdateProbs[0][1]" start="744" end="751" type="uint"/>
<field name="MVUpdateProbs[0][0]" start="736" end="743" type="uint"/>
<field name="MVUpdateProbs[0][7]" start="792" end="799" type="uint"/>
<field name="MVUpdateProbs[0][6]" start="784" end="791" type="uint"/>
<field name="MVUpdateProbs[0][5]" start="776" end="783" type="uint"/>
<field name="MVUpdateProbs[0][4]" start="768" end="775" type="uint"/>
<field name="MVUpdateProbs[0][11]" start="824" end="831" type="uint"/>
<field name="MVUpdateProbs[0][10]" start="816" end="823" type="uint"/>
<field name="MVUpdateProbs[0][9]" start="808" end="815" type="uint"/>
<field name="MVUpdateProbs[0][8]" start="800" end="807" type="uint"/>
<field name="MVUpdateProbs[0][15]" start="856" end="863" type="uint"/>
<field name="MVUpdateProbs[0][14]" start="848" end="855" type="uint"/>
<field name="MVUpdateProbs[0][13]" start="840" end="847" type="uint"/>
<field name="MVUpdateProbs[0][12]" start="832" end="839" type="uint"/>
<field name="MVUpdateProbs[0][18]" start="880" end="887" type="uint"/>
<field name="MVUpdateProbs[0][17]" start="872" end="879" type="uint"/>
<field name="MVUpdateProbs[0][16]" start="864" end="871" type="uint"/>
<field name="MVUpdateProbs[1][3]" start="920" end="927" type="uint"/>
<field name="MVUpdateProbs[1][2]" start="912" end="919" type="uint"/>
<field name="MVUpdateProbs[1][1]" start="904" end="911" type="uint"/>
<field name="MVUpdateProbs[1][0]" start="896" end="903" type="uint"/>
<field name="MVUpdateProbs[1][7]" start="952" end="959" type="uint"/>
<field name="MVUpdateProbs[1][6]" start="944" end="951" type="uint"/>
<field name="MVUpdateProbs[1][5]" start="936" end="943" type="uint"/>
<field name="MVUpdateProbs[1][4]" start="928" end="935" type="uint"/>
<field name="MVUpdateProbs[1][11]" start="984" end="991" type="uint"/>
<field name="MVUpdateProbs[1][10]" start="976" end="983" type="uint"/>
<field name="MVUpdateProbs[1][9]" start="968" end="975" type="uint"/>
<field name="MVUpdateProbs[1][8]" start="960" end="967" type="uint"/>
<field name="MVUpdateProbs[1][15]" start="1016" end="1023" type="uint"/>
<field name="MVUpdateProbs[1][14]" start="1008" end="1015" type="uint"/>
<field name="MVUpdateProbs[1][13]" start="1000" end="1007" type="uint"/>
<field name="MVUpdateProbs[1][12]" start="992" end="999" type="uint"/>
<field name="MVUpdateProbs[1][18]" start="1040" end="1047" type="uint"/>
<field name="MVUpdateProbs[1][17]" start="1032" end="1039" type="uint"/>
<field name="MVUpdateProbs[1][16]" start="1024" end="1031" type="uint"/>
<field name="RefLFDelta3" start="1080" end="1086" type="int"/>
<field name="RefLFDelta2" start="1072" end="1078" type="int"/>
<field name="RefLFDelta1" start="1064" end="1070" type="int"/>
<field name="RefLFDelta0" start="1056" end="1062" type="int"/>
<field name="ModeLFDelta3" start="1112" end="1118" type="int"/>
<field name="ModeLFDelta2" start="1104" end="1110" type="int"/>
<field name="ModeLFDelta1" start="1096" end="1102" type="int"/>
<field name="ModeLFDelta0" start="1088" end="1094" type="int"/>
<field name="Segmentation ID Stream - Address" start="1120" end="1167" type="uint"/>
<field name="Segmentation ID Stream - Arbitration Priority Control" start="1191" end="1192" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Segmentation ID Stream - Cacheability Control" start="1189" end="1190" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Segmentation ID Stream - Target Cache" start="1187" end="1188" type="uint">
<value name="Use Cacheability Controls From Page Table / UC with Fence" value="0"/>
<value name="Uncacheable" value="1"/>
<value name="Writethrough" value="2"/>
<value name="Writeback" value="3"/>
</field>
<field name="Segmentation ID Stream - Age for QUADLRU" start="1184" end="1185" type="uint"/>
</instruction>
<instruction name="MFX_WAIT" bias="1" length="1" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command Subtype" start="27" end="28" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="26" type="uint" default="0"/>
<field name="MFX Sync Control Flag" start="8" end="8" type="uint"/>
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
</instruction>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<instruction name="MI_ARB_CHECK" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
intel: genxml: add preemption control instructions Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2018-03-27 17:56:44 +01:00
<instruction name="MI_ARB_ON_OFF" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
<field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
</instruction>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>
<field name="Memory Type" start="22" end="22" type="uint">
<value name="Per Process Graphics Address" value="0"/>
<value name="Global Graphics Address" value="1"/>
</field>
<field name="Post-Sync Operation" start="21" end="21" type="bool"/>
<field name="Data Size" start="19" end="20" type="uint">
<value name="DWORD" value="0"/>
<value name="QWORD" value="1"/>
<value name="OCTWORD" value="2"/>
<value name="RESERVED" value="3"/>
</field>
<field name="Inline Data" start="18" end="18" type="uint"/>
<field name="CS STALL" start="17" end="17" type="uint"/>
<field name="Return Data Control" start="16" end="16" type="uint"/>
<field name="ATOMIC OPCODE" start="8" end="15" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Memory Address" start="34" end="79" type="address"/>
<field name="Operand1 Data Dword 0" start="96" end="127" type="uint"/>
<field name="Operand2 Data Dword 0" start="128" end="159" type="uint"/>
<field name="Operand1 Data Dword 1" start="160" end="191" type="uint"/>
<field name="Operand2 Data Dword 1" start="192" end="223" type="uint"/>
<field name="Operand1 Data Dword 2" start="224" end="255" type="uint"/>
<field name="Operand2 Data Dword 2" start="256" end="287" type="uint"/>
<field name="Operand1 Data Dword 3" start="288" end="319" type="uint"/>
<field name="Operand2 Data Dword 3" start="320" end="351" type="uint"/>
</instruction>
<instruction name="MI_BATCH_BUFFER_END" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="10"/>
</instruction>
<instruction name="MI_BATCH_BUFFER_START" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="49"/>
intel: decoder: unify MI_BB_START field naming The batch decoder looks for a field with a particular name to decide whether an MI_BB_START leads into a second batch buffer level. Because the names are different between Gen7.5/8 and the newer generation we fail that test and keep on reading (invalid) instructions. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107544 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-14 11:22:12 +01:00
<field name="Second Level Batch Buffer" start="22" end="22" type="uint">
<value name="First level batch" value="0"/>
<value name="Second level batch" value="1"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</field>
<field name="Add Offset Enable" start="16" end="16" type="bool"/>
intel/genxml: Make "Predication enable" a boolean Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:58:06 -07:00
<field name="Predication Enable" start="15" end="15" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Resource Streamer Enable" start="10" end="10" type="bool"/>
<field name="Address Space Indicator" start="8" end="8" type="uint" prefix="ASI">
<value name="GGTT" value="0"/>
<value name="PPGTT" value="1"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Batch Buffer Start Address" start="34" end="79" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_CLFLUSH" bias="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="39"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="9" type="uint" default="1"/>
<field name="Page Base Address" start="44" end="79" type="address"/>
<field name="Starting Cacheline Offset" start="38" end="43" type="uint"/>
<group count="0" start="96" size="32">
<field name="DW Representing a Half Cache Line" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MI_CONDITIONAL_BATCH_BUFFER_END" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="54"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Compare Semaphore" start="21" end="21" type="uint" default="0"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Compare Data Dword" start="32" end="63" type="uint"/>
<field name="Compare Address" start="67" end="111" type="address"/>
</instruction>
<instruction name="MI_COPY_MEM_MEM" bias="2" length="5">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="46"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT Source" start="22" end="22" type="bool"/>
<field name="Use Global GTT Destination" start="21" end="21" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<field name="Destination Memory Address" start="34" end="95" type="address"/>
<field name="Source Memory Address" start="98" end="159" type="address"/>
</instruction>
intel/genxml: Media instructions and structures for gen8 v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com> - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:54:25 +02:00
<instruction name="MI_FLUSH_DW" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="38"/>
<field name="Store Data Index" start="21" end="21" type="uint"/>
<field name="TLB Invalidate" start="18" end="18" type="bool"/>
<field name="Post-Sync Operation" start="14" end="15" type="uint"/>
<field name="Notify Enable" start="8" end="8" type="bool"/>
<field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
<field name="DWord Length" start="0" end="5" type="uint"/>
<field name="Address" start="35" end="79" type="address"/>
<field name="Destination Address Type" start="34" end="34" type="uint" prefix="DAT">
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="Immediate Data" start="96" end="159" type="uint"/>
</instruction>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
intel: genxml: decode variable length MI_LRI MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2018-04-03 11:21:31 +01:00
<group count="0" start="64" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="41"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Register Address" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
<instruction name="MI_LOAD_REGISTER_REG" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Source Register Address" start="34" end="54" type="offset"/>
<field name="Destination Register Address" start="66" end="86" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="19"/>
<field name="Display (Plane) Select" start="19" end="21" type="uint">
<value name="Display Plane A" value="0"/>
<value name="Display Plane B" value="1"/>
<value name="Display Plane C" value="4"/>
</field>
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
<field name="Start Scan Line Number" start="48" end="60" type="uint"/>
<field name="End Scan Line Number" start="32" end="44" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_LOAD_SCAN_LINES_INCL" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="18"/>
<field name="Display (Plane) Select" start="19" end="21" type="uint">
<value name="Display Plane A" value="0"/>
<value name="Display Plane B" value="1"/>
<value name="Display Plane C" value="4"/>
</field>
intel/genxml: Fix some more fake booleans in genxml. None of these are actually booleans. Tile Parameter is a tiling mode enum. Display pipes take plane numbers. Predicate Enable has some operations (and the default value of 6 was particular bogus). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-05-07 11:40:24 -07:00
<field name="Scan Line Event Done Forward" start="17" end="18" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
<field name="Start Scan Line Number" start="48" end="60" type="uint"/>
<field name="End Scan Line Number" start="32" end="44" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_LOAD_URB_MEM" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="44"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="URB Address" start="34" end="46" type="uint"/>
<field name="Memory Address" start="70" end="127" type="address"/>
</instruction>
<instruction name="MI_MATH" bias="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="26"/>
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
genxml: Add better support for MI_MATH This breaks the guts of MI_MATH (the instruction part) out into its own structure with proper named values. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed by: Iago Toral Quiroga <itoral@igalia.com>
2017-04-19 16:21:08 -07:00
<group count="0" start="32" size="32">
<field name="Instruction" start="0" end="31" type="MI_MATH_ALU_INSTRUCTION"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</group>
</instruction>
<instruction name="MI_NOOP" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="0"/>
<field name="Identification Number Register Write Enable" start="22" end="22" type="bool"/>
<field name="Identification Number" start="0" end="21" type="uint"/>
</instruction>
<instruction name="MI_PREDICATE" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="12"/>
<field name="Load Operation" start="6" end="7" type="uint" prefix="LOAD">
<value name="KEEP" value="0"/>
<value name="LOAD" value="2"/>
<value name="LOADINV" value="3"/>
</field>
<field name="Combine Operation" start="3" end="4" type="uint" prefix="COMBINE">
<value name="SET" value="0"/>
<value name="AND" value="1"/>
<value name="OR" value="2"/>
<value name="XOR" value="3"/>
</field>
<field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
intel/genxml: add missing MI_PREDICATE compare operations Doesn't save us a great deal of lines but at least they get decoded in aubinators. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-01-18 16:12:06 +00:00
<value name="TRUE" value="0"/>
<value name="FALSE" value="1"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<value name="SRCS_EQUAL" value="2"/>
<value name="DELTAS_EQUAL" value="3"/>
</field>
</instruction>
<instruction name="MI_REPORT_HEAD" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="7"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_REPORT_PERF_COUNT" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="40"/>
<field name="DWord Length" start="0" end="5" type="uint" default="2"/>
<field name="Memory Address" start="38" end="95" type="address"/>
<field name="Core Mode Enable" start="36" end="36" type="uint"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="32" end="32" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Report ID" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_RS_CONTEXT" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="15"/>
<field name="Resource Streamer Save" start="0" end="0" type="uint" prefix="RS">
<value name="Restore" value="0"/>
<value name="Save" value="1"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_RS_CONTROL" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="6"/>
<field name="Resource Streamer Control" start="0" end="0" type="uint" prefix="RS">
<value name="Stop" value="0"/>
<value name="Start" value="1"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_RS_STORE_DATA_IMM" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="43"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Destination Address" start="34" end="95" type="address"/>
<field name="Core Mode Enable" start="32" end="32" type="uint"/>
<field name="Data DWord 0" start="96" end="127" type="uint"/>
</instruction>
<instruction name="MI_SEMAPHORE_SIGNAL" bias="2" length="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="27"/>
<field name="Post-Sync Operation" start="21" end="21" type="bool"/>
<field name="Target Engine Select" start="15" end="17" type="uint">
<value name="RCS" value="0"/>
<value name="VCS0" value="1"/>
<value name="BCS" value="2"/>
<value name="VECS" value="3"/>
<value name="VCS1" value="4"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Target Context ID" start="32" end="63" type="uint"/>
</instruction>
<instruction name="MI_SEMAPHORE_WAIT" bias="2" length="4">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="28"/>
<field name="Memory Type" start="22" end="22" type="uint">
<value name="Per Process Graphics Address" value="0"/>
<value name="Global Graphics Address" value="1"/>
</field>
<field name="Wait Mode" start="15" end="15" type="uint">
<value name="Polling Mode" value="1"/>
<value name="Signal Mode" value="0"/>
</field>
<field name="Compare Operation" start="12" end="14" type="uint" prefix="COMPARE">
<value name="SAD_GREATER_THAN_SDD" value="0"/>
<value name="SAD_GREATER_THAN_OR_EQUAL_SDD" value="1"/>
<value name="SAD_LESS_THAN_SDD" value="2"/>
<value name="SAD_LESS_THAN_OR_EQUAL_SDD" value="3"/>
<value name="SAD_EQUAL_SDD" value="4"/>
<value name="SAD_NOT_EQUAL_SDD" value="5"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Semaphore Data Dword" start="32" end="63" type="uint"/>
<field name="Semaphore Address" start="66" end="95" type="address"/>
<field name="Semaphore Address High" start="96" end="111" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_SET_CONTEXT" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="24"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Logical Context Address" start="44" end="63" type="address"/>
<field name="Reserved, Must be 1" start="40" end="40" type="uint"/>
<field name="Core Mode Enable" start="36" end="36" type="bool"/>
<field name="Resource Streamer State Save Enable" start="35" end="35" type="bool"/>
<field name="Resource Streamer State Restore Enable" start="34" end="34" type="bool"/>
<field name="Force Restore" start="33" end="33" type="uint"/>
<field name="Restore Inhibit" start="32" end="32" type="uint"/>
</instruction>
<instruction name="MI_SET_PREDICATE" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="1"/>
<field name="PREDICATE ENABLE" start="0" end="3" type="uint">
<value name="NOOP Never" value="0"/>
<value name="NOOP on Result2 clear" value="1"/>
<value name="NOOP on Result2 set" value="2"/>
<value name="NOOP on Result clear" value="3"/>
<value name="NOOP on Result set" value="4"/>
<value name="Execute when one slice enabled." value="5"/>
<value name="Execute when two slices are enabled." value="6"/>
<value name="Execute when three slices are enabled." value="7"/>
<value name="NOOP Always" value="15"/>
</field>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="4">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="32"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Store Qword" start="21" end="21" type="uint"/>
<field name="DWord Length" start="0" end="9" type="uint" default="2"/>
<field name="Address" start="34" end="79" type="address"/>
<field name="Core Mode Enable" start="32" end="32" type="uint"/>
genxml: Make MI_STORE_DATA_IMM have a single 64-bit data field This is way more convenient than having two separate dword fields. Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-14 16:22:00 -07:00
<field name="Immediate Data" start="96" end="159" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</instruction>
<instruction name="MI_STORE_DATA_INDEX" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="33"/>
<field name="Use Per-Process Hardware Status Page" start="21" end="21" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Offset" start="34" end="43" type="uint"/>
<field name="Data DWord 0" start="64" end="95" type="uint"/>
<field name="Data DWord 1" start="96" end="127" type="uint"/>
</instruction>
<instruction name="MI_STORE_REGISTER_MEM" bias="2" length="4">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="36"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Predicate Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Register Address" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_STORE_URB_MEM" bias="2" length="4" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="45"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="URB Address" start="34" end="46" type="uint"/>
<field name="Memory Address" start="70" end="127" type="address"/>
</instruction>
<instruction name="MI_SUSPEND_FLUSH" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="11"/>
<field name="Suspend Flush" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_TOPOLOGY_FILTER" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="13"/>
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:44:22 -08:00
<field name="Topology Filter Value" start="0" end="5" type="3D_Prim_Topo_Type"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_URB_ATOMIC_ALLOC" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="9"/>
<field name="URB Atomic Storage Offset" start="12" end="19" type="uint"/>
<field name="URB Atomic Storage Size" start="0" end="8" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_URB_CLEAR" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="25"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="URB Clear Length" start="48" end="61" type="uint"/>
<field name="URB Address" start="32" end="46" type="offset"/>
</instruction>
<instruction name="MI_USER_INTERRUPT" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="2"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="MI_WAIT_FOR_EVENT" bias="1" length="1" engine="render|blitter">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="3"/>
<field name="Display Pipe C Vertical Blank Wait Enable" start="21" end="21" type="bool"/>
<field name="Display Sprite C Flip Pending Wait Enable" start="20" end="20" type="bool"/>
<field name="Display Plane C Flip Pending Wait Enable" start="15" end="15" type="bool"/>
<field name="Display Pipe C Scan Line Wait Enable" start="14" end="14" type="bool"/>
<field name="Display Pipe B Vertical Blank Wait Enable" start="11" end="11" type="bool"/>
<field name="Display Sprite B Flip Pending Wait Enable" start="10" end="10" type="bool"/>
<field name="Display Plane B Flip Pending Wait Enable" start="9" end="9" type="bool"/>
<field name="Display Pipe B Scan Line Wait Enable" start="8" end="8" type="bool"/>
<field name="Display Pipe A Vertical Blank Wait Enable" start="3" end="3" type="bool"/>
<field name="Display Sprite A Flip Pending Wait Enable" start="2" end="2" type="bool"/>
<field name="Display Plane A Flip Pending Wait Enable" start="1" end="1" type="bool"/>
<field name="Display Pipe A Scan Line Wait Enable" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="PIPELINE_SELECT" bias="1" length="1" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="1"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="Pipeline Selection" start="0" end="1" type="uint">
<value name="3D" value="0"/>
<value name="Media" value="1"/>
<value name="GPGPU" value="2"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="Destination Address Type" start="56" end="56" type="uint" prefix="DAT">
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="LRI Post Sync Operation" start="55" end="55" type="uint">
<value name="No LRI Operation" value="0"/>
<value name="MMIO Write Immediate Data" value="1"/>
</field>
<field name="Store Data Index" start="53" end="53" type="uint"/>
genxml: Make PIPE_CONTROL::CommandStreamerStallEnable a boolean This has been declared as a uint since SNB but it's only one bit. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-05-20 12:07:53 -07:00
<field name="Command Streamer Stall Enable" start="52" end="52" type="bool"/>
intel/genxml: Make some PIPE_CONTROL fields booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 23:09:38 -07:00
<field name="Global Snapshot Count Reset" start="51" end="51" type="bool"/>
<field name="TLB Invalidate" start="50" end="50" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Generic Media State Clear" start="48" end="48" type="bool"/>
<field name="Post Sync Operation" start="46" end="47" type="uint">
<value name="No Write" value="0"/>
<value name="Write Immediate Data" value="1"/>
<value name="Write PS Depth Count" value="2"/>
<value name="Write Timestamp" value="3"/>
</field>
<field name="Depth Stall Enable" start="45" end="45" type="bool"/>
<field name="Render Target Cache Flush Enable" start="44" end="44" type="bool"/>
<field name="Instruction Cache Invalidate Enable" start="43" end="43" type="bool"/>
<field name="Texture Cache Invalidation Enable" start="42" end="42" type="bool"/>
<field name="Indirect State Pointers Disable" start="41" end="41" type="bool"/>
<field name="Notify Enable" start="40" end="40" type="bool"/>
<field name="Pipe Control Flush Enable" start="39" end="39" type="bool"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="DC Flush Enable" start="37" end="37" type="bool"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="VF Cache Invalidation Enable" start="36" end="36" type="bool"/>
<field name="Constant Cache Invalidation Enable" start="35" end="35" type="bool"/>
<field name="State Cache Invalidation Enable" start="34" end="34" type="bool"/>
<field name="Stall At Pixel Scoreboard" start="33" end="33" type="bool"/>
<field name="Depth Cache Flush Enable" start="32" end="32" type="bool"/>
<field name="Address" start="66" end="111" type="address"/>
<field name="Immediate Data" start="128" end="191" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="STATE_BASE_ADDRESS" bias="2" length="16" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="1"/>
<field name="DWord Length" start="0" end="7" type="uint" default="14"/>
<field name="General State Base Address" start="44" end="95" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="General State MOCS" start="36" end="42" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="General State Base Address Modify Enable" start="32" end="32" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="Stateless Data Port Access MOCS" start="112" end="118" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Surface State Base Address" start="140" end="191" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="Surface State MOCS" start="132" end="138" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Surface State Base Address Modify Enable" start="128" end="128" type="bool"/>
<field name="Dynamic State Base Address" start="204" end="255" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="Dynamic State MOCS" start="196" end="202" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Dynamic State Base Address Modify Enable" start="192" end="192" type="bool"/>
<field name="Indirect Object Base Address" start="268" end="319" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="Indirect Object MOCS" start="260" end="266" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Indirect Object Base Address Modify Enable" start="256" end="256" type="bool"/>
<field name="Instruction Base Address" start="332" end="383" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="Instruction MOCS" start="324" end="330" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Instruction Base Address Modify Enable" start="320" end="320" type="bool"/>
<field name="General State Buffer Size" start="396" end="415" type="uint"/>
<field name="General State Buffer Size Modify Enable" start="384" end="384" type="bool"/>
<field name="Dynamic State Buffer Size" start="428" end="447" type="uint"/>
<field name="Dynamic State Buffer Size Modify Enable" start="416" end="416" type="bool"/>
<field name="Indirect Object Buffer Size" start="460" end="479" type="uint"/>
<field name="Indirect Object Buffer Size Modify Enable" start="448" end="448" type="bool"/>
<field name="Instruction Buffer Size" start="492" end="511" type="uint"/>
<field name="Instruction Buffer size Modify Enable" start="480" end="480" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="STATE_PREFETCH" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Prefetch Pointer" start="38" end="63" type="address"/>
<field name="Prefetch Count" start="32" end="34" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="STATE_SIP" bias="2" length="3" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="System Instruction Pointer" start="36" end="95" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen8) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for MI_TOPOLOGY_FILTER and MI_LOAD_URB_MEM. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:09 +02:00
<instruction name="SWTESS_BASE_ADDRESS" bias="2" length="2" engine="render">
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="SW Tessellation Base Address" start="44" end="79" type="address"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="SW Tessellation MOCS" start="40" end="43" type="uint"/>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</instruction>
genxml: Add pipeline statistics registers on gen7+ Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-15 15:18:21 -07:00
<register name="IA_VERTICES_COUNT" length="2" num="0x2310">
<field name="IA Vertices Count Report" start="0" end="63" type="uint"/>
</register>
<register name="IA_PRIMITIVES_COUNT" length="2" num="0x2318">
<field name="IA Primitives Count Report" start="0" end="63" type="uint"/>
</register>
<register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
<field name="VS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="HS_INVOCATION_COUNT" length="2" num="0x2300">
<field name="HS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="DS_INVOCATION_COUNT" length="2" num="0x2308">
<field name="DS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="GS_INVOCATION_COUNT" length="2" num="0x2328">
<field name="GS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="GS_PRIMITIVES_COUNT" length="2" num="0x2330">
<field name="GS Primitives Count Report" start="0" end="63" type="uint"/>
</register>
<register name="CL_INVOCATION_COUNT" length="2" num="0x2338">
<field name="CL Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="CL_PRIMITIVES_COUNT" length="2" num="0x2340">
<field name="CL Primitives Count Report" start="0" end="63" type="uint"/>
</register>
<register name="PS_INVOCATION_COUNT" length="2" num="0x2348">
<field name="PS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
<register name="CS_INVOCATION_COUNT" length="2" num="0x2290">
<field name="CS Invocation Count Report" start="0" end="63" type="uint"/>
</register>
intel: genxml: add INSTDONE registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 11:58:19 +00:00
<register name="BCS_INSTDONE" length="1" num="0x2206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="Blitter IDLE" start="1" end="1" type="bool" default="1"/>
<field name="GAB IDLE" start="2" end="2" type="bool" default="1"/>
<field name="BCS Done" start="3" end="3" type="bool" default="1"/>
</register>
<register name="INSTDONE_1" length="1" num="0x206c">
<field name="PRB0 Ring Enable" start="0" end="0" type="bool"/>
<field name="VFG Done" start="1" end="1" type="bool"/>
<field name="VS Done" start="2" end="2" type="bool"/>
<field name="HS Done" start="3" end="3" type="bool"/>
<field name="TE Done" start="4" end="4" type="bool"/>
<field name="DS Done" start="5" end="5" type="bool"/>
<field name="GS Done" start="6" end="6" type="bool"/>
<field name="SOL Done" start="7" end="7" type="bool"/>
<field name="CL Done" start="8" end="8" type="bool"/>
<field name="SF Done" start="9" end="9" type="bool"/>
<field name="TDG Done" start="12" end="12" type="bool"/>
<field name="URBM Done" start="13" end="13" type="bool"/>
<field name="SVG Done" start="14" end="14" type="bool"/>
<field name="GAFS Done" start="15" end="15" type="bool"/>
<field name="VFE Done" start="16" end="16" type="bool"/>
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="GAFM Done" start="18" end="18" type="bool"/>
<field name="GAM Done" start="19" end="19" type="bool"/>
genxml: Add missing INSTDONE_1 bits on Gen7.5+. This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-01-07 22:29:34 -08:00
<field name="RS Done" start="20" end="20" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
intel: genxml: add INSTDONE registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 11:58:19 +00:00
<field name="SDE Done" start="22" end="22" type="bool"/>
<field name="RCCFBC CS Done" start="23" end="23" type="bool"/>
</register>
<register name="VCS_INSTDONE" length="1" num="0x1206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="USB Done" start="1" end="1" type="bool"/>
<field name="QRC Done" start="2" end="2" type="bool"/>
<field name="SEC Done" start="3" end="3" type="bool"/>
<field name="MPC Done" start="4" end="4" type="bool"/>
<field name="VFT Done" start="5" end="5" type="bool"/>
<field name="BSP Done" start="6" end="6" type="bool"/>
<field name="VLF Done" start="7" end="7" type="bool"/>
<field name="VOP Done" start="8" end="8" type="bool"/>
<field name="VMC Done" start="9" end="9" type="bool"/>
<field name="VIP Done" start="10" end="10" type="bool"/>
<field name="VIT Done" start="11" end="11" type="bool"/>
<field name="VDS Done" start="12" end="12" type="bool"/>
<field name="VMX Done" start="13" end="13" type="bool"/>
<field name="VCP Done" start="14" end="14" type="bool"/>
<field name="VCD Done" start="15" end="15" type="bool"/>
<field name="VAD Done" start="16" end="16" type="bool"/>
<field name="VMD Done" start="17" end="17" type="bool"/>
<field name="VIS Done" start="18" end="18" type="bool"/>
<field name="VAC Done" start="19" end="19" type="bool"/>
<field name="VAM Done" start="20" end="20" type="bool"/>
<field name="JPG Done" start="21" end="21" type="bool"/>
<field name="VBP Done" start="22" end="22" type="bool"/>
<field name="VHR Done" start="23" end="23" type="bool"/>
<field name="VCI Done" start="24" end="24" type="bool"/>
<field name="VCR Done" start="25" end="25" type="bool"/>
<field name="VIN Done" start="26" end="26" type="bool"/>
<field name="VPR Done" start="27" end="27" type="bool"/>
<field name="VTQ Done" start="28" end="28" type="bool"/>
<field name="Reserved" start="29" end="29" type="bool"/>
<field name="VCS Done" start="30" end="30" type="bool"/>
<field name="GAC Done" start="31" end="31" type="bool"/>
</register>
<register name="VECS_INSTDONE" length="1" num="0x1a06c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="VECS Done" start="30" end="30" type="bool"/>
<field name="GAM Done" start="31" end="31" type="bool"/>
</register>
intel/genxml: Add SC_INSTDONE register. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-03-21 11:42:20 -07:00
<register name="SC_INSTDONE" length="1" num="0x7100">
<field name="SVL Done" start="0" end="0" type="bool"/>
<field name="WMFE Done" start="1" end="1" type="bool"/>
<field name="WMBE Done" start="2" end="2" type="bool"/>
<field name="HIZ Done" start="3" end="3" type="bool"/>
<field name="STC Done" start="4" end="4" type="bool"/>
<field name="IZ Done" start="5" end="5" type="bool"/>
<field name="SBE Done" start="6" end="6" type="bool"/>
<field name="RCZ Done" start="8" end="8" type="bool"/>
<field name="RCC Done" start="9" end="9" type="bool"/>
<field name="RCPBE Done" start="10" end="10" type="bool"/>
<field name="RCPFE Done" start="11" end="11" type="bool"/>
<field name="DAPB Done" start="12" end="12" type="bool"/>
<field name="DAPRBE Done" start="13" end="13" type="bool"/>
<field name="SARB Done" start="15" end="15" type="bool"/>
<field name="DC0 Done" start="16" end="16" type="bool"/>
<field name="DC1 Done" start="17" end="17" type="bool"/>
<field name="DC2 Done" start="18" end="18" type="bool"/>
<field name="GW0 Done" start="20" end="20" type="bool"/>
<field name="GW1 Done" start="21" end="21" type="bool"/>
<field name="GW2 Done" start="22" end="22" type="bool"/>
<field name="TDC Done" start="24" end="24" type="bool"/>
</register>
intel/genxml: Add ROW_INSTDONE register. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-03-21 11:42:21 -07:00
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
intel/genxml: Add SAMPLER_INSTDONE register. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-03-21 11:42:22 -07:00
<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM ARB3" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="BDM Done" start="19" end="19" type="bool"/>
</register>
genxml: Add L3 Cache Control register definitions Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-24 00:29:50 -07:00
<register name="L3CNTLREG" length="1" num="0x7034">
intel/genxml: turn SLM Enable bit into boolean Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-07 11:55:45 +01:00
<field name="SLM Enable" start="0" end="0" type="bool"/>
genxml: Add L3 Cache Control register definitions Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-24 00:29:50 -07:00
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
<field name="All Allocation" start="25" end="31" type="uint"/>
</register>
genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTEN Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-14 14:45:12 -05:00
<register name="SO_NUM_PRIMS_WRITTEN0" length="2" num="0x5200">
<field name="Num Prims Written Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_NUM_PRIMS_WRITTEN1" length="2" num="0x5208">
<field name="Num Prims Written Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_NUM_PRIMS_WRITTEN2" length="2" num="0x5210">
<field name="Num Prims Written Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_NUM_PRIMS_WRITTEN3" length="2" num="0x5218">
<field name="Num Prims Written Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_PRIM_STORAGE_NEEDED0" length="2" num="0x5240">
<field name="Prim Storage Needed Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_PRIM_STORAGE_NEEDED1" length="2" num="0x5248">
<field name="Prim Storage Needed Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_PRIM_STORAGE_NEEDED2" length="2" num="0x5250">
<field name="Prim Storage Needed Count" start="0" end="63" type="uint"/>
</register>
<register name="SO_PRIM_STORAGE_NEEDED3" length="2" num="0x5258">
<field name="Prim Storage Needed Count" start="0" end="63" type="uint"/>
</register>
intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9 Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-10-18 19:02:07 -07:00
<register name="SO_WRITE_OFFSET0" length="1" num="0x5280">
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
<register name="SO_WRITE_OFFSET1" length="1" num="0x5284">
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
<register name="SO_WRITE_OFFSET2" length="1" num="0x5288">
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
<register name="SO_WRITE_OFFSET3" length="1" num="0x528c">
<field name="Write Offset" start="2" end="31" type="offset"/>
</register>
genxml: Add the CACHE_MODE_1 register on gen8 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-12-06 17:51:26 -08:00
<register name="CACHE_MODE_1" length="1" num="0x7004">
<field name="RCZ Read after expansion control fix 2" start="2" end="2" type="bool"/>
<field name="Depth Read Hit Write-Only Optimization Disable" start="3" end="3" type="bool"/>
<field name="MCS Cache Disable" start="5" end="5" type="bool"/>
<field name="4X4 RCPFE-STC Optimization Disable" start="6" end="6" type="bool"/>
<field name="Sampler Cache Set XOR selection" start="7" end="8" type="uint"/>
<field name="NP PMA Fix Enable" start="11" end="11" type="uint"/>
<field name="HIZ Eviction Policy" start="12" end="12" type="uint"/>
<field name="NP Early Z Fails Disable" start="13" end="13" type="uint"/>
<field name="MSC Resolve Optimization Disable" start="14" end="14" type="uint"/>
<field name="RCZ Read after expansion control fix 2 Mask" start="18" end="18" type="bool"/>
<field name="Depth Read Hit Write-Only Optimization Disable Mask" start="19" end="19" type="bool"/>
<field name="MCS Cache Disable Mask" start="21" end="21" type="bool"/>
<field name="4X4 RCPFE-STC Optimization Disable Mask" start="22" end="22" type="bool"/>
<field name="Sampler Cache Set XOR selection Mask" start="23" end="24" type="uint"/>
<field name="NP PMA Fix Enable Mask" start="27" end="27" type="uint"/>
<field name="HIZ Eviction Policy Mask" start="28" end="28" type="uint"/>
<field name="NP Early Z Fails Disable Mask" start="29" end="29" type="uint"/>
<field name="MSC Resolve Optimization Disable Mask" start="30" end="30" type="uint"/>
</register>
intel: genxml: add GFX_ARB_ERROR_RPT register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 15:38:20 +00:00
<register name="GFX_ARB_ERROR_RPT" length="1" num="0x40a0">
<field name="TLB Page Fault Error" start="0" end="0" type="bool"/>
<field name="RSTRM PAVP Read Invalid" start="1" end="1" type="bool"/>
<field name="Invalid Page Directory Entry Error" start="2" end="2" type="bool"/>
<field name="ROSTRM PAVP Invalid Physical Address" start="3" end="3" type="bool"/>
<field name="TLB Page VTD Translation Error" start="4" end="4" type="bool"/>
<field name="WRDP PAVP Invalid" start="5" end="5" type="bool"/>
<field name="Page Directory Entry VTD Translation Error" start="6" end="6" type="bool"/>
<field name="Unloaded PD Error" start="8" end="8" type="bool"/>
<field name="GuC VTd translation Page Fault 2nd level (Undefined doorbell)" start="9" end="9" type="bool"/>
<field name="Non WB memory type for Advanced Context" start="10" end="10" type="bool"/>
<field name="PASID Not Enabled" start="11" end="11" type="bool"/>
<field name="PASID Boundary Violation" start="12" end="12" type="bool"/>
<field name="PASID Not Valid" start="13" end="13" type="bool"/>
<field name="PASID Was Zero For Untranslated Request" start="14" end="14" type="bool"/>
<field name="Context Was Not Marked As Present When Doing DMA" start="15" end="15" type="bool"/>
</register>
intel: genxml: add ACTHD registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 15:38:43 +00:00
<register name="ACTHD_UDW" length="1" num="0x205c">
<field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
</register>
<register name="BCS_ACTHD_UDW" length="1" num="0x2205c">
<field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
</register>
<register name="VCS_ACTHD_UDW" length="1" num="0x1205c">
<field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
</register>
<register name="VECS_ACTHD_UDW" length="1" num="0x1a05c">
<field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
</register>
intel: genxml: add FAULT_REG register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 14:27:53 +00:00
<register name="FAULT_REG" length="1" num="0x4094">
<field name="Valid Bit" start="0" end="0" type="bool"/>
<field name="Fault Type" start="1" end="2" type="uint">
<value name="Invalid PTE Fault" value="0"/>
<value name="Invalid PDE Fault" value="1"/>
<value name="Invalid PDPE Fault" value="2"/>
<value name="Invalid PML4E Fault" value="3"/>
</field>
<field name= "SRCID of Fault" start="3" end="10" type="uint"/>
<field name="GTTSEL" start="11" end="11" type="uint">
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="Engine ID" start="12" end="14" type="uint">
<value name="GFX" value="0"/>
<value name="MFX0" value="1"/>
<value name="MFX1" value="2"/>
<value name="VEBX" value="3"/>
<value name="BLT" value="4"/>
<value name="GUC" value="5"/>
</field>
</register>
intel: genxml: add RING_BUFFER_CTL registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 17:27:01 +00:00
<register name="BCS_RING_BUFFER_CTL" length="1" num="0x2203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="RCS_RING_BUFFER_CTL" length="1" num="0x203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="VECS_RING_BUFFER_CTL" length="1" num="0x1A03c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="VCS_RING_BUFFER_CTL" length="1" num="0x1203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="VCS2_RING_BUFFER_CTL" length="1" num="0x1203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-03-02 16:44:14 +00:00
<register name="INSTPM" length="1" num="0x20c0">
<field name="3D State Instruction Disable" start="1" end="1" type="bool"/>
<field name="3D Rendering Instruction Disable" start="2" end="2" type="bool"/>
<field name="Media Instruction Disable" start="3" end="3" type="bool"/>
<field name="CONSTANT_BUFFER Address Offset Disable" start="6" end="6" type="bool"/>
intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-06-15 11:43:45 -07:00
<field name="3D State Instruction Disable Mask" start="17" end="17" type="bool"/>
<field name="3D Rendering Instruction Disable Mask" start="18" end="18" type="bool"/>
<field name="Media Instruction Disable Mask" start="19" end="19" type="bool"/>
<field name="CONSTANT_BUFFER Address Offset Disable Mask" start="22" end="22" type="bool"/>
intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-03-02 16:44:14 +00:00
</register>
anv: Generate pack headers from XML definition This huge commit switches us over to using a simple xml format (genxml) for defining our command streamer commands and a python script for generating the pack headers we use in the driver.
2016-02-08 16:21:09 -08:00
</genxml>
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