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intel: genxml: decode variable length MI_LRI

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MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one
command. In our drivers we only use one tuple at a time, but the
kernel might load more than one at a time.

Instead of making all the tuple part of a group, we leave out the
first tuple (the one we use in the generated packing structures).

This is particularly useful for looking at error stats generated by
the kernel.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
This commit is contained in:
Lionel Landwerlin 2018-04-03 11:21:31 +01:00
parent 2841af6238
commit 4d59127213
10 changed files with 40 additions and 0 deletions
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4
src/intel/genxml/gen10.xml
View file

@ -2969,6 +2969,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

4
src/intel/genxml/gen11.xml
View file

@ -2956,6 +2956,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

4
src/intel/genxml/gen4.xml
View file

@ -860,6 +860,10 @@
<field name="DWord Length" start="0" end="5" type="uint" default="1"/>
<field name="Register Offset" start="34" end="63" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="31" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

4
src/intel/genxml/gen45.xml
View file

@ -890,6 +890,10 @@
<field name="DWord Length" start="0" end="5" type="uint" default="1"/>
<field name="Register Offset" start="34" end="63" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="31" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

4
src/intel/genxml/gen5.xml
View file

@ -974,6 +974,10 @@
<field name="DWord Length" start="0" end="5" type="uint" default="1"/>
<field name="Register Offset" start="34" end="63" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="31" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

4
src/intel/genxml/gen6.xml
View file

@ -1531,6 +1531,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">

4
src/intel/genxml/gen7.xml
View file

@ -2020,6 +2020,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">

4
src/intel/genxml/gen75.xml
View file

@ -2380,6 +2380,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">

4
src/intel/genxml/gen8.xml
View file

@ -2607,6 +2607,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="64" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

4
src/intel/genxml/gen9.xml
View file

@ -2894,6 +2894,10 @@
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
</instruction>
<instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">