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837 commits

Author SHA1 Message Date
Ilya Zlobintsev
369990d966 amdgpu: update marketing names for strix point revisions 2025-12-19 15:41:40 +02:00
Simon Ser
6bfcfc725f build: bump version to 2.4.131
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-12-11 22:17:34 +01:00
Sergio Costas Rodriguez
64ef303d70
amdgpu: NetBSD lacks secure_getenv
When adding support for defining extra paths for the `amdgpu.ids`
file using an environment variable, the patch used a call to
secure_getenv(), which is only available in GNU. This breaks the
build in NetBSD systems.

This patch adds conditional compilation to use secure_getenv()
only when compiling against the GNU libraries.

Fix c3c7fb21aa (note_3229411)

Signed-off-by: Sergio Costas Rodriguez <sergio.costas@canonical.com>
2025-12-11 15:41:39 +01:00
Samuel Pitoiset
b7861fb536 amdgpu: add Steam Machine marketing name
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2025-12-11 08:52:33 +01:00
Simon Ser
523534ee01 build: bump version to 2.4.130
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-12-08 14:15:17 +01:00
Simon Ser
1b68532f88 Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.

Generated using make headers_install
Generated from drm-next branch commit 0692602defb0c273f80dec9c564ca50726404aca

Signed-off-by: Simon Ser <contact@emersion.fr>
2025-12-08 13:09:09 +00:00
Val Packett
bef7c6fcf1 headers: drm: Sync virtgpu_drm.h with Linux v6.16
The header shipped with libdrm was missing blob resources, context_init,
syncobj support, and capset definitions.

Update to the current version from Linux, which was last modified in 6.16.

Signed-off-by: Val Packett <val@invisiblethingslab.com>
2025-12-07 20:06:56 -03:00
Andrew Davis
b71953a199 omap: fix omap_bo_size for tiled buffers
The buffer size is calculated using pixels, not bytes as it should. The
result is often correct, though, as the stride is aligned to page size,
but there are still many cases where the size ends up being wrong.

Fix this by not calculating the size at all, as in that case
DRM_OMAP_GEM_INFO ioctl is used to get the correct size from the kernel.
This is better in any case as then the userspace library doesn't need to
know how the tiled buffers need to be aligned.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
2025-12-04 09:39:10 +00:00
Sergio Costas Rodriguez
d72d7c6eef
amdgpu: Fix envar name in documentation
After a change in the patch, the environment variable name for
the `amdgpu.ids` file paths changed to plurar form, but the
documentation wasn't updated.

This patch fixes it.
2025-12-03 10:53:38 +01:00
Sergio Costas Rodriguez
a050f86ed8
Support multiple paths in AMDGPU_ASIC_ID_TABLE_PATH envar
This patch allows to specify several colon-separated paths where
to search for the `amdgpu.ids` file in the AMDGPU_ASIC_ID_TABLE_PATH
environment variable.
2025-12-02 17:03:09 +01:00
Sergio Costas Rodriguez
c3c7fb21aa
amdgpu: add env support for amdgpu.ids path
In some cases, like when building a Snap application that uses
libdrm, the `amdgpu.ids` file isn't directly available at the
compiling place, but inside a mounted folder. This forces each
application to link/bind the file from the current place
(usually at the $SNAP/gnome-platform/usr/share/libdrm/amdgpu.ids)
which is cumbersome.

This patch allows to set an environment variable, called
AMDGPU_ASIC_ID_TABLE_PATH, where the file will be also searched
if it isn't located in the default, meson-configured, path.
2025-12-02 17:02:39 +01:00
Simon Ser
a8e5e10a87 build: bump version to 2.4.128
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-11-17 16:17:12 +01:00
Simon Ser
31e68ea81c Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.

Generated using make headers_install
Generated from drm-next branch commit 2a084f4ad727244768b919455aa9dc1c04630487

Signed-off-by: Simon Ser <contact@emersion.fr>
2025-11-16 20:45:03 +01:00
Alex Deucher
35a21916c8 amdgpu: update marketing names
https://www.amd.com/en/products/graphics/desktops/radeon/7000-series/amd-radeon-rx-7700.html
https://www.amd.com/en/products/graphics/desktops/radeon/9000-series/amd-radeon-rx-9060.html
https://www.amd.com/en/products/accelerators/instinct/mi350/mi350x.html
https://www.amd.com/en/products/accelerators/instinct/mi350/mi355x.html

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-10 14:37:06 -05:00
Samuel Pitoiset
3968028058 amdgpu: update marketing names
https://www.amd.com/en/products/graphics/desktops/radeon/9000-series/amd-radeon-rx-9060xt.html

Closes: https://gitlab.freedesktop.org/mesa/libdrm/-/issues/120
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2025-11-03 09:43:51 +01:00
Marek Olšák
679c474974 Bump version to 2.4.128 2025-11-01 22:30:31 -04:00
Marek Olšák
7816984a20 Revert ABI breakage "drm/amdgpu: Add user queue HQD count to hw_ip info"
This reverts commit e4bd1ba753.

Such a change of ABI is illegal and causes crashes. See:
https://gitlab.freedesktop.org/mesa/libdrm/-/issues/121#note_3172362
2025-11-01 22:14:40 -04:00
Christian König
aaf8a893e1 test/amdgpu: remove amdgpu unit tests
Those haven't been updated in the last two years and have been replaced by
IGT test cases: https://gitlab.freedesktop.org/drm/igt-gpu-tools

Signed-off-by: Christian König <christian.koenig@amd.com>
2025-10-27 07:32:56 +00:00
Mario Limonciello
871e326ac7 amdgpu: Only read /proc/cpuinfo as a fallback
Some older Vega APUs don't provide a very useful string. If we have
a string in amdgpu.ids use that, but fallback to /proc/cpuinfo.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
2025-10-22 03:08:52 +00:00
Mario Limonciello (AMD)
90656fc8e4 amdgpu: Slice and dice the string for APUs
The string will generally have a CPU and GPU component, so if both
are found split it up.  Make sure that it starts with AMD to be
consistent.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
2025-10-22 03:08:52 +00:00
Jesse.Zhang
7518cc4fdd amdgpu: Add parameter validation to amdgpu_bo functions to fix SIGSEGV
This commit adds essential parameter validation to several key
functions in amdgpu_bo.c to prevent null pointer dereferences
that were causing segmentation faults and improve overall code
robustness.

The changes address the following crash scenario:
Received signal SIGSEGV.
Stack trace:
 #0 [fatal_sig_handler+0x17b]
 #1 [__sigaction+0x50]
 #2 [amdgpu_bo_alloc+0x37]
 #3 [__igt_unique____real_main461+0x7d5]
 #4 [main+0x2d]
 #5 [__libc_init_first+0x90]
 #6 [__libc_start_main+0x80]
 #7 [_start+0x25]

Changes made:

1. amdgpu_bo_alloc():
   - Validate alloc_buffer and buf_handle parameters
   - Return -EINVAL if either is NULL
   - Prevents null pointer dereference in memset and subsequent operations

2. amdgpu_bo_set_metadata():
   - Validate info parameter
   - Return -EINVAL if info is NULL
   - Prevents accessing invalid metadata structure

3. amdgpu_bo_query_info():
   - Validate info parameter in addition to existing bo->handle check
   - Return -EINVAL if info is NULL
   - Prevents writing to invalid info pointer

4. amdgpu_bo_list_create():
   - Validate resources parameter
   - Return -EINVAL if resources is NULL when number_of_resources > 0
   - Prevents invalid memory access during resource array processing

These changes ensure proper error handling when callers pass invalid
null pointers, preventing potential segmentation faults and making
the API more robust against programming errors. The validation occurs
early in each function to minimize performance impact.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
2025-10-22 08:59:55 +08:00
Mario Limonciello
2c1d39eff8 amdgpu: Read model name from /proc/cpuinfo for APUs
The correct marketing name is encoded in the model name field
that is read from the hardware on an APU.  Try to read from /proc/cpuinfo
when an APU is found to identify such hardware.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
2025-10-15 09:20:59 -05:00
Simon Ser
f7013effc3 build: bump version to 2.4.127
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-10-14 18:44:17 +02:00
Vlad Zahorodnii
7a325ad150 xf86drm: Drop drmFauxDeviceInfo
Its contents is the same as drmFauxBusInfo. While it is technically an
API breaking change, libdrm with the relevant changes has been released
only recently and there are issues with quering DRM nodes that are on
the faux bus, which result in crashes, so it is unlikely that there are
users that depend on the new API.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
2025-10-14 19:38:10 +03:00
Vlad Zahorodnii
1e9b50f1d5 xf86drm: Fix drmDevicesEqual() for nodes on the faux bus
The name string is allocated on the heap, so the memcmp() function will
not return 0 even though two nodes share the same device name.

Also, the device info will not be populated when counting the available
drm devices. For example, using drmGetDevices2(0, NULL, 0). In that
case, drmGetDevices2() will eventually crash in drmDevicesEqual() while
merging nodes belonging to the same device due to passing null pointers
to memcmp().

This change adds faux device name to businfo. The businfo is populated
regardless whether device info is needed, which is needed to make the
drmGetDevices2(0, NULL, 0) case work. drmFauxBusInfo can also be used
with the memcmp() function to match the other cases in drmDevicesEqual().

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
2025-10-14 19:38:10 +03:00
Vlad Zahorodnii
0a5e2c96b1 xf86drm: Trim traling whitespace in xf86drm.h
This prevents text editors that trim trailing whitespace automatically
from making unrelated changes.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
2025-10-14 19:38:03 +03:00
Simon Ser
22d70b6a8f build: bump version to 2.4.126
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-10-01 15:59:46 +02:00
Alex Deucher
7d43d9b6fe amdgpu: update marketing names
https://www.amd.com/zh-cn/products/graphics/desktops/radeon/9000-series/amd-radeon-rx-9070-gre.html
https://www.amd.com/en/products/graphics/workstations/radeon-ai-pro/ai-9000-series/amd-radeon-ai-pro-r9700.html

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-08-11 09:52:25 -04:00
José Expósito
d870a12c3a xf86drm: Add faux bus
Linux 6.14 included a new type of bus, the "faux" bus [1].

The next version of Linux (v6.16) will move the VKMS driver to the faux
bus. See kernel commit 5686601908d8 ("drm/vkms: convert to use
faux_device") for more details.

Add support for the faux bus so drmGetDeviceFromDevId(), drmGetDevices()
and drmGetDevices2() return the devices on it.

[1] https://lore.kernel.org/all/2025021023-sandstorm-precise-9f5d@gregkh/
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
2025-08-01 11:22:18 +02:00
Huang Rui
9ea8a8e93d modetest: fix build error on is_power_of_two()
The inline function is_power_of_two should be set as static since it's
only called in pattern.c, otherwise it will encounter below build error.

[114/136] Linking target tests/modetest/modetest
FAILED: tests/modetest/modetest
cc  -o tests/modetest/modetest tests/modetest/modetest.p/buffers.c.o tests/modetest/modetest.p/cursor.c.o tests/modetest/modetest.p/modetest.c.o -Wl,--as-needed -Wl,--no-undefined -fno-omit-frame-pointer '-Wl,-rpath,$ORIGIN/../..' -Wl,-rpath-link,/home/ray/repo/drm/build/ -Wl,--start-group libdrm.so.2.125.0 tests/util/libutil.a -lm -pthread /usr/lib/x86_64-linux-gnu/libcairo.so -Wl,--end-group
/usr/bin/ld: tests/util/libutil.a.p/pattern.c.o: in function `check_yuv':
/home/ray/repo/drm/build/../tests/util/pattern.c:1989: undefined reference to `is_power_of_two'
/usr/bin/ld: /home/ray/repo/drm/build/../tests/util/pattern.c:1990: undefined reference to `is_power_of_two'
/usr/bin/ld: /home/ray/repo/drm/build/../tests/util/pattern.c:1991: undefined reference to `is_power_of_two'
collect2: error: ld returned 1 exit status

Signed-off-by: Huang Rui <ray.huang@amd.com>
2025-07-14 14:45:14 +08:00
Jesse.Zhang
e4bd1ba753 drm/amdgpu: Add user queue HQD count to hw_ip info
Add a new field userq_num_hqds to drm_amdgpu_info_hw_ip to expose the
number of available hardware queue descriptors (HQDs) for user queues.
This allows userspace to query the maximum number of user queues that
can be created for a particular IP block.

the patch link in driver side:
https://lists.freedesktop.org/archives/amd-gfx/2025-June/126686.html
https://lists.freedesktop.org/archives/amd-gfx/2025-July/126981.html

v2: rename userq_num_hqds to userq_num_slots (Marek)

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2025-07-09 09:40:34 +08:00
Emil Svendsen
289175512c modetest: util: add seed argument for noise patterns
Add seed argument for modetest noise patterns. If no seed is provided
the current time will be used as seed.

The used seed will be printed so the noise pattern can be reproduced.

Signed-off-by: Emil Svendsen <emas@bang-olufsen.dk>
2025-06-09 09:31:02 +02:00
Emil Svendsen
40aeab6fd5 modetest: util: pattern: add new patterns
Add three new test patterns:

- noise: random black and white pixels
- noise-color: random color pixels
- black-white: alternate between black and white pixels

These patterns are useful for measuring radiated emissions for EMC
compliance tests.

Signed-off-by: Emil Svendsen <emas@bang-olufsen.dk>
2025-06-09 09:25:29 +02:00
Simon Ser
76a1e97a9a build: bump version to 2.4.125
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-06-08 14:27:53 +02:00
Simon Ser
3ba6183b79 Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.

Generated using make headers_install.
Generated from drm-next branch commit 04c8970771b4f1f39bb8453a2eeb188c4d5edbd6

Signed-off-by: Simon Ser <contact@emersion.fr>
2025-06-08 14:22:46 +02:00
Simon Ser
fa6f0fbad7 Switch URLs to mesa/libdrm
The GitLab repository has been renamed.

Signed-off-by: Simon Ser <contact@emersion.fr>
References: https://gitlab.freedesktop.org/mesa/drm/-/issues/74
2025-06-08 12:16:36 +00:00
Simon Ser
dccb4b18e2 ci: fix arm32v7 Debian container preparation
buildah tried to pull the arm64 variant of the arm32v7/debian:bookworm
container:

 * choosing an image from manifest list docker://arm32v7/debian:bookworm: no image found in image index for architecture "arm64", variant "v8", OS "linux"

Signed-off-by: Simon Ser <contact@emersion.fr>
2025-05-22 16:05:30 +02:00
Simon Ser
c3a4c985d5 ci: upgrade FreeBSD to version 14.2
py39-docutils doesn't exist in the package repositories, likely
because the Python version has been upgraded. Let's not hardcode
the Python version in the package name.

Signed-off-by: Simon Ser <contact@emersion.fr>
2025-05-22 16:05:30 +02:00
Simon Ser
e9a886f859 ci: upgrade ci-templates to latest commit
Signed-off-by: Simon Ser <contact@emersion.fr>
2025-05-22 16:05:25 +02:00
Corentin Noël
a0fbf455fa meson: Do not check for meson version >=0.54
Meson version 0.59 is already required.
2025-05-20 11:05:27 +02:00
Alex Deucher
b65d6ede3e amdgpu: update marketing names
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-plus-395.html
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-390.html
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-385.html
https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-max-pro-300-series/amd-ryzen-ai-max-pro-380.html
https://www.amd.com/en/products/graphics/desktops/radeon/9000-series/amd-radeon-rx-9070.html
https://www.amd.com/en/products/graphics/desktops/radeon/9000-series/amd-radeon-rx-9070xt.html
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-5-340.html
https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-7-350.html

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-05 16:49:52 -04:00
Sunil Khatri
614f8d7391 drm/amdgpu: add UAPI to query if user queues are supported
add uapi support for user queues query inline with kernel
changes.

https://lists.freedesktop.org/archives/amd-gfx/2025-April/122559.html

Reviewed-by: Marek Olšák marek.olsak@amd.com
Reviewed-by: Yogesh Mohan Marimuthu yogesh.mohanmarimuthu@amd.com
Reviewed-by: Alex Deucher alexander.deucher@amd.com
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
2025-04-30 18:56:07 +05:30
Arunpravin Paneer Selvam
15e174c1ed amdgpu: Add queue id support to the user queue wait IOCTL
Add queue id support to the user queue wait IOCTL
drm_amdgpu_userq_wait structure.

This is required to retrieve the wait user queue and maintain
the fence driver references in it so that the user queue in
the same context releases their reference to the fence drivers
at some point before queue destruction.

Otherwise, we would gather those references until we
don't have any more space left and crash.

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2025-04-18 20:51:59 +05:30
Jie1zhang
fdf384d4b5 amdgpu: Add queue priority and secure flags support for user queues
This patch extends the user queue creation API to support:
1. Queue priority levels (normal low, low, normal high, high)
   - High priority is restricted to admin-only
2. Secure queue flag for protected content access

The changes include:
- Adding a `flags` parameter to `amdgpu_create_userqueue()`
- Defining priority and security flags in `amdgpu_drm.h`
- Updating the `drm_amdgpu_userq_in` struct to replace padding with flags
- Documenting the new flags field

Related driver patches provided by Alex:
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122782.html
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122780.html
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122786.html

Cc: Koenig, Christian <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>

Signed-off-by: Jesse.Zhang <Jesse.zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2025-04-14 15:37:51 +08:00
Arvind Yadav
43e8a3f86a amdgpu: Add amdgpu userqueue IOCTL functions
This patch adds new IOCTL functions to support
userqueue create, remove, signal and wait etc.

v2:(Marek)
 - Add csa support for SDMA queue.
 - Addressed's review comments.
 - Removed raw2/op2 ioctl.
 - Added syncobj_timeline_handles in amdgpu_userq_wait IOCTL.

v3:(Yogesh)
 - Rename timeline* objects as per UAPI review (Arvind).

v4: (Marek)
 - Drop AMDGPU_USERQ_BO_WRITE as this should not be a global option
   of the IOCTL, It should be option per buffer. Hence adding separate
   array for read and write BO handles. (Arun)

 - Modify num_fences to __u16, flags changed to __u16 and placed
   the num_fences next to flags for optimal padding and size. (Arun)

v5:(Marek/Pierre-Eric)
  - add more detail params description for signal and wait IOCTL calls.
  - Remove the unused structure fields in signal and wait structs.
  - Add separate array of read and write for BO handles. (Arun)

  - Removes the unused flags parameter from the
	amdgpu_create_userqueue IOCTL. (Arvind)

v6:(Pierre-Eric)
  - Remove unused headers. (Arvind)

  - Modify the function parameter names and struct
    field names as per the review comments. (Arun)

v7:(Marek)
  - Modify the structure field name and comments. (Arun)

  - Rename vm_timeline_syncobj and add comment for
    vm_timeline_point.
  - Remove GDS buffer support from MQD. (Arvind)

v8:(Pierre-Eric)
  - Modify the function parameter names.
  - Added new function in amdgpu-symbols.txt (Arvind)

v9:(Marek)
  - Use the drm signal/wait structure as the parameter. (Arun)

Cc: Deucher, Alexander <alexander.deucher@amd.com>
Cc: Koenig, Christian <christian.koenig@amd.com>
Cc: Sharma, Shashank <shashank.sharma@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
2025-04-10 10:03:07 -04:00
Arvind Yadav
72d3140428 amdgpu: UAPI for AMDGPU usermode queues
This patch adds UAPI interface changes for AMDGPU usermode
queues, semaphore and new AMDGPU GEM domain for doorbells.
Usermode queues allow a userspace process to create
and submit its graphics/compute/sdma work directly to the GPU.

v2:(Marek)
 - Add csa support for SDMA queue.
 - Rename UAPI objects and struct as per UAPI review. (Shashank)

v3:(Yogesh)
 - Rename UAPI timeline* objects as per UAPI review. (Arvind)

v4: (Marek)
 - Drop AMDGPU_USERQ_BO_WRITE as this should not be a global option
   of the IOCTL, It should be option per buffer. Hence adding separate
   array for read and write BO handles. (Arun)
 - Modify num_fences to __u16, flags changed to __u16 and placed
   the num_fences next to flags for optimal padding and size. (Arun)

 - Fix 32-bit holes issue in sturct drm_amdgpu_gem_va as per
   UAPI review (Arvind).

v5:(Marek/Pierre-Eric)
  - add more detail params description for signal and wait IOCTL calls.
  - Remove the unused structure fields in signal and wait structs.
  - Add separate array of read and write for BO handles. (Arun)

  - Removes the unused flags parameter from the usermode queue UAPI structure
  - Clarify comments on top of drm_amdgpu_userq_in
  - Clarify comment for queue_id (in)
  - Clarify comment for mqd
  - Clarify comment for compute MQD size
  - Clarify comment for queue_id (out)
  - Adds padding variables in userqueue in/out structures. (Shashank)

v6:(Pierre-Eric)
  - Modify the function parameter names and struct
    field names as per the review comments. (Arun)

v7:(Marek)
  - Modify the structure field name and comments. (Arun)

  - Rename vm_timeline_syncobj and add comment for
    vm_timeline_point.
  - Remove GDS buffer support from MQD. (Arvind)

v8:(Pierre-Eric)
  - Modify the function parameter names.

Cc: Koenig, Christian <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
2025-04-10 10:03:07 -04:00
Shashank Sharma
5d7d7c4318 drm/amdgpu: add new AMDGPU_INFO subquery for userqueue metadata
This patch:
- adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in AMDGPU_INFO_IOCTL
  to get the size and alignment of shadow and csa objects from the
  kernel. This information is required for a userqueue consumer (like
  MESA/libdrm) to create the userqueue metadata objects properly.
- also adds supporting metadata structures and a high level wrapper
  function (amdgpu_query_uq_metadata_info) to the query, to make it
  easy to use.

The corresponding kernel changes for this UAPI extension can be found
in amd-gfx mailing list, link:
https://patchwork.freedesktop.org/patch/621390/?series=139715&rev=2

This patch adds support only for the GFX IP, and the other engines may
be supported in subsequent development.

V2: fix the build error due to exporting of helper function
V3: make an entry for amdgpu_query_uq_metadata_info in
    amdgpu-symbols.txt
V4: Rename the subquery to AMDGPU_INFO_UQ_FW_AREAS (Marek, Pierre-Eric)
V5: Addressed review comments (Pierre-Eric):
    - Fix the API comment to match the new IOCTL name
    - remove the unused uq_metadata parameter

Cc: Marek Olsak <marek.olsak@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Arvind Yadav <arvind.yadav@amd.com>
Reviewed-by: Marek Olsak <marek.olsak@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
2025-04-10 13:20:00 +00:00
Daniel van Vugt
d387ec976f xf86drm: Handle NULL in drmCopyVersion
Just as it is already handled in the caller, `drmGetVersion`.

I'm not sure what the offending driver is, but the Ubuntu incidents
seem to be coming from a dual Intel/Nvidia machine. And they show
it is `card1` so I'm guessing `nvidia-drm` is the offender.

Related: https://bugs.launchpad.net/bugs/2104352
2025-03-27 17:43:05 +08:00
Alex Deucher
a7eb2cfd53 amdgpu: add new marketing names
Updated client names.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-01-17 17:26:15 -05:00
Simon Ser
c7684a957a xf86drm: deprecate drmAvailable()
Signed-off-by: Simon Ser <contact@emersion.fr>
References: https://gitlab.freedesktop.org/mesa/drm/-/issues/113
2025-01-09 14:08:03 +00:00
Alex Deucher
e7d4b1df2d amdgpu: add new marketing names
Updated from 6.3 branch.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-12-18 13:15:57 -05:00
Alex Deucher
1f140f7d65 amdgpu: add new marketing names
Updated from 6.2 branch.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-12-18 13:11:38 -05:00
Matt Turner
38ec7dbd4d build: bump version to 2.4.124 2024-12-04 13:30:30 -05:00
Rob Barnes
f314a43f14 modetest: Make modetest availble to vendor on Android
Make modetest available to vendors on Android. libdrm_util and
libdrm_test_headers is also made available to vendors since these are
depenencies of modetest. This results in the module target
modetest.vendor being availble to vendor modules.

Signed-off-by: Rob Barnes <robbarnes at google.com>
2024-10-29 10:49:10 -06:00
Mauro Rossi
e68e9b8013 android: add genrule for generated_static_table_fourcc.h
Fixes the following building error:

external/libdrm/xf86drm.c:158:10: fatal error: 'generated_static_table_fourcc.h' file not found
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Change-Id: I1b0cac498ed63ebec6e8c03629bbf4a1b6a9618d
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
2024-10-20 12:26:53 +02:00
Marek Olšák
50da61eebd xf86drm: print AMD modifiers properly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2024-10-15 19:49:05 -04:00
Alan Coopersmith
c0a08f06ae include/drm/README: update drm-next link to use gitlab instead of cgit 2024-09-29 17:47:51 -07:00
Dmitry Baryshkov
0a1162e2af modetest: add support for YUV422 and YUV444 plane format
Currently modetest supports only the YUV420 and YVU420 planar YCbCr
plane formats (aka YV12 and YU12). Extend the code to add support for
YUV422 / YVU422 and YUV444 / YVU444 plane formats.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-09-23 21:11:29 +02:00
Dmitry Baryshkov
38c043dca2 modetest: simplify planar YUV handling
In preparation to adding more planar YUV formats, introduce X, Y
subsampling ratios and use them to calculate plane offsets and buffer
size.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-09-23 21:11:29 +02:00
Simon Ser
bea14386bc build: simplify Linux system check
No need for contains() here.

Signed-off-by: Simon Ser <contact@emersion.fr>
2024-09-08 09:15:08 +00:00
Marijn Suijten
887fec2c28
tests/util: Call drmGetDevices2() instead of drmOpen()ing all modules
Whenever `util_open()` is called to open a device for the first matching
module, it will skip devices for the `nvidia_drm` kernel module which
is not in the list.  We could add this module for now, but keeping this
list of DRM modules up to date is cumbersome.

At the same time walking a list of modules and calling `drmOpen()` for
each of them is incredibly expensive (when the user doesn't explicitly
specify one with `-M`), as each each call opens every DRM node just
to see if they are associated to the requested module.  And for no
good reason: all we want is the first `DRM_NODE_PRIMARY` (which is what
`drmOpen()` also returns) to use by default.

For example on the `"msm"` driver, which used to be the 9th in the
modules list, all nodes are opened for the 9th time before e.g.
`modetest` returns a useful result, which takes ages unless the user
painstakingly provides the module for the currently known device on
the cmdline.

This is very simply solved by calling `drmGetDevices(2)()`, which
iterates through all DRM nodes only once and allows us to immediately
find + `open()` the first device that has a PRIMARY node.  A random
search for the error shows that this was also attempted in (a fork of?)
kmscube:
https://git.ti.com/cgit/glsdk/kmscube/commit/?id=456cabc661caac5c60729751d45efd668faa8e97

Finally we add a `drmIsKMS()` check to make sure we only include primary
nodes that actually support rendering, and also print the values from
`drmGetVersion()` on success to make it easier to identify the device.

In the future we could extrapolate this feature by letting query
commands like `modetest -c` list connectors for every device/module, not
just the first PRIMARY node that we found.
2024-09-03 13:30:41 +02:00
Matt Turner
25dec5b91f build: bump version to 2.4.123 2024-08-26 13:10:22 -07:00
Mark Collins
f3f56f41bb Disable ioctl signed overload for Bionic libc
Bionic libc ships with `ioctl` that has two signatures, one with an
unsigned `request` parameter and one with a signed request parameter.

This leads to compilation failing due to `__typeof__(ioctl)` being used
by DRM which fails to resolve which overload to use, this has been fixed
by defining `BIONIC_IOCTL_NO_SIGNEDNESS_OVERLOAD` on Android.

Signed-off-by: Mark Collins <mark@igalia.com>
2024-08-22 18:45:38 +00:00
Su Hong Koo
88db611498 tests: Make modetest and proptest cc_binary in Android.bp
Change module type of modetest and proptest from cc_test to cc_binary,
as neither are tests.

Signed-off-by: Su Hong Koo <sukoo@google.com>
2024-08-01 10:09:05 -04:00
Daniel Stone
b0815faac0 libs: Tie DSO minor versions to libdrm version
There is an excellent writeup explaining this requirement here:
    https://gitlab.freedesktop.org/wayland/wayland/-/issues/175

In short, for mixed environments such as the Steam Runtime and other
container-like environments, choosing which libdrm to link into the
client's address space is a hard problem. If the runtime has a newer
libdrm than the host, then it should be preferred, because the client
may be using newly-added symbols. But if the host has a newer libdrm,
then that should be used, because drivers may be depending on those.

Bumping the DSO minor version is transparent to all users because apps
only link against the major version, e.g. DT_NEEDED libdrm.so.2; the
fact that libdrm.so.2 is a link to libdrm.so.2.122.0 is a detail known
only to the loader, but it does let a smart runtime make better
decisions.

Signed-off-by: Daniel Stone <daniels@collabora.com>
2024-08-01 13:28:41 +01:00
Jiyong Park
4bd09d78df Enable GPU in crosvm
When the GPU feature is turned on in crosvm, these modules are added as
dependencies. Since crosvm is included in the virt APEX, add the APEX to
the apex_available properties of the modules to make them available in
the APEX.
2024-07-30 10:54:34 -04:00
Jiyong Park
d9043a256f add crosvm to com.android.virt
To do so, crosvm and its dependencies have the apex_available property
set to "//apex_available:platform", "com.android.virt" to explicitly
acknowledge the joining.
2024-07-30 10:54:34 -04:00
Jason Macnak
f22956a4e9 Adds libdrm_headers
... as being able to use cc_library in header_libs is not
intended and does not work on all branches which blocks
aosp/1497292.
2024-07-30 10:54:34 -04:00
Inseob Kim
460f7907de Export include dirs with -isystem
drm_property_type_is function in xf86drmMode.h file can cause compiler
error because it performs unsigned to signed conversion. Some Android.mk
modules have been avoiding this by adding "-isystem external/libdrm"
flag, because warnings from system headers are suppressed.

This changes exported_include_dirs to export_system_include_dirs
to workaround the potential error with the same manner above.
2024-07-30 10:54:34 -04:00
Jason Macnak
dcb14fe0c6 Makes libdrm available on host
... to make drm format header visible for host wayland server.

Adds -Wno-implicit-function-declaration for vasprintf() on
xf86drm.c:2965.

Adds -Wno-int-conversion for drm_mmap() on libdrm_macros.h:60.

Also, drive-by alphabetize cflags.
2024-07-30 10:54:34 -04:00
Jerry Zhang
6aa6411c5a Make libdrm recovery_available 2024-07-30 10:54:34 -04:00
John Stultz
c2b5759a2f Android.bp: Add include exports for android dir
This forward ports Stefan Schake's patch
32ee9c0e05 "android: Add missing include exports" to the
Android.bp file.
2024-07-30 10:54:34 -04:00
Elliott Hughes
aef24b66d9 readdir_r is deprecated.
Add -Wno-deprecated-declarations to suppress compiler warning about
using readdir_r, which is deprecated.
2024-07-30 10:54:34 -04:00
Su Hong Koo
aefb5fa987 Delete all Makefile.sources files
Delete all Makefile.sources as all the makefiles that use them have
been replaced with Android.*.bp files for Soong.
2024-07-30 10:54:23 -04:00
Dan Willemsen
21ac1816a4 Convert to Android.bp
See build/soong/README.md for more information about Soong.

Removes BOARD_GPU_DRIVERS, which wasn't affecting anything, since none
of the HAVE_* macros are defined. Even if they were, we'd prefer to
compile all of them so that a single library can support multiple
boards.
2024-07-29 14:47:30 -04:00
Alex Deucher
11cafdd8d6 amdgpu: add new marketing names
Updated from 6.1 branch.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-11 21:46:17 -04:00
Alex Deucher
5e1e7c4d71 amdgpu: add new marketing names
https://www.amd.com/en/processors/ryzen-processors-laptop-business
https://www.amd.com/en/products/ryzen-pro-processors-laptop

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-11 21:31:50 -04:00
Enrico Weigelt, metux IT consult
b065dbc5cc Fix FTBS on undefined clock_gettime() and asprintf()
Some platforms (eg. SunOS) explicitly need extra symbols in order to define
those functions. There're many files needing the __EXTENSIONS__ symbol,
so doing this on a global scale.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-27 02:07:00 +02:00
Simon Ser
ad78bb591d build: bump version to 2.4.122
Signed-off-by: Simon Ser <contact@emersion.fr>
2024-06-26 10:13:31 +02:00
Simon Ser
998d2a2e81 Sync headers with drm-next
Synchronize drm_fourcc.h and drm_mode.h to drm-next.

Generated using make headers_install.
Generated from drm-next branch commit 541b1b0a8fc235bca355921eb7f3f59a8efa3e9a

Signed-off-by: Simon Ser <contact@emersion.fr>
2024-06-26 08:08:40 +00:00
Enrico Weigelt, metux IT consult
a97bd7b4ac ci: upgrade FreeBSD VM to 14.1
Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-25 12:57:01 +02:00
Enrico Weigelt, metux IT consult
d096affbaa ci: upgrade debian container to bookworm
Buster is oldoldstable and EOL in a few days. Bookworm is the current stable.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-25 12:56:11 +02:00
Enrico Weigelt, metux IT consult
589f8e86f1 etnaviv: fix FTBS on undefined linux/* headers on non-Linux platforms.
Using C standard headers instead.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-25 10:41:35 +02:00
Enrico Weigelt, metux IT consult
b7338fc842 freedreno: fix FTBS on non-Linux platforms (unused header)
The <linux/fb.h> header only exists on Linux, but isn't used anymore,
so drop it entirely.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-24 17:44:54 +00:00
Enrico Weigelt, metux IT consult
90c1a35f2a fix FTBS on FreeBSD (or non-Linux in general)
Several drivers still including <linux/stddef.h>, but not using anything
from it, thus breaking build on non-Linux platforms (eg. FreeBSD).
Since not needed at all, just stop including it.

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-24 17:24:28 +00:00
Enrico Weigelt, metux IT consult
0cd18d0dfb OpenBSD: fix FTBS on misspelled and missing variables
../xf86drm.c:4622:9: error: use of undeclared identifier 'written'; did you mean 'write'?
    if (written + 1 > max_node_length)
        ^~~~~~~
        write

../xf86drm.c:4624:21: error: use of undeclared identifier 'sbuf'; did you mean 'sbrk'?
    if (stat(node, &sbuf))
                    ^~~~

Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
2024-06-24 12:57:51 +02:00
Nicolas Caramelli
7f20912b1b Remove libm in libdrm dependencies
Signed-off-by: Nicolas Caramelli <caramelli.devel@gmail.com>
2024-06-02 22:09:56 +00:00
Marek Olšák
70c4f836cc Bump version to 2.4.121 2024-06-01 13:31:41 -04:00
Marek Olšák
93d037cdd4 amdgpu: sync amdgpu_drm.h 2024-06-01 13:27:04 -04:00
Flora Cui
37265ab0ad tests/amdgpu: fix compile error with gcc14
../../drm/tests/amdgpu/shader_code.h:114:9: error: initialization of
‘const uint32_t *’ {aka ‘const unsigned int *’} from incompatible
pointer type ‘const uint32_t (*)[10][6]’ {aka ‘const unsigned int
(*)[10][6]’} [-Wincompatible-pointer-types]
  114 |         ps_##_ps##_shader_patchinfo_code_gfx##_n, \
      |         ^~~
../../drm/tests/amdgpu/shader_code.h:119:10: note: in expansion of macro
‘SHADER_PS_INFO’
  119 |         {SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
      |          ^~~~~~~~~~~~~~

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-05-27 10:37:25 +08:00
Flora Cui
cee441f32d tests/amdgpu: fix compile error with gcc7.5
fix commit cc3c80c6("tests/amdgpu: refactor dispatch/draw test")
../../SOURCES/drm/tests/amdgpu/shader_code.h:113:2: error: initializer
element is not constant
  ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
	    ^

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-05-27 10:37:18 +08:00
Flora Cui
058a04de62 tests/amdgpu: fix compile warning with the guard enum value
../../drm/tests/amdgpu/shader_test_util.c: In function
‘amdgpu_dispatch_init’:
../../drm/tests/amdgpu/shader_test_util.c:296:9: warning: enumeration
value ‘AMDGPU_TEST_GFX_MAX’ not handled in switch [-Wswitch]
  296 |         switch (test_priv->info->version) {
      |         ^~~~~~

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-05-27 10:37:13 +08:00
José Expósito
4df9173595 amdgpu: Make amdgpu_cs_signal_semaphore() thread-safe
The issue was found by a static analysis tool:

    Error: LOCK_EVASION (CWE-543):
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:596: thread1_checks_field:
        Thread1 uses the value read from field "context" in the
        condition "sem->signal_fence.context". It sees that the
        condition is false. Control is switched to Thread2.
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:596: thread2_checks_field:
        Thread2 uses the value read from field "context" in the
        condition "sem->signal_fence.context". It sees that the
        condition is false.
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:598: thread2_acquires_lock:
        Thread2 acquires lock "amdgpu_context.sequence_mutex".
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:599: thread2_modifies_field:
        Thread2 sets "context" to a new value. Note that this write can
        be reordered at runtime to occur before instructions that do
        not access this field within this locked region. After Thread2
        leaves the critical section, control is switched back to
        Thread1.
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:598: thread1_acquires_lock:
        Thread1 acquires lock "amdgpu_context.sequence_mutex".
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:599: thread1_overwrites_value_in_field:
        Thread1 sets "context" to a new value. Now the two threads have
        an inconsistent view of "context" and updates to fields of
        "context" or fields correlated with "context" may be lost.
    libdrm-2.4.115/amdgpu/amdgpu_cs.c:596: use_same_locks_for_read_and_modify:
        Guard the modification of "context" and the read used to decide
        whether to modify "context" with the same set of locks.
    #  597|                   return -EINVAL;
    #  598|           pthread_mutex_lock(&ctx->sequence_mutex);
    #  599|->         sem->signal_fence.context = ctx;
    #  600|           sem->signal_fence.ip_type = ip_type;
    #  601|           sem->signal_fence.ip_instance = ip_instance;

Check `sem->signal_fence.context` in the locked region to avoid a race
condition.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: José Expósito <jexposit@redhat.com>
2024-05-23 18:57:18 +00:00
Simon Ser
362b5b0a88 xf86drm: document drmDevicesEqual()
I always need to double-check what the return value means when
using that function (since it's not a bool).

Signed-off-by: Simon Ser <contact@emersion.fr>
2024-04-11 12:11:30 +02:00
David Heidelberg
1179edb49a include poll.h instead of sys/poll.h
Fixes: f803a45e74 ("add libsync.h helper")
Fixes: 4c18828e16 ("tegra: Add job and push buffer APIs")
Signed-off-by: David Heidelberg <david@ixit.cz>
2024-04-10 23:27:16 +00:00
Simon Ser
f94a79a7a7 ci: use "meson setup" sub-command
"meson" without a sub-command is deprecated.

Signed-off-by: Simon Ser <contact@emersion.fr>
2024-03-29 16:09:47 +01:00
Simon Ser
5a9cfb3c59 ci: build with meson --fatal-meson-warnings
This catches uses of deprecated features.

Signed-off-by: Simon Ser <contact@emersion.fr>
2024-03-29 11:44:09 +01:00
Joaquim Monteiro
764ed8b916
meson: Fix broken str.format usage
str.format used to allow any type as an argument, which often resulted
in using an internal string representation. This is considered broken
behavior, and is deprecated since Meson 1.3.0.

Signed-off-by: Joaquim Monteiro <joaquim.monteiro@protonmail.com>
2024-03-29 10:24:22 +00:00
Joaquim Monteiro
fbb83f74d6
meson: Replace usages of deprecated ExternalProgram.path()
!347 fixed some of these, but not all.

Signed-off-by: Joaquim Monteiro <joaquim.monteiro@protonmail.com>
2024-03-29 10:23:52 +00:00
Pierre-Eric Pelloux-Prayer
c7c3c14bfc amdgpu: fix deinit logic
The devices weren't removed from dev_list.

Instead of just fixing the issue by adding:

   if (*node) *node = dev->next;

after the while loop, use this opportunity to use a clearer
control flow.

Fixes: 7275ef8e ("amdgpu: add amdgpu_device_initialize2")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
2024-03-27 08:55:26 +01:00
Matt Turner
c45ffb1edf symbols-check: Add _fbss, _fdata, _ftext
These are exported on mips/mips64.

See also: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11955
2024-03-25 15:35:58 +00:00
Matt Turner
525e80447f symbols-check: Add _GLOBAL_OFFSET_TABLE_
This is exported on hppa/parisc.

See also: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26978

Bug: https://bugs.gentoo.org/927204
2024-03-25 15:35:58 +00:00
Pierre-Eric Pelloux-Prayer
7275ef8eba amdgpu: add amdgpu_device_initialize2
Allows to opt-out from the device deduplication logic. This is not the
recommended way of using dev handles, but it's necessary for native context:
in this situation one process (eg: Qemu) will init many devices and we
want independent devices to make sure guest applications are isolated from
each other.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-03-21 11:03:38 +01:00
Pierre-Eric Pelloux-Prayer
6978f999ea amdgpu: add amdgpu_va_range_alloc2
This is the same functionnality that amdgpu_va_range_alloc offers,
except it's now usable without a device handle.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-03-21 10:57:04 +01:00
Pierre-Eric Pelloux-Prayer
96fe43a029 amdgpu: expose amdgpu_va_manager publicly
This will allow applications to use this feature without a device.

The first use case will be native context: we want VA address to
be managed by the guest (to avoid a round-trip to the host to only
generate a VA) but the amdgpu_device only exist on the host.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-03-21 10:57:02 +01:00
Pierre-Eric Pelloux-Prayer
4376848720 amdgpu: add amdgpu_va_manager
Until now VA management was tied to a device handle, but there's no
reason for this.

As a first step to export VA management outside of amdgpu_device,
this commit adds a new structure type holding the 4 va_mgr.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-03-21 10:56:29 +01:00
David Rosca
c8f327ce9c amdgpu: Make amdgpu_device_deinitialize thread-safe
Device will be removed from dev_list when refcount reaches 0, so the
dev_mutex must be locked before decreasing reference otherwise there's
a race where this device is still in dev_list with refcount 0 which will
assert or crash in amdgpu_device_initialize trying to use this device
instead of creating new one.

Fixes issue reported in https://gitlab.freedesktop.org/drm/amd/-/issues/2156#note_2268110

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-03-05 03:53:39 +00:00
Francesco Valla
1b4e04ba68 tests/util: add tidss driver
Add an entry for the "tidss" driver, so that the test utilities work
with this driver without passing the -M argument.

Signed-off-by: Francesco Valla <valla.francesco@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-26 23:50:25 +01:00
Adrián Larumbe
01f91aa73d meson: make build system happy by replacing deprecated feature
ExternalProgram.path() is deprecated since 0.55, use
ExternalProgram.full_path() instead.

Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
2024-02-15 01:20:02 +00:00
Dylan Baker
7c5c742de8 xf86drm: Don't consider node names longer than the maximum allowed
This fixes the logic that decides if a node name is valid to use the
same length restrictions that are used in drmDeviceAlloc, which expects
node names to conform to a specific naming scheme (On OSes except
OpenBSD this means `/dev/dri/renderD123`). This addresses the problem of
node names that are longer than expected, while still allowing symlinks
to work.

I've also applied the same fix to the OpenBSD path, while bringing the
check that `snprintf` didn't error from OpenBSD to the main path.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
2024-02-12 12:03:21 -08:00
Dylan Baker
1aa800d464 Revert "xf86drm: ignore symlinks in process_device()"
This reverts commit 7ab1cdac90.

This breaks numerous tools that rely on being able to read symlinks, and
constitutes a regression.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Closes: #103
2024-02-12 12:03:17 -08:00
Tobias Jakobi
7ab1cdac90 xf86drm: ignore symlinks in process_device()
If the user has some UDev rules in place that creates symlinks for
one of the card or render nodes, and the name of the symlink is
too long, then drmDeviceAlloc() ends up truncating the name of
the node.
This in turn results in chaos in different subsystems. E.g.
vulkaninfo dies early with this:

Code 0 : failed to stat DRM primary node /dev/dri/my-favorite- (VK_ERROR_INITIALIZATION_FAILED)
(if the symlink is called /dev/dri/my-favorite-card-node)

Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
2024-02-08 14:23:52 +00:00
Jonathan Gray
140943281b amdgpu: add marketing names from amd-6.0.1 2024-01-24 11:17:03 +11:00
Jonathan Gray
9d9498f466 amdgpu: add marketing name for Radeon RX 6550M
from notebookcheck review of Lenovo ThinkPad Z16 Gen 2
2024-01-24 11:17:03 +11:00
Jonathan Gray
dfb8111ecb amdgpu: add marketing names from amd-6.0 2024-01-24 11:17:03 +11:00
Jonathan Gray
fb13af4398 amdgpu: add marketing names from Windows Steam Deck OLED APU driver 2024-01-24 11:17:03 +11:00
Jonathan Gray
6414474000 amdgpu: add marketing names from PRO Edition for W7700 2024-01-24 11:17:03 +11:00
Jonathan Gray
ad750dc608 amdgpu: add marketing names from Adrenalin 23.11.1 2024-01-24 11:17:03 +11:00
Simon Ser
75254bf239 build: bump version to 2.4.120
Signed-off-by: Simon Ser <contact@emersion.fr>
2024-01-13 10:37:07 +01:00
Simon Ser
6c4392f49b Sync headers with drm-next
Synchronize drm.h and drm_mode.h to drm-next.

Generated using make headers_install.
Generated from drm-next branch commit a60501d7c2d3e70b3545b9b96576628e369d8e85

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Simon Zeni <simon.zeni@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-01-13 10:33:05 +01:00
Pierre-Eric Pelloux-Prayer
118addfaf8 amdgpu: fix use-after-free
Closes: https://gitlab.freedesktop.org/mesa/drm/-/issues/96
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2024-01-04 11:00:37 +01:00
Eric Engestrom
54b1208138 radeon: fix missing stencil_tile_mode initialisation in the linear/fallback case
../radeon/radeon_surface.c:1611:13: error: 'stencil_tile_mode' may be used uninitialized [-Werror=maybe-uninitialized]
 1611 |         r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0);
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2024-01-01 07:43:19 +00:00
Marek Olšák
fc5f2239f3 meson: bump libdrm version to 2.4.119
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2023-12-21 06:49:36 -05:00
Marek Olšák
85343095fd amdgpu: add amdgpu_va_get_start_addr
for Mesa

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2023-12-21 06:49:34 -05:00
Simon Ser
02a41cf302 build: bump version to 2.4.118
Signed-off-by: Simon Ser <contact@emersion.fr>
2023-11-20 14:03:51 +01:00
Simon Ser
07f4948bfc xf86drmMode: add drmModeCloseFB()
Add a wrapper for the new CLOSEFB IOCTL, to close a framebuffer
without implicitly disabling planes or CRTCs.

See https://lore.kernel.org/dri-devel/20231020101926.145327-2-contact@emersion.fr/

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-11-20 12:55:31 +00:00
Simon Ser
7b60986640 Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.

Generated using make headers_install.
Generated from drm-next branch commit c79b972eb88b077d2765e7790d0902b3dc94d55c

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-11-20 12:55:31 +00:00
Simon Ser
15b7fbf3e7 xf86drm: add drmGetNodeTypeFromDevId
This is useful to figure out whether the dev_t refers to a primary
node or a render node. Indeed, drmGetDeviceFromDevId returns a
drmDevice, which holds both the primary and render nodes.

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-11-20 12:22:10 +00:00
Neil Armstrong
6acadd495c modetest: switch usage to proper options grammar
It was unclear how #mode could be used, so fixup the usage string and print
the struct grammar of the -s and -P options to clarify the usage.

The following grammar was compiled:
<plane_topology> ::= <plane_id> "@" <crtc_id> ":" <width> "x" <height> ( <plane_offsets> )?
<plane_offsets> ::= "+" <x_offset> "+" <y_offset> ( <plane_scale> )?
<plane_scale> ::= "*" <scale> ( <plane_format> )?
<plane_format> ::= "@" <format>

<mode_topology> ::= <connector_id> ( "," <connector_id> )* ( "@" <crtc_id> )? ":" <mode_selection> ( "@" <format> )?
<mode_selection> ::=  <indexed_mode> | <named_mode> | <custom_mode>
<indexed_mode> ::=  "#" <mode_index>
<named_mode> ::=  <width> "x" <height> ( "-" <vrefresh> )?
<custom_mode> ::=  <hdisplay> "," <hsyncstart> "," <hsyncend> "," <htotal> "," <vdisplay> "," <vsyncstart> "," <vsyncend> "," <vtotal>  "-" <vrefresh>
<property>  ::= <object_id> ":" <property_name> ":" <value>

<plane_id> ::= [0-9]+
<crtc_id> ::= [0-9]+
<width> ::= [0-9]+
<height> ::= [0-9]+
<x_offset> ::= [0-9]+
<y_offset> ::= [0-9]+
<scale> ::= [0-9]+ ( "." [0-9]+ )
<format> ::= ( [A-Z] | [0-9] )+
<connector_id> ::= [0-9]+
<mode_index> ::= [0-9]+
<hdisplay> ::= [0-9]+
<hsyncstart> ::= [0-9]+
<hsyncend> ::= [0-9]+
<htotal> ::= [0-9]+
<vdisplay> ::= [0-9]+
<vsyncstart> ::= [0-9]+
<vsyncend> ::= [0-9]+
<vtotal> ::= [0-9]+
<object_id> ::= [0-9]+
<vrefresh> ::= [0-9]+
<property_name> ::= ( [A-Z] | [0-9] | "_" )+
<value> ::= [0-9]+

with the https://bnfplayground.pauliankline.com/ service

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-11-15 09:11:48 +00:00
Geert Uytterhoeven
a0b011439d modetest: add support for big-endian XRGB1555/RGB565
Add support for creating buffers using big-endian formats.

For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - No changes,

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
584a85b891 util: add pwetty support for big-endian RGB565
Add support for rendering the crosshairs in a buffer using the
big-endian RGB565 format.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - No changes,

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
32a03fb32c util: fix pwetty on big-endian
Cairo always uses native byte order for rendering.

Hence if the byte order of the frame buffer differs from the byte order
of the CPU, the frame buffer contents need to be byteswapped twice: once
before rendering, to convert to native byte order, and a second time
after rendering, to restore the frame buffer format's byte order.

Note that byte swapping is not done for ARGB32 formats, as for these
formats, byte order only affects the order of the red, green, and blue
channels, which we do not care about here.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Wrap byteswap_buffer{16,32}() implementation inside #if HAVE_CAIRO
    to avoid defined-but-not-used compiler warnings,

v2:
  - RGB30 is untested.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
6f00a73485 util: add test pattern support for big-endian XRGB1555/RGB565
Add support for drawing the SMPTE and tiles test patterns in buffers
using big-endian formats.

For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Increase indentation after definition of cpu_to_be16(),

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
bc37db5c66 modetest: add support for parsing big-endian formats
When specifying a frame buffer format like "RG16_BE" (big-endian RG16),
modetest still uses the little-endian variant, as the format string is
truncated to four characters.

Fix this by increasing the format string size to 8 bytes (7 characters +
NUL terminator).

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Update for suffix change from "be" to "_BE", cfr. commit
    ffb9375a50 ("xf86drm: handle DRM_FORMAT_BIG_ENDIAN in
    drmGetFormatName()"),
  - Replace hardcoded numbers in code by sizeof(),

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
9d7024218f util: add missing big-endian RGB16 frame buffer formats
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Update for suffix change from "be" to "_BE", cfr. commit
    ffb9375a50 ("xf86drm: handle DRM_FORMAT_BIG_ENDIAN in
    drmGetFormatName()"),

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
1b8d0e5ccd util: fix 16 bpp patterns on big-endian
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set.  Hence writes of multi-byte pixel
values need to take endianness into account.

Introduce a swap16() helper to byteswap 16-bit values, and a
cpu_to_le16() helper to convert 16-bit values from CPU-endian to
little-endian, and use the latter in the various pattern fill functions
for 16-bit formats.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Increase indentation after definition of cpu_to_le16(),

v2:
  - New.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
8cb6d837cc util: fix 32 bpp patterns on big-endian
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set.  Hence writes of multi-byte pixel
values need to take endianness into account.

Introduce a swap32() helper to byteswap 32-bit values, and a
cpu_to_le32() helper to convert 32-bit values from CPU-endian to
little-endian, and use the latter in the various pattern fill functions
for 32-bit formats.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - Use new HAVE_BIG_ENDIAN symbol,

v3:
  - Increase indentation after definition of cpu_to_le32(),

v2:
  - Add Acked-by,
  - Add swap32() intermediate helper,
  - Add __ARM_BIG_ENDIAN and __s390__.
2023-10-31 13:24:32 +00:00
Geert Uytterhoeven
5dba8d73df intel: determine target endianness using meson
The endianness of the target is currently determined based on
preprocessor symbols.  Unfortunately some symbols checked are wrong
(sparc64-linux-gnu-gcc does not define __BIG_ENDIAN__ or SPARC), and
several checks for big-endian architectures are missing.

Fix this by introducing a new preprocessor symbol HAVE_BIG_ENDIAN, which
is set based on meson's knowledge of the target endianness.

Android.common.mk does not need an update, as Android is always
little-endian (https://developer.android.com/ndk/guides/abis.html).

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - Replace explicit #ifdef checks by a define set by meson,

v3:
  - No changes,

v2:
  - Add arm, aarch64, microblaze, s390, and sh.
2023-10-31 13:24:32 +00:00
Jonas Karlman
de88f74df9 modetest: add support for DRM_FORMAT_NV{15,20,30}
Add smpte and tiles pattern for 10-bit NV15, NV20 and NV30 pixel formats
based on the existing pattern for NV12 with colors simply scaled from
8-bit to 10-bit.

These pixel formats are typically used by video decoder and display
pipeline on Rockchip SoCs, e.g. on RK322X, RK3288, RK3328 and RK3399
the video decoder produce 10-bit video frames in NV15 and NV20 format.

NV20 and NV30 pixel formats was added in drm-misc commit 728c15b4b5f3
("drm/fourcc: Add NV20 and NV30 YUV formats").

This can be tested/validated on Rockchip SoCs with drm-misc commit
d4b384228562 ("drm/rockchip: vop: Add NV15, NV20 and NV30 support").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-10-30 12:25:09 +00:00
David Jagu
8a933c778a meson: fix typo in libdrm_intel
Replace system() with cpu_family() for libdrm_intel
This restore libdrm_intel to be built by default

Closes: #93

Signed-off-by: David Jagu <marav8@free.fr>
2023-10-24 18:59:39 +02:00
Geert Uytterhoeven
a2dbfd6442 modetest: add SMPTE pattern support for C[124] formats
Add support for drawing the SMPTE pattern in buffers using a
color-indexed frame buffer formats with two, four, or sixteen colors.

Note that this still uses 256 as the CLUT size, as
DRM_IOCTL_MODE_SETGAMMA enforces that the size matches against the
(fixed) gamma size, while the CLUT size depends on the format.

Move clearing the color LUT entries from util_smpte_index_gamma() to its
caller, as only the caller knows how many entries there really are
(currently DRM always assumes 256 entries).

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - Add missing C[12] to oneline-summary,
  - Do not remove memset() of full lut, else some entries may stay
    uninitialized,

v3:
  - Add Acked-by,

v2:
  - Split off changes to tests/modetest/modetest.c,
  - Add C1 and C2 support.

The linuxdoc comments say userspace can query the gamma size:

 * drm_mode_gamma_set_ioctl - set the gamma table
 *
 * Set the gamma table of a CRTC to the one passed in by the user. Userspace can
 * inquire the required gamma table size through drm_mode_gamma_get_ioctl.

 * drm_mode_gamma_get_ioctl - get the gamma table
 *
 * Copy the current gamma table into the storage provided. This also provides
 * the gamma table size the driver expects, which can be used to size the
 * allocated storage.

but the code doesn't seem to support that in an easy way (like setting
red/green/blue to NULL on input, retrieving gamma_size on output), only
by providing big enough buffers for red/green/blue, and looping over
gamma_size until -EINVAL is no longer returned.
2023-10-24 09:45:14 +02:00
Geert Uytterhoeven
bf462d0311 modetest: add support for DRM_FORMAT_C[124]
Add support for creating buffers using the new color-indexed frame
buffer formats with two, four, and sixteen colors.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Add Acked-by,

v2:
  - Split off changes to tests/modetest/buffers.c.
2023-10-24 09:45:09 +02:00
Geert Uytterhoeven
c895650f5d util: add SMPTE pattern support for C2 format
Add support for drawing the SMPTE pattern in a buffer using the C2
indexed format.

As only four colors are available, resolution is halved, and the pattern
is drawn in a PenTile RG-GB matrix, using Floyd-Steinberg dithering.
The magnitude of the green subpixels is reduced, as there are twice as
many green subpixels as red or blue subpixels.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dithering example at https://drive.google.com/file/d/1g5O8XeacrjrC8rgaVENvR65YeI6QvmtO/view

v5:
  - Add Reviewed-by,

v4:
  - Replace FILL_COLOR() use by pentile_color_lut[],

v3:
  - Add Acked-by,

v2:
  - New.
2023-10-24 09:44:49 +02:00
Geert Uytterhoeven
6b9b462729 util: add SMPTE pattern support for C1 format
Add support for drawing the SMPTE pattern in a buffer using the C1
indexed format.

As only two colors are available, the pattern is drawn in black and
white, using Floyd-Steinberg dithering[1].

[1] https://en.wikipedia.org/wiki/Floyd%E2%80%93Steinberg_dithering

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dithering example at https://drive.google.com/file/d/1waJczErrIaEKRhBCCU1ynxRG8agpo0Xx/view

v5:
  - Add Reviewed-by,

v4:
  - Replace FILL_COLOR() use by bw_color_lut[],

v3:
  - Add Acked-by,
  - Add Wikipedia link,

v2:
  New.
2023-10-24 09:44:29 +02:00
Geert Uytterhoeven
15c6657617 util: add SMPTE pattern support for C4 format
Add support for drawing the SMPTE pattern in a buffer using the C4
indexed format.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Add Acked-by,

v2:
  - Use new smpte_top[],
  - Split off changes to tests/util/pattern.c.
2023-10-24 09:44:25 +02:00
Geert Uytterhoeven
8134deb31f util: store number of colors for indexed formats
Store the number of available colors for color-indexed frame
buffer formats in the format_info[] array.  This avoids the need of test
code for having to use switch statements all the time to obtain the
number of colors, or to check if a mode is color-indexed or not.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Add Acked-by,

v2:
  - New.
2023-10-24 09:44:21 +02:00
Geert Uytterhoeven
236766b0b3 util: add support for DRM_FORMAT_C[124]
Add support for creating buffers using the new color-indexed frame
buffer formats with two, four, and sixteen colors.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Add Acked-by,

v2:
  - Split off changes to tests/util/format.c.
2023-10-24 09:44:13 +02:00
Geert Uytterhoeven
6d9645bb3b util: factor out and optimize C8 SMPTE color LUT
The color LUT for the SMPTE pattern in indexed mode contains 22 entries,
although only 13 are non-unique.

Reduce the size of the color LUT by dropping duplicate entries, so it
can be reused for formats supporting e.g. 16 colors.  Rename the
function util_smpte_c8_gamma() to util_smpte_fill_lut(), and its first
parameter size to ncolors, to match their actual use.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - Rename util_smpte_index_gamma() to util_smpte_fill_lut(), and its
    first parameter from size to ncolors,
  - Move smpte_color_lut[] down,
  - Kill FILL_COLOR() macro,
  - Add and use EXPAND_COLOR() macro,

v3:
  - Add Acked-by,

v2:
  - Factor out smpte color LUT.
2023-10-24 09:44:04 +02:00
Geert Uytterhoeven
eb06a81e42 util: improve SMPTE color LUT accuracy
Fill in the LSB when converting color components from 8-bit to 16-bit.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
v5:
  - Add Reviewed-by,

v4:
  - No changes,

v3:
  - Add Acked-by,

v2:
  - New.
2023-10-24 09:43:30 +02:00
Simon Ser
5254fd1146 build: bump version to 2.4.117
Signed-off-by: Simon Ser <contact@emersion.fr>
2023-10-20 07:24:54 +02:00
Dylan Baker
bd205d133e meson: replace deprecated program.path -> program.full_path
To avoid Meson warnings

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2023-10-20 05:21:01 +00:00
Dylan Baker
16e6a96505 meson: Use feature.require() and feature.allowed()
To reduce the size and complexity of checks. require() allows combining
auto and enabled checks(), so that something like
```meson
x = get_option('feature')
y = false
if x.enabled()
  if not condition
    error(...)
  endif
  y = condition
endif
```
can be rewritten as:
```meson
y = get_option('feature').require(condition, error_message : ...).allowed()
```
require checks the condition, then if the feature is required it emits
an error with the given message otherwise it returns a disabled feature.
allowed then returns whether the feature is not disabled, and returns
that (ie, .allowed() == not .disabled()). This is especially helpful for
longer more complex conditions

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2023-10-20 05:21:01 +00:00
Dylan Baker
a6a2ccb448 meson: fix intel requirements
Intel requires libpciaccess and an x86/x86_64 host, so if those
aren't found and it's enabled we need to error

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2023-10-20 05:21:01 +00:00
Samuel Pitoiset
8d8357dc64 amdgpu: add support for querying VM faults information
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2023-10-10 10:25:07 +02:00
Samuel Pitoiset
22b698a599 amdgpu: amdgpu_drm.h for new GPUVM fault ioctl
Based on agd5f/drm-next.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2023-10-10 10:25:07 +02:00
Simon Ser
6abc164052 ci: bump FreeBSD to 13.2
13.0 is no longer supported and causes a 404 when fetching the
image, see e.g. [1] for example failure.

[1]: https://gitlab.freedesktop.org/mesa/drm/-/jobs/45849458

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-09-19 23:39:10 +09:00
Simon Ser
bdab606879 xf86drm: mark DRM_MAX_MINOR as deprecated
With the work in [1], libdrm users should no longer rely on the
minor numbering scheme we've used so far. Instead, they should use
drmGetDevices2().

[1]: https://lore.kernel.org/lkml/20230724211428.3831636-1-michal.winiarski@intel.com/

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-09-19 23:35:59 +09:00
Chia-I Wu
13691f5266 modetest: print modifiers in hex as well
Print modifiers in hex in addtion to in strings returned by
drmGetFormatModifierName.  In some cases, hex numbers can be more easily
compared visually.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2023-09-13 16:26:49 +00:00
Marijn Suijten
dfd00c6250 modetest: allocate and commit atomic request around set_property()
Currently the atomic request is only assigned after `set_property()` is
called, leaving `dev.req` in its uninitialized state causing
`drmModeAtomicAddProperty()` to return an error code, which is printed
as `"Success"` because `errno` is not set by `libdrm` (but it would have
been when non-atomic `drmModeObjectSetProperty()` called an IOCTL
immediately):

    sony-akatsuki-row ~ $ modetest -M msm -a -w 81:ACTIVE:0
    failed to set CRTC 81 property ACTIVE to 0: Success

Solve this by assigning a new atomic request object before calling
`set_property()`, when there are properties to set.  Likewise, commit
these properties after `set_property()` even if there is no other
operation (setting modes or planes) specified.

Furthermore `drmModeObjectSetProperty()` is implemented in terms of
`DRM_IOCTL()` which already returns `-errno` when `ioctl()` returns
`-1`, so we should instead pass `ret` to `strerror()` and get an
accurate error string out of `drmModeAtomicAddProperty()` too.

Fixes: 93220283 ("tests/modetest: Add atomic support")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
2023-09-10 12:14:06 +00:00
Neil Armstrong
7618a64633 modetest: allow using -r and -P
Since now -r sets the pipe struct and count like -s we can also
use -P with -r.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-09-10 11:55:14 +00:00
Neil Armstrong
2e17aea573 modetest: permit -r and -s to work together
Let's permit testing vsync with the default mode, this returns
back the pipe content and count when calling set_mode() so the
vsync test can also be used.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-09-10 11:55:14 +00:00
Marijn Suijten
64b09cef49 modetest: document why no blob is created for linear gamma LUT
As found and discussed in [MR 58] a blob is not created in the else arm
because adding the GAMMA_LUT property with a NULL/0 blob_id causes it
to be reset to a default linear / pass-thru gamma table.  The values
in the gamma_lut table might still be consumed in the legacy API path
below though, so it has to be initialized to a linear table.

[MR 58]: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/58#note_466972

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
2023-09-09 11:07:56 +02:00
Ezequiel Garcia
b709c3010e modetest: avoid erroring if there's no gamma legacy support
Let's follow the Rule of Silence. And while here,
document what's going on.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
2023-09-09 11:07:47 +02:00
Dmitry Baryshkov
45f3d9bab6 modetest: custom mode support
It is useful to be able to specify mode parameters manually. Add support
for setting user-supplied modes. This patch is based on the original
idea by Rohit and Jessica, but implemented from scratch.

Suggested-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Suggested-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-09-08 18:19:31 +00:00
Geert Uytterhoeven
4d3635fada util: remove unused definitions of RED, GREEN, and BLUE
These are unused since commit edcef53685 ("modetest: Add test
pattern support for missing RGB formats").

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
v2:
  - Add Reviewed-by.
2023-09-08 18:01:43 +00:00
Geert Uytterhoeven
ea5237e549 modetest: fix mode_vrefresh() for interlace/dblscan/vscan
mode_vrefresh() does not take into account interlaced, doublescan, and
multiscan modes, leading to incorrect refresh rates.

Fix this, based on drm_mode_vrefresh() in Linux.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2023-09-08 18:01:43 +00:00
Geert Uytterhoeven
022a4d8a82 util: fix grey in YUV SMPTE patterns
The YUV SMPTE patterns use RGB 191/192/192 instead of 192/192/192 for
the grey color in the top color bar.

Change it to 192/192/192, to match the RGB SMPTE patterns.

Fixes: a94ee62429 ("modetest: Add SMPTE test pattern")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
v2:
  - Add Reviewed-by.
2023-09-08 18:01:43 +00:00
Geert Uytterhoeven
be42051ead modetest: add support for DRM_FORMAT_NV{24,42}
Add support for creating buffers using semi-planar YUV formats with
non-subsampled chroma planes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v2:
  - Add Reviewed-by.
2023-09-08 17:42:38 +00:00
Geert Uytterhoeven
8e5286d4f9 util: add pattern support for DRM_FORMAT_NV{24,42}
Add support for drawing the SMPTE and tiles patterns in buffers using
semi-planar YUV formats with non-subsampled chroma planes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v2:
  - Add Reviewed-by.
2023-09-08 17:42:38 +00:00
Geert Uytterhoeven
cd3b248cdc util: add NV24 and NV42 frame buffer formats
Add the missing entries for semi-planar YUV formats with
non-subsampled chroma planes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v2:
  - Add Reviewed-by.
2023-09-08 17:42:38 +00:00
Rohith Iyer
8db39ef7bb modetest: add support for writeback connector
Add writeback support to modetest with the below options:

- Passing in -a -c will now also show the writeback connector

- Dump the writeback output buffer to bitstream
  Usage: "./modetest -M msm -s <connector_id>:<widthxheight>
          -a -o <filepath>
          -P <plane_id>@<crtc_id>:<widthxheight>+0+0@RG24"

This currently supports single writeback connector.

Co-developed-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
[DB: dropped custom mode support, fixed segfault]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-09-08 16:27:39 +00:00
Jonathan Gray
ee52a88a57 amdgpu: add marketing names from Adrenalin 23.9.1 2023-09-07 01:28:25 +10:00
Jonathan Gray
0be9179f41 amdgpu: add marketing names from Adrenalin 23.7.2 2023-09-05 19:25:16 +00:00
Jonathan Gray
e194de72d3 amdgpu: add marketing names from PRO Edition 23.Q3 W7000 2023-09-05 19:25:16 +00:00
Jonathan Gray
51f3109f19 amdgpu: add marketing names from amd-5.5.1 (23.10.1) 2023-09-05 19:25:16 +00:00
Jonathan Gray
d4a7ee1a56 amdgpu: add marketing names from amd-5.4.6 (22.40.6) 2023-09-05 19:25:16 +00:00
Geert Uytterhoeven
6a961ca843 amdgpu: Use PRI?64 to format uint64_t
On 32-bit:

    ../tests/amdgpu/amdgpu_stress.c: In function ‘alloc_bo’:
    ../tests/amdgpu/amdgpu_stress.c:178:49: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Allocated BO number %u at 0x%lx, domain 0x%x, size %lu\n",
                                                   ~~^
                                                   %llx
       num_buffers++, addr, domain, size);
                      ~~~~
    ../tests/amdgpu/amdgpu_stress.c:178:72: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 6 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Allocated BO number %u at 0x%lx, domain 0x%x, size %lu\n",
                                                                          ~~^
                                                                          %llu
       num_buffers++, addr, domain, size);
                                    ~~~~
    ../tests/amdgpu/amdgpu_stress.c: In function ‘submit_ib’:
    ../tests/amdgpu/amdgpu_stress.c:276:54: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 5 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Submitted %u IBs to copy from %u(%lx) to %u(%lx) %lu bytes took %lu usec\n",
                                                        ~~^
                                                        %llx
       count, from, virtual[from], to, virtual[to], copied, delta / 1000);
                    ~~~~~~~~~~~~~
    ../tests/amdgpu/amdgpu_stress.c:276:65: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 7 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Submitted %u IBs to copy from %u(%lx) to %u(%lx) %lu bytes took %lu usec\n",
                                                                   ~~^
                                                                   %llx
       count, from, virtual[from], to, virtual[to], copied, delta / 1000);
                                       ~~~~~~~~~~~
    ../tests/amdgpu/amdgpu_stress.c:276:70: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 8 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Submitted %u IBs to copy from %u(%lx) to %u(%lx) %lu bytes took %lu usec\n",
                                                                        ~~^
                                                                        %llu
       count, from, virtual[from], to, virtual[to], copied, delta / 1000);
                                                    ~~~~~~
    ../tests/amdgpu/amdgpu_stress.c:276:85: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 9 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
      fprintf(stdout, "Submitted %u IBs to copy from %u(%lx) to %u(%lx) %lu bytes took %lu usec\n",
                                                                                       ~~^
                                                                                       %llu
       count, from, virtual[from], to, virtual[to], copied, delta / 1000);
                                                            ~~~~~~~~~~~~
    ../tests/amdgpu/amdgpu_stress.c: In function ‘parse_size’:
    ../tests/amdgpu/amdgpu_stress.c:296:24: warning: format ‘%li’ expects argument of type ‘long int *’, but argument 3 has type ‘uint64_t *’ {aka ‘long long unsigned int *’} [-Wformat=]
      if (sscanf(optarg, "%li%1[kmgKMG]", &size, ext) < 1) {
                          ~~^             ~~~~~
                          %lli
    ../tests/amdgpu/amdgpu_stress.c: In function ‘main’:
    ../tests/amdgpu/amdgpu_stress.c:378:45: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
         fprintf(stderr, "Buffer size to small %lu\n", size);
                                               ~~^     ~~~~
                                               %llu

Fix this by using the proper "PRI?64" format specifiers.

Fixes: d77ccdf3ba ("amdgpu: add amdgpu_stress utility v2")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
---
On Linux/amd64, the format strings in the resulting binary are
unchanged.

v3:
  - Add Reviewed-by,

v2:
  - Use PRI?64 to unbreak 64-bit build.
2023-09-04 09:31:55 +02:00
Geert Uytterhoeven
ca041d5fe6 amdgpu: Fix pointer/integer mismatch warning
On 32-bit:

    ../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
    ../amdgpu/amdgpu_bo.c:554:13: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
           cpu < (void*)((uintptr_t)bo->cpu_ptr + bo->alloc_size))
                 ^

Indeed, as amdgpu_bo_info.alloc_size is "uint64_t", the sum is
always 64-bit, while "void *" can be 32-bit or 64-bit.

Fix this by casting bo->alloc_size to "size_t", which is either
32-bit or 64-bit, just like "void *".

Fixes: c6493f360e ("amdgpu: Eliminate void* arithmetic in amdgpu_find_bo_by_cpu_mapping")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
---
v2:
  - Add Reviewed-by.
2023-09-04 09:31:36 +02:00
Simon Ser
7bdb135f0c build: bump version to 2.4.116
Signed-off-by: Simon Ser <contact@emersion.fr>
2023-08-23 11:57:39 +02:00
Dor Askayo
18644eb64f nouveau: add interface to make buffer objects global
This is useful for when GEM handles are exported and may be shared
between multiple buffer objects without going through other libdrm
interfaces.

Signed-off-by: Dor Askayo <dor.askayo@gmail.com>
Reviewed-by: Karol Herbst <git@karolherbst.de>
2023-08-17 21:09:55 +00:00
James Zhu
3bc3cca230 xf86drm: use drm device name to identify drm node type
Currently drm node's minor range is used to identify node's type.
Since kernel drm uses node type name and minor to generate drm
device name, It will be more general to use drm device name to
identify drm node type.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2023-08-16 09:28:59 -04:00
James Zhu
7130cb163e xf86drm: update DRM_NODE_NAME_MAX supporting more nodes
Current DRM_NODE_NAME_MAX only can support up to 999 nodes,
Update to support up to 2^MINORBITS nodes.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2023-08-16 09:28:57 -04:00
Simon Ser
c6013245ce xf86drm: add drmSyncobjEventfd
This is a wrapper for DRM_IOCTL_SYNCOBJ_EVENTFD.

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-07-27 16:10:41 +02:00
Simon Ser
431becd4e0 Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.

Generated using make headers_install.
Generated from drm-next branch commit 52920704df878050123dfeb469aa6ab8022547c1

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-07-27 15:57:59 +02:00
Simon Ser
4de32c8609 xf86drm: drop control nodes implementation
Drop support for control nodes. The kernel never returns such
nodes. Stop trying to detect and handle them, and always return
an error when a caller tries to open them.

The header is left untouched to avoid breaking libdrm's API.

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-07-26 08:26:05 +00:00
Simon Ser
4b51e34d1a xf86drm: bump DRM_MAX_MINOR to 64
This is what the kernel uses (see drm_minor_alloc).

Signed-off-by: Simon Ser <contact@emersion.fr>
2023-07-26 08:22:27 +00:00
Xaver Hugl
cc8c223c9e xf86drmMode: constify drmModeCrtcSetGamma
The data is never modified, so it should be const

Signed-off-by: Xaver Hugl <xaver.hugl@gmail.com>
2023-07-20 11:01:48 +00:00
Ruijing Dong
5e0b1df4fb tests/amdgpu/vcn: fix session buffer issue for vcn1-vcn3
issue:
   in vcn1-vcn3, session buffer was not truly added, it shows
   decoding creation commands cannot be sent multiple times.

problem:
   session buffer has to be the first buffer sending out.
   Otherwise, system could assume session buffer doesn't
   exist.

solution:
   move session buffer sending sequence to be the first one.

Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
2023-07-17 08:40:11 -04:00
Saleemkhan Jamadar
7d7a9901bd tests/amdgpu/vcn:update decoder unit test
update decoder unit test with session context buffer for VCN v1 to v4

v2: remove multiple checks for vcn4 (Ruijing Dong)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
2023-07-06 14:03:15 -04:00
Marek Olšák
98e1db5011 amdgpu: add an environment variable that overrides the context priority
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2023-05-11 12:53:29 -04:00
Ruijing Dong
7784d57166 tests/amdgpu/vcn: fix drm test failure
1. fixed an issue that drm test vcn3/4 encoding test
   could cause VCN engine stuck.
2. adding missing or errous encoding ib package members.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
2023-05-11 11:09:38 -04:00
Ruijing Dong
03d18b44db tests/amdgpu/vcn: change vbv_buffer name to input
It is input buffer instead of vbv_buffer.
Correct its name.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
2023-05-11 11:09:32 -04:00
Luben Tuikov
28d9a3c4fb tests/amdgpu: Allow to exclude a test or a suite of tests
Add the command line argument -e s[.t] to exclude (disable) suite s, or to
exclude suite s test t.

This is useful for instance to run the Basic Suite, but disable the GPU reset
test, on the command line, like this:

    amdgpu_tests -s 1 -e 1.13

This option can be specified more than once on the command line, in order to
exclude more than one suite and/or suite and test combination from being run.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2023-03-24 13:47:21 +00:00
Luben Tuikov
41121251de tests/amdgpu: Add all 9 options to the help output
Add -s and -t to the help output, as well as sort
the options output alphabetically.

v1: Fix a spelling in the subject of this commit.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2023-03-24 13:47:21 +00:00
Luben Tuikov
25e08fd9ae tests/amdgpu: Fix Usage string
Fix the Usage: string on -h (help) in amdgpu_tests.c,
so brackets match, and remove mismatched angle brackets.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2023-03-24 13:47:21 +00:00
Jonathan Gray
bf867aed27 amdgpu: add marketing names from amd-5.4.3 (22.40.3) 2023-03-24 13:21:42 +00:00
Pierre-Eric Pelloux-Prayer
466e3c0c24 amdgpu: remove va::dev member
This is unused so drop it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2023-03-24 11:25:10 +01:00
jie zhang
d1681af054 test/amdgpu/hotunplug: add apu check for hotplug test
For apu, it is integrated with cpu.
So hotplug test should be unnecessary for it.

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
2023-03-17 17:24:14 +00:00
Jan Beich
332809f3ee meson: drop pthread-stubs dependency on BSDs
pthread-stubs >= 0.4 simply passes -pthread which is similar to what
dependency('threads') returns. And make it a private dependency
for subprojects even on Linux.

Reviewed-by: Emmanuel Vadot <manu@FreeBSD.org>
2023-02-10 14:58:52 +00:00
Yi Xie
c6d6dce99f tests/util: Add vkms driver
Add an entry for the "vkms" driver, so that the test utilities work with
the vkms driver without passing the -M argument.

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Yi Xie <yixie@google.com>
2023-02-10 05:22:52 +00:00
Simon Ser
ee558cea20 build: bump version to 2.4.115
Signed-off-by: Simon Ser <contact@emersion.fr>
2023-02-09 12:55:44 +01:00
Simon Ser
6c4c48e61c xf86drm: add support for printing AMD GFX11 modifiers
See kernel commit 543036a2de71 ("drm/amd: Add GFX11 modifiers support
to AMDGPU (v3)").

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-09 10:41:58 +01:00
Alex Deucher
0e2c7d0571 amdgpu: add some additional marketing names
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-03 11:20:38 -05:00
Alex Deucher
bdcd492328 amdgpu: add marketing names from amd-5.4 (22.40)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-03 11:20:27 -05:00
Simon Ser
64d6fabaa1 xf86drm: fix warning in drmGetFormatModifierNameFromVivante()
Fixes the following warning:

    ../xf86drm.c: In function ‘drmGetFormatModifierNameFromVivante’:
    ../xf86drm.c:614:14: warning: passing argument 1 of ‘asprintf’ from incompatible pointer type [-Wincompatible-pointer-types]
      614 |     asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression);
          |              ^~~~~~~~~~~~
          |              |
          |              const char **
    In file included from ../xf86drm.c:34:
    /usr/include/stdio.h:396:40: note: expected ‘char ** restrict’ but argument is of type ‘const char **’
      396 | extern int asprintf (char **__restrict __ptr,
          |                      ~~~~~~~~~~~~~~~~~~^~~~~
    ../xf86drm.c:615:12: warning: return discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
      615 |     return mod_vivante;
          |            ^~~~~~~~~~~

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-12-21 16:42:44 +01:00
Philipp Zabel
874af99463 xf86drm: Add support for decoding Vivante format modifiers
Allow applications to pretty-print Vivante format modifiers.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-11-30 18:18:17 +01:00
Philipp Zabel
329eebcf32 drm_fourcc: sync drm_fourcc with latest drm-next kernel
Update drm_fourcc.h to include latest changes from drm-next branch.
This brings in sub-8bpp formats, AVUY and XVUY 8:8:8:8, and
Vivante tile-status and compression modifiers.

Generated using make headers_install.
Generated from drm-next branch commit 077bd80083ab

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-11-30 18:18:17 +01:00
Matt Roper
07dae1d108 intel: Eliminate need to keep adding PCI IDs
The Intel-specific code in libdrm is continually updated with new PCI
IDs for each new platform so that we can recognize the IP version
properly.  However this is mostly a pointless exercise; none of the
Intel code in libdrm is conditional on IP versions above 8.  If we just
treat any future unrecognized Intel platforms as IP version 8, we should
get the same behavior without the need for continued PCI ID updates.

Note that the intel_decode tool probably _should_ have conditions on
newer IP versions, but it was last updated for gen8 and has been
bitrotting from gen9 onward.  This change won't make the tool behave any
more incorrectly than it already does today.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2022-11-22 16:00:57 -08:00
Saleemkhan Jamadar
e699b28b54 tests/amdgpu/jpeg: enable unit test for jpeg 4
Enable decode unit test for jpeg4.

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
2022-11-11 09:57:01 -05:00
Lang Yu
0a8fad5f5c tests/amdgpu: use AMDGPU_TIMEOUT_INFINITE to query fence
We need to wait longer when running on emulator.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
2022-11-09 14:57:14 +08:00
Simon Ser
b9ca37b313 build: bump version to 2.4.114
Signed-off-by: Simon Ser <contact@emersion.fr>
2022-11-03 09:33:36 +01:00
Simon Ser
e832f5b0b8 modetest: use dumb buffer helpers
Signed-off-by: Simon Ser <contact@emersion.fr>
2022-11-02 18:46:38 +01:00
Simon Ser
ce22377778 modetest: use sized integers in struct bo
Use the same size types as the kernel.

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-11-02 18:46:15 +01:00
Simon Ser
fc6bc66c64 modetest: drop unused offset field in struct bo
Signed-off-by: Simon Ser <contact@emersion.fr>
2022-11-02 18:45:42 +01:00
Simon Ser
3be3b1a83f xf86drmMode: add helpers for dumb buffers
Up until now, DRM clients had to hand-roll their code to create,
destroy and map dumb buffers. This is slightly inconvenient,
a bit error-prone, and not easily discoverable.

Introduce wrappers for these operations, just like we have for
other KMS IOCTLs.

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-10-27 22:18:22 +02:00
Simon Ser
82b2b1e898 amdgpu: silence uninitialized variable warning
The compiler isn't smart enough to tell that this can't happen:

    [30/74] Compiling C object amdgpu/libdrm_amdgpu.so.1.0.0.p/amdgpu_bo.c.o
    In file included from ../amdgpu/amdgpu_internal.h:32,
                     from ../amdgpu/amdgpu_bo.c:39:
    ../xf86atomic.h: In function ‘amdgpu_find_bo_by_cpu_mapping’:
    ../xf86atomic.h:47:54: warning: ‘bo’ may be used uninitialized [-Wmaybe-uninitialized]
       47 | # define atomic_inc(x) ((void) __sync_fetch_and_add (&(x)->atomic, 1))
          |                                                      ^
    ../amdgpu/amdgpu_bo.c:536:27: note: ‘bo’ was declared here
      536 |         struct amdgpu_bo *bo;
          |                           ^~

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-23 17:47:24 +02:00
Alex Deucher
a81b9ab8f3 amdgpu: Add a default marketing name if none is found
Apparently quite a few apps use this API to get the GPU
name and end up with NULL as the GPU name.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-17 16:19:44 -04:00
Alex Deucher
613cc945b3 amdgpu_ids: add MI marketing names
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-17 16:19:44 -04:00
Alex Deucher
2ca30c7e4f amdgpu.ids: update to the latest marketing name
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-17 16:19:44 -04:00
Alex Deucher
7e4aa50e3d amdgpu.ids: sort the file
So the list is in numeric order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-17 16:19:44 -04:00
Alex Deucher
74b7b618dc amdgpu.ids: use consistent formatting for RID
Use two digits for the revision id.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-17 16:19:44 -04:00
Simon Ser
ffb9375a50 xf86drm: handle DRM_FORMAT_BIG_ENDIAN in drmGetFormatName()
This bit can be added to a DRM format to indicate that it's
big endian instead of little endian.

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-10-17 12:03:50 +02:00
Marco Felsch
e08a22dc43 tests/util: add imx-lcdif driver
This makes the test utilities work with the i.MX LCDIFv3 driver
without the necessity of using the -M argument.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-10-06 18:38:29 +02:00
Simon Ser
0bd3e4e94f build: automatically disable Intel if pciaccess is not found
Wire up the pciaccess dep to the intel option. This automatically
skips the dep if intel is explicitly disabled, fails if intel is
explicitly enabled and it's not found, and disables intel if it's
set to auto and the dep is not found.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2022-10-03 09:03:30 +02:00
Simon Ser
2df9cc28c0 intel: move declarations to top in drm_intel_gem_bo_unreference()
Fixes the following warning:

    [65/74] Compiling C object intel/libdrm_intel.so.1.0.0.p/intel_bufmgr_gem.c.o
    ../intel/intel_bufmgr_gem.c: In function ‘drm_intel_gem_bo_unreference’:
    ../intel/intel_bufmgr_gem.c:1388:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
     1388 |         drm_intel_bufmgr_gem *bufmgr_gem =
          |         ^~~~~~~~~~~~~~~~~~~~

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2022-10-03 08:54:43 +02:00
Jordan Justen
e0df5fce89
include/drm/i915_drm.h: Update from Linux v6.0-rc7
Generated from the Linux v6.0-rc7 tag with a sha1 of
f76349cf41451c5c42a99f18a9163377e4b364ff.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2022-09-28 17:04:12 -07:00
Jordan Justen
e2504b921f
include/drm/drm_fourcc.h: Update from Linux v6.0-rc7
Generated from the Linux v6.0-rc7 tag with a sha1 of
f76349cf41451c5c42a99f18a9163377e4b364ff.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2022-09-28 17:03:04 -07:00
Eli Schwartz
474894ed17
meson: fast-fail on unsupported OSes
It's not worth even attempting to configure anything on OSes where there
is no DRM to have a userspace library for.

This failure message can be useful in e.g. the case where libdrm is an
optional wrap fallback in another project.

Signed-off-by: Eli Schwartz <eschwartz93@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2022-09-11 01:49:42 -04:00
Simon Ser
fb5c0c301a build: bump to version 2.4.113
Signed-off-by: Simon Ser <contact@emersion.fr>
2022-08-31 16:38:38 +02:00
Simon Ser
e761875fc5 tests/modetest: use drmGetFormatName()
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marius Vlad <marius.vlad@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
2022-08-31 06:40:49 +00:00
Simon Ser
baa4b8cafc xf86drm: add drmGetFormatName()
Same as drmGetFormatModifierName() but for formats.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marius Vlad <marius.vlad@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
2022-08-31 06:40:49 +00:00
Matt Roper
03e0ab4d88 intel: Hook up new platforms IDs
In commit 98794e2a0d ("lib: sync i915_pciids.h with kernel") we
resynchronized the PCI header with the kernel to bring in the
definitions for several new platforms.  But before those IDs will be
recognized, we still need to hook them up in the libdrm chipset code as
well.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/5416
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2022-08-30 19:32:48 +00:00
Sui Jingfeng
33f0009de5 meson: auto-enable etnaviv on arm, arc, mips and loongarch architectures
There is a Vivante GC1000 gpu in LS2K1000 and LS7A1000.

LS7A1000 is a bridge chip made by Loongson corporation
which act as north and/or south bridge of loongson's
desktop and server level processor. It is equivalent
to RS780E or something like that. In fact, the company
use RS780E as bridge of LS3A3000 at its early stage,
but as RS780E is out of stock long long time ago, the
company have to made one by themself. More details can
be read from its user manual[1].

This bridge chip typically use with LS3A3000, LS3A4000
and LS3A5000.

LS3A3000 is 4 core 1.45gHz mips64r2 compatible cpu.
LS3A4000 is 4 core 1.8gHz mips64r5 compatible cpu.
LS3A5000 is 4 core 2.5gHz loongarch cpu, the company
acclaim that loongarch a new archtecture with its
instruction set is released[2].

LS2K1000 is a double core 1.0Ghz mips64r2 compatible SoC[3].

we need to enable it to test and developing driver on above
listed archtecture.

[1] https://loongson.github.io/LoongArch-Documentation/Loongson-7A1000-usermanual-EN.html
[2] https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.html
[3] https://wiki.debian.org/InstallingDebianOn/Lemote/Loongson2K1000

Signed-off-by: Sui Jingfeng <15330273260@189.cn>

[Eric: rebase over meson changes, add ARM & ARC architectures, and drop
"experimental" from the description]
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2022-08-30 16:03:36 +01:00
Matt Turner
d4bb19e2c4 intel: Avoid aliasing violation
../intel/test_decode.c: In function ‘compare_batch’:
../intel/test_decode.c:109:39: error: dereferencing type-punned pointer might break strict-aliasing rules [-Werror=strict-aliasing]
  109 |         out = open_memstream((char **)&ptr, &size);
      |                                       ^~~~
cc1: some warnings being treated as errors

The fix is simple: just declare `ptr` as a `char *` to begin with.
2022-08-23 22:54:15 +00:00
Eric Engestrom
3ff3d59ed9 atomic: fix atomic_add_unless() fallback's return value
According to the kernel documentation:
  Returns non-zero if @v was not @u, and zero otherwise.

Fixes: 63fc571863 ("atomic: add atomic_add_unless()")
Closes: https://gitlab.freedesktop.org/mesa/drm/issues/17
Signed-off-by: David Shao <davshao@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>

[Eric: fix its callers to maintain current behaviour]
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2022-08-23 22:49:34 +00:00
Matthieu Herrb
cf54ebf6cf Remove unused 3rd parameter to open(2)
The 3rd parameter is only used with the O_CREAT flag

Signed-off-by: Matthieu Herrb <matthieu@herrb.eu>
2022-08-23 22:43:38 +00:00
Eric Engestrom
a64a176cfd meson: simplify some more build options by using features
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-23 18:52:16 +01:00
Eric Engestrom
26eb15165b meson: convert auto combos into proper features
Allows users to easily enable everything (eg. packagers), or select just
the drivers they want with something like:
    -D auto-features=disabled -D amdgpu=enabled

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-23 18:52:16 +01:00
Eric Engestrom
4a7706b2a4 ci: drop dead script since e722ba9f67
Noticed-by: Michel Daenzer <michel@daenzer.net>
2022-08-23 17:54:58 +01:00
Eric Engestrom
502f64cb30 meson: fix value of auto for a bunch of drivers
You can't have an error if your driver is requested by you're missing
a dep, but then happily build that driver without the dep in `auto`.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2022-08-22 21:06:22 +01:00
Eric Engestrom
3e3874d50d ci: bump images tags to take !255 into effect
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-22 18:53:08 +01:00
Eric Engestrom
f32db9d354 ci/freedesktop: bump python version of docutils package as 3.8 no longer exists 2022-08-22 18:50:04 +01:00
Eric Engestrom
1637d8b020 ci: fix the tested meson version
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-22 17:41:18 +01:00
Eric Engestrom
24163f40d3 ci: remove system meson before installing the pip one
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-22 17:40:42 +01:00
Simon Zeni
46d1e99a5d build: make tests optional
Building the project as a meson subproject, meson inherits the warning level
from the parent project. Making the tests optional bypasses that issue and
reduces build time.

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-08-18 09:58:41 +00:00
Likun Gao
003eb2a554 tests/amdgpu: add sdma slow copy linear hang test
Issue slow copy linear for sdma to trigger SDMA hang test.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2022-08-15 06:10:15 +00:00
Likun Gao
3c04686ae5 tests/amdgpu: add sdma corrupted header hang test
Issue corrupted header for sdma to trigger SDMA hang test.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2022-08-15 06:10:15 +00:00
Flora Cui
f1b897ec83 tests/amdgpu: add dispatch/draw test for gfx11
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2022-08-15 06:10:15 +00:00
Flora Cui
cc3c80c6ae tests/amdgpu: refactor dispatch/draw test
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2022-08-15 06:10:15 +00:00
Hawking Zhang
176e6ce6f3 tests/amdgpu: skip gfx CE subtest in gfx11
CE is not available in gfx11

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
2022-08-15 06:10:15 +00:00
Matt Roper
98794e2a0d lib: sync i915_pciids.h with kernel
This synchronizes with kernel commit 7835303982d1 ("drm/i915/mtl: Add
MeteorLake PCI IDs") to bring in the missing PCI IDs for several recent
platforms.

These days adding PCI IDs to libdrm doesn't really matter for real-world
system usage.  However there are still a few driver testing situations
where they're needed (such as the IGT dma-buf tests that still rely on
libdrm's bufmgr code).  At some point we should probably break that
final IGT dependency on libdrm so that these PCI ID resyncs won't be
necessary anymore, but that hasn't happened yet.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/5416
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2022-08-03 22:48:27 +00:00
Stephan Lachnit
40fcca248b
build: set c_std to c11
Signed-off-by: Stephan Lachnit <stephanlachnit@debian.org>
2022-07-25 17:37:32 +02:00
Eric Curtin
512c8a88ca tests/util: Add simpledrm driver
Add an entry for the "simpledrm" driver, so that the test utilities
work with the simpledrm driver without passing the -M argument.

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Eric Curtin <ecurtin@redhat.com>
2022-07-22 13:25:53 +01:00
Ruijing Dong
6070e6a798 tests/amdgpu/vcn: add unified queue support in vcn4
add unified queue headers on the existing tests.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
2022-07-20 18:23:59 -04:00
Ruijing Dong
8be3042864 tests/amdgpu/vcn: align comments for AMDGPU_HW_IP_VCN_ENC
From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support both encoding
and decoding jobs.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
2022-07-20 18:23:55 -04:00
James Zhu
e83aaae15e tests/amdgpu: enable vcn swRing test for version 4 and later
Enable vcn decode software ring test for version 4 and later.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
2022-07-20 18:23:45 -04:00
Alex Deucher
e214a6a6e8 amdgpu: update marketing names for 22.20
Add new marketing names.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-18 17:08:21 -04:00
Simon Ser
60cf6bcef1 build: bump version to 2.4.112
Signed-off-by: Simon Ser <contact@emersion.fr>
2022-07-06 10:43:38 +02:00
Simon Ser
3ee004ef52 xf86drmMode: introduce drmModeConnectorGetPossibleCrtcs
Nowadays, users don't really care about encoders except for retrieving
the list of CRTCs compatible with a connector. Introduce a new function
so that users no longer need to deal with encoders.

This is a re-do of [1], but with a slightly different API.

Signed-off-by: Simon Ser <contact@emersion.fr>

[1]: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/102
2022-07-02 22:22:49 +02:00
Simon Ser
0427c1f669 tests: use drmModeGetConnectorTypeName
Drop util_lookup_connector_type_name and use
drmModeGetConnectorTypeName instead.

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-07-02 20:13:29 +00:00
Simon Ser
50f8d51773 xf86drmMode: introduce drmModeGetConnectorTypeName
User-space often needs to print the name of a connector type.
When a new connector type is added, all user-space programs need
to be updated to support the new connector type.

Expose a function to get a connector type name in libdrm.

The names are taken from the kernel [1].

[1]: https://cgit.freedesktop.org/drm/drm/tree/drivers/gpu/drm/drm_connector.c?h=4fc8cb47fcfdc93e274a1291757e478df4f9c39b#n83

Signed-off-by: Simon Ser <contact@emersion.fr>
2022-07-02 20:13:29 +00:00
Saleemkhan Jamadar
f7828dc180 tests/amdgpu/vcn:vcn encoder unit test
Add support for vcn encoder unit test

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
2022-06-11 12:13:26 -04:00
Sathishkumar S
0b21fcb214 tests/amdgpu: fix decode test failure on VCN2.5
For VCN2.5 wrong index was chosen, fix it.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2022-06-11 12:13:03 -04:00
Simon Ser
f83ad09dc0 xf86drmMode: constify drmModeAtomicReq functions
This acts as an additional ABI guarantee, and improves
documentation for users.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com>
2022-06-09 11:44:38 +02:00
Simon Ser
3bede5dbbc gen_table_fourcc: strip _MODIFIER suffix for INVALID
This is the only modifier printed with a "_MODIFIER" suffix. It
looks inconsistent when callers already print this word (e.g.
"modifier: INVALID_MODIFIER").

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marius Vlad <marius.vlad@collabora.com>
2022-06-08 14:02:48 +02:00
Dave Airlie
f801b07a60 build: bump version to 2.4.111
Signed-off-by: Dave Airlie <airlied@redhat.com>
2022-06-03 14:04:41 +10:00
Guchun Chen
362a93d1fb tests/amdgpu: use appropriate ring for different asics
Use compute ring in case of no gfx ring.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
2022-05-26 21:02:33 +08:00
Alex Deucher
3f266e57d0 amdgpu: add marketing names from 22.10
Add new marketing names

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-13 13:20:14 -04:00
Eleni Maria Stea
ae6d81da20 tests/modeprint: fix argument type
Replaced the type PRId64 with PRIu64 in a printf as the argument was
unsigned to fix the related compiler warning.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-05-09 15:54:20 +03:00
Eleni Maria Stea
4caec56fb8 modeprint, modetest, proptest: cast __u64 to uint64_t
It seems that __u64 values are defined differently across systems. In
glibc it's defined as unsigned long, in Linux kernel headers
(int-ll64.h) as unsigned long long, and on FreeBSD as uint64_t so it
matches glibc. A temporal solution is to cast all __u64 values to
uint64_t to avoid warnings on Linux, but ideally we'd like a better fix
in the future.

See also: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/212
for discussion.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
2022-05-09 15:53:56 +03:00
Eleni Maria Stea
c907d4ade1 xf86drm.c: fix C99 warning
Moved declaration to the top to resolve C99 compliance warning.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-05-09 14:56:11 +03:00
Karol Herbst
678a32b98f nouveau: add ioctl wrapper to check for dead channels
v2: explicitly set nr_push to 0 as well

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-03 11:23:30 +00:00
Tejas Upadhyay
d95b12e7e3 intel: Add support for RPLP
Add RPLP platform support and PCIIDs

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
2022-04-21 23:04:33 +05:30
Matt Turner
62e25c8baa man: Add formatting to drmModeGetConnector reference
Signed-off-by: Matt Turner <mattst88@gmail.com>
2022-04-19 13:13:13 -07:00
Matt Turner
37d50e1cbf man: Fix some typos
Signed-off-by: Matt Turner <mattst88@gmail.com>
2022-04-19 13:10:50 -07:00
Daniel Stone
2b997bb4bb libkms: Remove libkms completely
libkms was a very early attempt at a KMS management library, that only
got as far as handling requests to create buffers. It has since been
superseded by GBM in doing this, which everyone uses, unlike libkms
which no-one uses.

Remove it from the tree to avoid any confusion.

Signed-off-by: Daniel Stone <daniels@collabora.com>
2022-04-15 22:40:29 +00:00
Flora Cui
85393adb12 tests/amdgpu: add dispatch test for gfx10
Signed-off-by: Flora Cui <flora.cui@amd.com>
2022-03-30 16:39:02 +08:00
Flora Cui
f2314a4871 tests/amdgpu: add draw test for gfx10
Signed-off-by: Flora Cui <flora.cui@amd.com>
2022-03-30 16:39:02 +08:00
Lu Jiacheng
7c28f52830 tests/amdgpu: Add test suite CP DMA 2022-03-09 15:05:04 +00:00
Alex Deucher
2e91f124a3 amdgpu: add marketing names from 21.50
Add new marketing names

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02 11:51:08 -05:00
Alex Deucher
dce623f525 test/amdgpu: only disable deadlock tests on asics without GPU reset
Switch the logic to only disable the tests for asics which don't
have GPU reset support.  This way we don't need to update it
every time we add a new asic which does support it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02 16:10:41 +00:00
Andrey Grodzovsky
b47c057d69 tests/amdgpu/hotunplu: Enable hotunplug tests.
I tested with latest amd-staging-drm-next and after minor
fix for me all the testys pass. I bumped libdrm minor version
for this.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
2022-03-01 12:57:39 -05:00
Thierry Reding
8376362245 tests: tegra: Add VIC flip test
This test will attempt to use the VIC to blit one surface to another
and perform a vertical flip.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
8c4887b4e1 tests: tegra: Add VIC blit test
This test will attempt to use the VIC to blit from one surface to
another.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
e9ddc93d8e tests: tegra: Add VIC clear test
This test will attempt to use VIC to clear a surface.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
26b872ebad tests: tegra: Add VIC 4.2 support
The Video Image Composer (VIC) 4.2 can be found on NVIDIA Tegra194 SoCs.
It uses a different class (C5B6) that is slightly incompatible with the
class found on earlier generations, although it is backwards compatible
with the class implemented on Tegra186 (B1B6).

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
5217c5c747 tests: tegra: Add VIC 4.1 support
The Video Image Composer (VIC) 4.1 can be found on NVIDIA Tegra186 SoCs.
It uses a different class (B1B6) that is slightly incompatible with the
class found on earlier generations.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
fa5dc0c925 tests: tegra: Add VIC 4.0 support
The Video Image Composer (VIC) 4.0 can be found on NVIDIA Tegra210 SoCs.
It uses a different class (B0B6) that is slightly incompatible with the
class found on earlier generations.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 16:06:49 +01:00
Thierry Reding
8215b29832 tests: tegra: Add VIC 3.0 support
The Video Image Composer (VIC) 3.0 can be found on NVIDIA Tegra124 SoCs.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:17 +01:00
Thierry Reding
2ddf703bc3 tests: tegra: Add VIC support
Implement a small abstraction interface to allow different versions of
VIC to be used transparently. An implementation will be chosen based on
the VIC version number reported by the DRM_TEGRA_IOCTL_OPEN_CHANNEL
IOCTL.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:15 +01:00
Thierry Reding
b707a71654 tests: tegra: Add syncpoint timeout test
This test can be used to purposefully trigger a job timeout.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:12 +01:00
Thierry Reding
637d6a46d3 tests: tegra: Add syncpt-wait test
This is a very simple sanity test to check whether or not a syncpt can
be incremented by a host1x client. This uses gr2d on Tegra20 through
Tegra114 and VIC on Tegra124 and later.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:11 +01:00
Thierry Reding
8f8e54d688 tests: tegra: Add gr2d-fill test
This test uses the IOCTLs for job submission and fences to fill a sub-
region of the screen to a specific color using gr2d.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:09 +01:00
Thierry Reding
37fbc4c892 tests: tegra: Add helper library for tests
This library provides helpers for common functionality needed by test
programs.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:06 +01:00
Thierry Reding
55bc688f11 tegra: Add syncpoint APIs
These new functions can be used to allocate and free syncpoints, as well
as wait for a syncpoint threshold to be reached. Jobs can also be waited
on if a syncpoint was attached to them.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:04 +01:00
Thierry Reding
4c18828e16 tegra: Add job and push buffer APIs
These new functions can be used to create a job on a given channel, add
commands to the job using its push buffer and submit the job.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:02 +01:00
Thierry Reding
b77af8ece6 tegra: Add channel APIs
These new functions can be used to open a channel to a given engine, map
and unmap buffer objects to that channel, and close the channel.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:40:01 +01:00
Thierry Reding
dece59037d tegra: Include private.h in list of source files
This makes sure that the proper dependencies are created and that the
file is distributed.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:59 +01:00
Thierry Reding
5f920e61c8 tegra: Update for new UABI
This new UABI is a more modern version that works better with both old
and recent chips.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:57 +01:00
Thierry Reding
37e9695d51 tegra: Install tegra-openclose test
Allow this simple test to be installed so that it can easily be run on a
target device.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:55 +01:00
Thierry Reding
69fa0dd940 tegra: Make API more consistent
Most functions in libdrm_tegra take as first parameter the object that
they operate on. Make the device and buffer object creation functions
follow the same scheme.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:53 +01:00
Thierry Reding
abe27b1757 tegra: Add PRIME support helpers
These helpers facilitate exporting and importing buffer objects to and
from PRIME file descriptors.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:15 +01:00
Thierry Reding
f7a77f6993 tegra: Add flink helpers
Add helpers to export and import buffer objects via flink names.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:09 +01:00
Thierry Reding
1842707183 tegra: Fix mmap() of GEM buffer objects
Store 64-bit offset values and use libdrm's built-in drm_mmap() function
instead of mmap() to ensure the full 64-bit offset is used.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:39:06 +01:00
Thierry Reding
e44e781603 tegra: Extract common buffer object allocation code
All of the buffer object allocation functions use the same boilerplate
code. Move that code into a separate function that can be reused.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:38:21 +01:00
Thierry Reding
bec2a28e98 tegra: Remove unused IOCTL implementations
The DRM_TEGRA_GEM_{GET,SET}_FLAGS and DRM_TEGRA_GEM_{GET,SET}_TILING
IOCTLs were badly designed and have since been obsoleted by framebuffer
modifiers. Remove these implementations to make it clear their usage is
discouraged.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 15:38:18 +01:00
Thierry Reding
bca42ae004 tegra: Indent according to .editorconfig
Reindent the sources according to the settings found in the newly added
.editorconfig.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-23 14:41:16 +01:00
Sathishkumar S
d13ab997f5 tests/amdgpu: enable vcn test based on ip query
family_id checks can be removed and instead use ip major/minor version

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2022-02-19 18:10:01 -05:00
Sathishkumar S
1d92f32741 tests/amdgpu: enable jpeg test based on ip query
enable jpeg test if ip query is successful and avoid family_id
based checks, instead use ip major/minor version

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2022-02-19 18:09:53 -05:00
Samuel Pitoiset
56f81e6776 build: bump version to 2.4.110
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2022-02-16 11:00:13 +01:00
Daniel Stone
79fa377c8b drm/atomic: Stable sort for atomic request de-duplication
Atomic request property lists are defined to be de-duplicated: an atomic
request can contain multiple sets for the same property on the same
object, and only the last one will take effect.

drmModeAtomicCommit already sorts the property set by object and
property ID. We were relying on qsort to also sort by cursor - i.e.
pointer value - when object and property ID are equal, however whilst
glibc does this, the sort order is explicitly undefined when the
comparator is equal. Using the pointer is also not stable on all
implementations.

Add an explicit 'cursor' member to each property set which is used as
the tie-breaker comparator.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: #46
2022-02-04 06:16:28 +00:00
Dylan Baker
7aede93ef9 meson: use summary() instead of message
It's cleaner, it's nicer looking, and it's a nice builtin.

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:20:47 -08:00
Dylan Baker
cc16120543 meson: use the modern interface for pkg.generate
This produces no differences in the generated output. I've had to
manually add `requires : 'libdrm'` to libdrm_intel, otherwise libdrm
ends up in `Requires.private` instead of `Requires`.

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:20:40 -08:00
Dylan Baker
38c568775e meson: use cc.has_function_attribute instead of open coding
It's less code, and also allows meson to short circuit for compilers is
knows don't support this.

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:08:23 -08:00
Dylan Baker
f9539d4128 meson: use cc.check_header instead of open coding
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:08:23 -08:00
Dylan Baker
52b96a6fbf meson: use more standard formatting for better readability
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:08:23 -08:00
Dylan Baker
eaf234c148 meson: switch to cc.get_supported_arguments
This is generally faster, as meson is able to parallelize the checks for
us.

This also removes the workaround for checking gcc/clang -Wno-*
arguments, which meson now handles internally so we don't need to handle
it ourselves.

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:07:55 -08:00
Dylan Baker
6b0b493555 meson: switch the meson builtin for symbol visiblity
This allows meson to check if the compiler supports gnu style symbol
visibility, and apply the appropriate flags as necessary, rather than us
adding them by hand

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2022-01-20 10:07:18 -08:00
Samuel Pitoiset
847be2651f tests/amdgpu: add a test for new CTX OP to get/set stable pstates
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2022-01-20 18:32:48 +01:00
Samuel Pitoiset
de84cdc563 amdgpu: implement new CTX OP to set/get stable pstates
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2022-01-20 18:32:46 +01:00
Samuel Pitoiset
94bc814416 amdgpu: update_drm.h for new CTX OP to set/get stable pstates
Based on agd5f/drm-next.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2022-01-20 18:32:44 +01:00
Eric Engestrom
63d06ad3c3 use standard __typeof__() instead of GNU extension typeof()
And switch to c_std=c99. This simplifies using libdrm as a meson
subproject for mesa.

v2: (dylan)
  - switch to c99 as the standard
  - Fix amdgpu security tests as well

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emma Anholt <emma@anholt.net>
2022-01-19 16:08:31 -08:00
Guchun Chen
fa80f49df8 tests/amdgpu: Add VCN test support for Biege Goby
Added Beige Goby chip id in vcn test.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-By: Veerabadhran Gopalakrishnan <Veerabadhran.gopalakrishnan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2022-01-14 09:25:18 -05:00
Tejas Upadhyay
440e2d7a34 intel: Add support for ADL-N
Add ADL-N platform support and PCIIDs

Align with kernel commit:
7e28d0b26759 ("drm/i915/adl-n: Enable ADL-N platform")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-12-21 13:54:52 +00:00
Simon Ser
287cdb0390 releasing: s/master/main/
This default branch name has been changed. Update RELEASING
accordingly.

Signed-off-by: Simon Ser <contact@emersion.fr>
2021-12-21 13:07:01 +00:00
ravitejax
0c620c5766 intel: Add support for RPLS platform
Fixes: 3d8e59ce01 ("intel: sync i915_pciids.h with kernel")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-12-21 14:59:23 +05:30
Raviteja Goud Talla
3d8e59ce01 intel: sync i915_pciids.h with kernel
Align with kernel commit:

52407c220c44c ("drm/i915/rpl-s: Add PCI IDS for Raptor Lake S")

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2021-12-16 18:20:31 +05:30
Dylan Baker
d9188a7750 meson: add override_dependency when possible
This allows consumers of libdrm as a subproject to use the simpler
`dependency('libdrm', fallback : 'libdrm')` syntax, as the libdrm build
files already tell meson that they override a dependency called
"libdrm".

Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-12-14 00:20:40 +00:00
Dylan Baker
9324e4f054 meson: use dictionary kwargs
So we don't have to duplicate the libdrm library call just to not set
the version keyword for android

Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
2021-12-14 00:20:40 +00:00
Sathishkumar S
294b9c8322 tests/amdgpu: add jpeg tests support
v2:
- remove dec create/destroy msg as its not relevant to jpeg (Leo)
- enable the test for jpeg2/jpeg3 (Leo)
- validate checksum of result (Leo)
- add appropriate comments (Leo)

v3:
- linux style function definition indent (James)
- use multiline comment delimiter (Leo)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2021-12-09 19:31:45 -05:00
Simon Ser
febfe0addd build: bump version to 2.4.109 2021-11-25 21:33:02 +01:00
Eleni Maria Stea
997edcd37f xf86drm: fix compiler warnings
Used casting to fix warnings about assigning different enum types to
variables. Used error checks in places where snprintf is called and
output might be truncated to fix gcc format-truncation warnings.

v2: Removed a change in drm.h (Simon Ser)
v3, v4: Removed unecessary braces in snprintf (Simon Ser)

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
2021-11-25 20:28:33 +00:00
Bas Nieuwenhuizen
f70e8ae835 amdgpu: Add new function to get fd.
Dual purpose:
 - The drm fd dedupe functionality confuses the radeonsi
   amdgpu winsys if radeonsi isn't the first thing opening
   the device. By exposing the fd we can detect this case.
 - For a common mesa Vulkan sync objects implementation
   with syncobj. (notable: no buffer allocation)

Both shouldn't interferece with libdrm_amdgpu functionality
though it does somewhat piece the abstraction of the library.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3424
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5630
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2021-11-23 16:02:05 +00:00
Emmanuel Vadot
b40d0a7d6c ci: Add FreeBSD support
Use qemu to do CI on FreeBSD.
Not everything is compiled as all arm aren't supported on FreeBSD.
Same thing for Nouveau.
The tests aren't enable for now as they are all failing.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
2021-11-23 08:43:46 +00:00
Emmanuel Vadot
e722ba9f67 ci: Switch freedesktop/ci-templates
This switch to the latest ci-templates.
Most of the file is taken from the one in wayland.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
2021-11-23 08:43:46 +00:00
Simon Ser
57e0b0552e xf86drm: add drmGetDeviceFromDevId
This adds a function to get a drmDevicePtr from a dev_t identifier
of a device. This is useful for Wayland that uses these to identify
devices over the protocol.

This is done by taking the implementation of drmGetDevice2, and removing
the call to fstat to find the dev_t.

Signed-off-by: Scott Anderson <scott.anderson@collabora.com>
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2021-11-19 15:30:30 +01:00
suijingfeng
dd3d6dd321 radeon: remove duplicate declaration of struct radeon_bo_manager in radeon_bo.h
Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
2021-11-12 03:55:01 +00:00
Simon Ser
d76c387125 build: bump version to 2.4.108
Signed-off-by: Simon Ser <contact@emersion.fr>
2021-11-08 17:35:03 +01:00
Luigi Santivetti
e641e2a632 xf86drm: add iterator API for DRM/KMS IN_FORMATS blobs
Add support for parsing IN_FORMATS property blobs. Providing libdrm
with this functionality helps to standardise how user-space reads
kernel blobs and decreases duplication on the client side.

drmModeFormatModifierBlobIterNext() allows the caller to view
formats and associated modifiers given a valid property blob.
An example is available inside the libdrm unit test, modetest.c.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-11-08 16:20:04 +00:00
Joshua Ashton
f256bb9afd amdgpu: Make marketing names consistent
Fixes sporadic (TM), capitalization, missing AMD suffixes and spacing.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
2021-11-04 06:03:49 +00:00
Alex Richardson
fda3d0010f Fix -Werror=format build errors on FreeBSD
On 64-bit FreeBSD targets uint64_t is generally defined as `unsigned long`
and not `unsigned long long`. Use the PRI macros to fix -Wformat.

Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-11-02 10:44:30 +00:00
Christian König
d77ccdf3ba amdgpu: add amdgpu_stress utility v2
Simple yet useful command line utility to simulate memory pressure.

Already found quite a number of problems in TTM with that.

v2: replace spaces with tabs

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2021-10-20 15:15:30 +02:00
Simon Ser
dd3655ce73 man: refer to drmCloseBufferHandle instead of DRM_IOCTL_GEM_CLOSE
This function in libdrm core wraps DRM_IOCTL_GEM_CLOSE.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
751752d264 tegra: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
bf23fe37be omap: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
53ef4b37a1 nouveau: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
7b67fec649 freedreno: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
2fda5f9b0c exynos: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
bd1f320bc0 etnaviv: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
80f8fbd488 radeon: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
7e13fe1dbf intel: use drmCloseBufferHandle
Instead of manually calling drmIoctl, use the equivalent function
from libdrm core.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Simon Ser
ef77e5e1eb amdgpu: use drmCloseBufferHandle
Instead of using a hand-rolled amdgpu_close_kms_handle function,
use the function from libdrm core, which does exactly the same
thing.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-10-06 09:03:21 +02:00
Dennis Tsiang
bd26b61cff xf86drm: Update drmGetFormatModifierNameFromArm to handle AFRC
Update drmGetFormatModifierNameFromArm function to handle AFRC
modifiers.

Signed-off-by: Dennis Tsiang <dennis.tsiang@arm.com>
2021-10-04 10:18:41 +00:00
Dennis Tsiang
d2875fe008 drm_fourcc: sync drm_fourcc with latest drm-next kernel
Update drm_fourcc.h to include latest changes from drm-next branch.
This brings in AFRC (Arm Fixed-Rate Compression) modifiers.

Generated using make headers_install.
Generated from drm-next branch commit 6880fa6

Signed-off-by: Dennis Tsiang <dennis.tsiang@arm.com>
2021-10-04 10:18:41 +00:00
Simon Ser
02ac4a0a36 xf86drmMode: simplify drm_property_type_is
No need to have two branches depending on DRM_MODE_PROP_EXTENDED_TYPE.
We can just use drmModeGetPropertyType instead.

This does introduce a slight change: previously, drm_property_type_is()
could be called with non-type flags such as IMMUTABLE. However no user
seems to do this (checked KWin/Mutter/Sway/Weston/Xorg).

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-09-27 15:02:03 +02:00
Simon Ser
bb709e6023 xf86drmMode: switch to standard inline qualifier
__inline is non-standard, inline is.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-09-27 15:01:59 +02:00
Simon Ser
e939bd1e8c xf86drmMode: make drm_property_type_is arg const
This function only needs read-only access to the property. This is
not a breaking ABI change.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-09-27 15:01:55 +02:00
Jason Ekstrand
f9c27a9e8c intel: Drop legacy execbuffer support
Execbuffer2 support was introduced to libdrm in b50964027b, 10 years
ago, and no driver has used the old execbuf path since.  There's no need
to support 10-year-old kernels.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2021-09-27 11:26:27 +00:00
Simon Ser
264e66b5e9 xf86drm: add GEM_CLOSE ioctl wrapper
We have wrappers for PRIME_HANDLE_TO_FD and PRIME_FD_TO_HANDLE,
but not for GEM_CLOSE. Add it so that callers don't need to
manually call drmIoctl.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
2021-09-27 12:57:02 +02:00
Tvrtko Ursulin
122ff0e878 intel: Do not assert on unknown chips in drm_intel_decode_context_alloc
There is this long standing nit of igt/tools/intel_error_decode asserting
when you feed it an error state from a GPU the local libdrm does not know
of.

To fix this I need a tweak in drm_intel_decode_context_alloc to make it
not assert but just return NULL (which seems an already possible return
value).

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2021-09-24 12:55:02 +00:00
José Roberto de Souza
02dd464bf6 intel: Sync pci ids
Sync libdrm with kernel, a new DG1 pci was added.
Commit 5f0d4214938d ("drm/i915/dg1: Add new PCI id")

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
2021-09-23 21:40:58 +00:00
Alex Deucher
a97f265c7d amdgpu: add new marketing name
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-20 15:10:08 -04:00
Alex Deucher
4529056e4f amdgpu: add marketing names from 21.30
Add new marketing names

Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-20 15:10:08 -04:00
ZhiJie.Zhang
d201a41d1a tests/modetest: get cursor width and height by drmGetCap
Should get cursor width and height by drmGetCap.

Signed-off-by: ZhiJie.Zhang <zhangzhijie@loongson.cn>
2021-09-02 09:26:17 +00:00
Tejas Upadhyay
a7892962e1 intel: sync ADL-S PCI IDs with kernel
Align with kernel commits:

c79b846f892d ("drm/i915/adl_s: Update ADL-S PCI IDs")
3f50033dd88a ("drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA")

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-08-24 12:49:19 +05:30
Eric Engestrom
1a4c0ec9ae xf86drm: fix mem leak in drm_usb_dev_path()
`sysfs_uevent_get()` returns a `strndup()`ed string, which must be `free()`d.

Fixes: bf63f8acdc ("libdrm: Handle usb_interface devices for usb parsing")
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2021-08-14 09:05:49 +01:00
Karol Herbst
1d29e1df8b nouveau: print bo address in the GPU/CPU vm and its size
v2: print bo->offset as 64 bit

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2021-08-04 18:27:13 +02:00
Jordan Justen
8d0fb9b3f2
libdrm: NOTE! Default branch is now main
To update your local repository to use the new default branch, these
commands may help:

$ git fetch origin
$ git checkout master
$ git branch -m main
$ git branch --set-upstream-to=origin/main
$ git remote set-head origin --auto

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2021-08-02 15:31:26 -07:00
Mario Kleiner
149b99fe54 headers: drm: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 8a02ea42bc1d4c448caf1bab0e05899dad503f74

Some changes were omitted, e.g., to nouveau_drm.h, i915_drm.h, and
msm_drm.h, as the nouveau and i915 changes looked to me as if they
could break compatibility or require other compatibility fixes to
libdrm which i can not judge. msm_drm.h broke the build, as there
are definitely changes needed to libdrm's msm support code.

The shortlog below is edited to only list what corresponds to files
that are included here, because it looked safe to me.

The changes were as follows (shortlog from
b10733527bfd864605c33ab2e9a886eec317ec39..HEAD):

Aaron Liu (1):
      drm/amdgpu: add uapi to define yellow carp series

Alex Deucher (1):
      drm/amdgpu: add INFO ioctl support for querying video caps (v4)

Christian Gmeiner (1):
      drm/etnaviv: provide more ID values via GET_PARAM ioctl.

Felix Kuehling (1):
      drm/amdgpu: Add new placement for preemptible SG BOs

Jiawei Gu (1):
      drm/amdgpu: Add vbios info ioctl interface

Lionel Landwerlin (1):
      drm: fix drm_mode_create_blob comment

Mario Kleiner (1):
      drm/fourcc: Add 16 bpc fixed point framebuffer formats.

Nirmoy Das (1):
      drm/amdgpu: remove AMDGPU_GEM_CREATE_SHADOW flag

Noralf Trønnes (1):
      drm/uapi: Add USB connector type

Radhakrishna Sripada (1):
      drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

Simon Ser (13):
      drm: improve kernel-docs in drm_mode.h
      drm: document drm_mode_get_connector
      drm: document drm_mode_modeinfo
      drm: document that user-space should force-probe connectors
      drm/doc: atomic implicitly enables other caps
      drm/doc: re-format drm.h file comment
      drm/doc: demote old doc-comments in drm.h
      drm/fourcc: fix Amlogic format modifier masks
      drm/uapi: document kernel capabilities
      drm/connector: demote connector force-probes for non-master clients
      drm: reference mode flags in DRM_CLIENT_CAP_* docs
      drm: clarify and linkify DRM_CLIENT_CAP_WRITEBACK_CONNECTORS docs
      drm: document minimum kernel version for DRM_CLIENT_CAP_*

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
2021-08-02 02:39:12 +00:00
Eric Anholt
e6fb9ccf2a meson: Don't build libkms for Android.
Nobody wants that that I know of.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-07-30 10:58:11 -07:00
Eric Anholt
a819b9ad3b meson: Build libdrm.so as an unversioned lib on Android.
Android vendor libraries don't have sonames, and libdrm.so shouldn't
either.  This lets a Mesa built against a libdrm.so built for Android
be copied directly to a Chrome OS ARC installation.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-07-30 10:58:11 -07:00
Aaron Liu
4ac7d6bf5d test/amdgpu: Bob to Alice copy should be TMZ in secure bounce test
SDMA copy from Alice to Bob is in TMZ mode. Therefore
SDMA copy back from Bob to Alice should be in TMZ mode too.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
2021-07-23 10:24:22 +08:00
Luben Tuikov
87a68fe9e4 tests/amdgpu: Fix TMZ secure bounce test
Fix the TMZ secure bounce test, in that Bob's
buffer has to be created encrypted (with the
encrypted flag set), so that when we copy from
Alice's buffer, which is also encrypted, to Bob's
buffer, the copy can be successful and the data
actually copied.

This fixes the test and it no longer fails. Tested
on Sienna Cichlid.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Aaron Liu <aaron.liu@amd.com>
Cc: Huang Rui <ray.huang@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com>
2021-07-16 12:10:06 -04:00
Bas Nieuwenhuizen
9cef5dee3c Bump version to 2.4.107
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2021-07-02 03:12:30 +02:00
Alex Deucher
ab72fde87e amdgpu: update marketing names
From 21.20 release.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-29 21:06:42 -04:00
Marius Vlad
5d97031e8a README.rst: Include some notes about syncing uapi headers
Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Marius Vlad
65d8939808 xf86drm: Add support for decoding AMLOGIC format modifiers
Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Marius Vlad
9ae8f17d56 xf86drm: Add support for decoding AMD format modifiers
Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Marius Vlad
99a0522aef xf86drm: Add support for decoding Nvidia format modifiers
Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Marius Vlad
a04b674887 xf86drm: Add a vendor function to decode the format modifier
As format modifiers can be encoded in quite complex forms, the static
table previously added is not sufficient to retrieve, extract and decode
the token formats to a human-readable string.  This patch introduces a
vendor specific callback which could be used to perform an additional
search to match up with vendor encoding scheme, which, will be used
first, before resorting to searching the static table.

With it, add support for decoding the ARM format modifiers.

Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Marius Vlad
67e911977f xf86drm: Add a human readable representation for format modifiers
Introduces two new methods to retrieve a human readable representation of a
format modifier:

drmGetFormatModifierName() - returns a format modifier as a string,
from a token modifier
drmGetFormatModifierVendor() - returns the vendor as a string, from a
token modifier

and the fourcc_mod_get_vendor macro that returns the vendor.

New format modifiers added in drm_fourcc.h uapi kernel header should be
sync'ed up with libdrm and should include a human readable
representation for that format modifier, in order to display it
correctly as a string.

That happens with the help of a python script that reads up drm_fourcc
header file and outputs a static table comprised of token modifiers
alongside a vendor table (Suggested-by Simon Ser <contact@emersion.fr>).

The reason for doing it in libdrm is to have a unified place instead of each
user of libdrm having a way to keep track of the format modifiers.

With this patch, modetest has also been modified to make use of it.

Signed-off-by: Marius Vlad <marius.vlad@collabora.com>
2021-06-22 11:16:04 +00:00
Eleni Maria Stea
f287d1990b Conditionally include <linux/limits.h> and <sys/params.h> on Linux, BSD
<linux/limits.h> should be included conditionally for Linux only, also
SPECNAMELEN used conditionally when the OS is FreeBSD requires to
include <sys/params.h>.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-06-20 14:32:33 +03:00
Eleni Maria Stea
8bc56fe0fb _WANT_KERNEL_ERRNO must be defined in FreeBSD for ERESTART to be used
In FreeBSD's errno.h ERESTART is not defined by default, only when the
user requests the pseudo-errors returned inside the kernel to be
enabled. As a result the block where drmCommandWriteRead is
called returns compile error. Defined _WANT_KERNEL_ERRNO to fix it (see
FreeBSD's /usr/include/errno.h)

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-06-20 09:20:08 +03:00
Eleni Maria Stea
90c9175c81 include <sys/types.h> in xf86drmMode when the OS is FreeBSD
<sys/types.h> need to be included in xf86drmMode.c for type u_int in
<sys/sysctl.h> (that is included when OS is FreeBSD) to be recognized.

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-06-20 09:20:08 +03:00
Bas Nieuwenhuizen
085ee3e488 amdgpu: Add vamgr for capture/replay.
In Vulkan we have extensions to assist with capture in replay in a
world where addresses are returned to the application. This involves
creating buffers at the same VA during replay as they were during
capture.

By itself libdrm_amdgpu already has support for this, but there is
the obvious failure mode that if another buffer is already allocated
at that VA things fail spectacularly. This is an actual issue as
internal buffers, like winsys images or shader binaries also
participate in the same VA allocation.

To avoid this problem applications have to create buffers which
are going to be captured with a flag, and the implementation is to
separate VA allocation for those buffers to reduce the collision risk:

"Implementations are expected to separate such buffers in the GPU address
space so normal allocations will avoid using these addresses. Apps/tools
should avoid mixing app-provided and implementation-provided addresses for
buffers created with VK_BUFFER_CREATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT,
to avoid address space allocation conflicts."

This patch implements that by adding a flag for these buffers and allocating
address space from the top of the address range instead of the bottom.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Christian König <christian.koenig@amd.com>
2021-06-15 13:08:20 +00:00
Andrey Grodzovsky
d615430c68 tests/amdgpu/hotunplug: Add hotunplug with exported fence
Disconnect device while fence is exported.
Also disable this test for sytem with single GPU.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Andrey Grodzovsky
93a4708ac0 tests/amdgpu/hotunplug: Add hotunplug with exported bo test
Disconnect device while BO is exported.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Andrey Grodzovsky
b5f611cc37 tests/amdgpu/hotunplug: Add unplug with cs test.
Same as simple test but while doing cs

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Andrey Grodzovsky
d4b780a735 test/amdgpu/hotunplug: Add test suite for GPU unplug
Add plug/unplug device and open/close device file
infrastructure.
Add basic test - unplug device while device file still
open. Close device file afterwards and replug the device.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Andrey Grodzovsky
d330f68c11 test/amdgpu: Add helper functions for hot unplug
Expose close device and add open device wich preserves
test index.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Andrey Grodzovsky
ae2e2bd68a tests/amdgpu: Fix valgrind warning
Struct access after free

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com
2021-06-09 20:27:09 +00:00
Rahul Kumar
140ce56dcb amdgpu: Added product name for E9390,E9560 and E9565 dgpu
Update marketing names.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-07 10:59:19 -04:00
Lang Yu
4e178807b9 Revert "tests/amdgpu: fix bo eviction test issue"
This reverts commit a5a400c958.

Bo evict test was disabled by default per below commit.
So still keep it as disabled.

1f6a85cc test/amdgpu: disable bo eviction test by default

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01 12:56:24 +00:00
Tejas Upadhyay
4c8365183e intel: Add support for ADLP
Add ADLP platform support and PCIIDs

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-05-20 12:01:25 +00:00
Dave Airlie
77b642b6de Bump version to 2.4.106
Signed-off-by: Dave Airlie <airlied@redhat.com>
2021-05-18 13:38:07 +10:00
Karol Herbst
cfbea78fdf nouveau: add debug option to sync pushbuffer submissions
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:41:16 +02:00
Karol Herbst
91c3eb1700 novueau: document debug flags
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:41:14 +02:00
Karol Herbst
17a51b0b31 nouveau: rework debugging so we can also dump into a file
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:41:12 +02:00
Karol Herbst
c0ae9cfa00 nouveau: make debug features accessible in normal builds
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:41:10 +02:00
Karol Herbst
2f04bd2d89 nouveau: mask push buffer length pushbuf_dump
nvc0 sets the NVC0_IB_ENTRY_1_NO_PREFETCH bit on some pushbuffers

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:41:09 +02:00
Karol Herbst
52fd2a2542 nouveau: fix crash in pushbuf_dump with an unmapped bo
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2021-05-06 19:40:57 +02:00
Eric Engestrom
bf08984682 ci: use base-devel tag of archlinux image instead of base and then installing base-devel after
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-04-30 10:13:37 +02:00
Eric Engestrom
b4847d97df ci: use archlinux/archlinux docker image instead of deprecated and now removed archlinux/base
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-04-30 10:13:37 +02:00
Bas Nieuwenhuizen
40f73d0b0b Revert "xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied"
This reverts commit b362850689.

This breaks when the kernel driver does not support modifiers and the
application properly zeroes the modifiers.

Acked-by: Simon Ser <contact@emersion.fr>
2021-04-22 20:24:11 +02:00
Jinzhou Su
c7dc0465cf test/amdgpu: Add emit mem sync flag for test IB
In syncobj test, 3 threads will be created. Sometimes
the first gfx IB and the third sdma IB will use same
physical page. There will be risk that sdma engine will
read gfx IB in the same physical page. So better to flush
the cache before commit the sdma IB.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-19 14:04:22 +08:00
Huang Rui
67a64bb946 test/amdgpu: use tmz ids to check whether enable security tests
Using tmz ids that reported from kernel to decide whether enable
security tests.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2021-04-14 09:52:33 +02:00
James Zhu
3c02304c04 tests/amdgpu/vcn: update to support aldebaran
VCN is supported after AI family Arcturus.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2021-04-14 02:41:56 +00:00
Feifei Xu
7b844dabf9 tests/amdgpu:retire asic_id check on unsupported cases
Retire the asic_id check for AI family.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2021-04-12 17:46:31 +08:00
Feifei Xu
991e95fd13 tests/amdgpu: update gfx9 BufferCopy/BufferClear
buffer_load/store_format_xyzw require 64bit vgpr_a[2].
The original parameter is one u32. Modify the shader binary to
fit the 64bit parameter.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-by: Gang Long <Gang.Long@amd.com>
2021-04-09 15:11:08 +08:00
Leo Liu
6b4e956d29
Bump version to 2.4.105
Signed-off-by: Leo Liu <leo.liu@amd.com>
2021-04-07 09:54:11 -04:00
Leo Liu
1d13cc1032 amdgpu: add function of INFO ioctl for querying video caps
via the newly added uapi/amdgpu_drm interface

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-06 08:58:57 -04:00
Leo Liu
50c98335c7 amdgpu: sync up amdgpu_drm.h with latest from kernel
From drm-next:

commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7
Merge: 06debd6e1b28 8c44390d8872
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Mar 26 15:52:01 2021 +0100

    Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

    amd-drm-next-5.13-2021-03-23:

    amdgpu:
    ...

    UAPI:
    - amdgpu: Add a new INFO ioctl interface to query video capabilities
      rather than hardcoding them in userspace.  This allows us to provide
      fine grained asic capabilities (e.g., if a particular part is
      bandwidth limited, we can limit the capabilities).  Proposed userspace:
      https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
      https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
    ...

    Danvet: A bunch of conflicts all over, but it seems to compile ... I
    did put the call to dc_allow_idle_optimizations() on a single line
    since it looked a bit too jarring to be left alone.

    Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
    From: Alex Deucher <alexander.deucher@amd.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-06 08:58:54 -04:00
Simon Ser
b362850689 xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied
The kernel will always return EINVAL if modifiers are supplied but
the flag DRM_MODE_FB_MODIFIERS isn't set. That's a pretty nice
footgun.

Be a little more helpful and set the flag if the user has supplied
a modifier array.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-04-06 10:37:03 +02:00
Lang Yu
a5a400c958 tests/amdgpu: fix bo eviction test issue
On Raven2/Picasso, the default VRAM size is 2048M,
and the default GTT size is 3072M. If max_allocation
of VRAM exceeds half of GTT size, GTT memory can't
hold evicted bo from VRAM and bo in itself at the
same time. Then amdgpu_cs_list_validate will failed
with "Not enough memory for command submission" error.

NOTE:
The installed DRAM should be larger than 8GB,
if the VRAM size is 2048M.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2021-04-01 11:41:51 -04:00
Lang Yu
af871ec1a6 drm/tests/amdgpu: fix Metadata test failed issue
The unit of size_metadata is one byte not four bytes.
Enable Metadata test.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2021-04-01 11:41:49 -04:00
Simon Ser
6d821612d9 xf86drmMode: introduce drmModeGetPropertyType
We already have drm_property_type_is, but it's needlessly complicated
and doesn't cover all use-cases (requires the caller to provide a
type).

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-03-31 07:42:15 +00:00
Jinzhou Su
f5abbc3033 test/amdgpu: remove static varible in Syncobj test
In syncobj test, wait thread and signal thread create
simultaneously. The ptr for GFX IB and SDMA IP should be
operated separately. With static, there will be risk that
GFX NOP is in SDMA IB or SDMA NOP is in GFX IB, then GFX or
SDMA hang caused.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2021-03-24 11:34:04 -04:00
Ashutosh Dixit
cd3681976c intel: Keep libdrm working without pread/pwrite ioctls
The general direction at this time is to phase out pread/write ioctls and
not support them in future products. The ioctls have already been disabled
in i915 for future products. This means libdrm must handle the absence of
these ioctls. This patch does this by modifying drm_intel_gem_bo_subdata()
and drm_intel_gem_bo_get_subdata() to do the read/write using the
pread/pwrite ioctls first but when these ioctls are unavailable fall back
to doing the read/write using a combination of mmap and memcpy.

A similar solution was added to igt-gpu-tools in commit
ad5eb02eb3 ("lib/ioctl_wrappers: Keep IGT working without pread/pwrite
ioctls").

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
2021-03-22 15:22:31 -07:00
Fang Tan
52f05d3d89 meson: use library() instead of shared_library().
This allows users to select the library type (static or shared)
using the Meson -Ddefault_library built-in option.

Issue: https://gitlab.freedesktop.org/mesa/drm/-/issues/45

Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Fang Tan <tanfang@uniontech.com>
2021-03-09 16:57:32 +08:00
Alistair Delva
7d6a175990 xf86drm: fix null pointer deref in drmGetBufInfo
If info.count is large, drmMalloc() / alloca() may fail, and the
resulting null pointer is not null checked before dereference.

Issue: https://gitlab.freedesktop.org/mesa/drm/-/issues/62

Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alistair Delva <adelva@google.com>
2021-03-02 08:29:27 -08:00
Tejas Upadhyay
2e67fef5f6 intel: Add support for JSL
Add the PCI ID import for JSL.

V1 - Indentation
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2021-03-02 14:52:38 +05:30
Emil Velikov
a9bb32cfe1 xf86drm: cap number of reported devices by drmGetDevice(2)
Do as the documentation says - when devices non NULL, cap the reported
devices to max_devices. Otherwise we risk out-of-bound access
for users of the API.

v2:
 - Fix this w/o breaking the API

v3:
 - Drop local variables, flip inverted conditional (Simon)

Issue: https://gitlab.freedesktop.org/mesa/drm/-/issues/56
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-02-26 13:03:06 +00:00
Emil Velikov
06844b6eae Revert "xf86drm: cap number of reported devices by drmGetDevice(2)"
This reverts commit 8cb12a2528.

The commit fixed the OOB, yet it broke drmDevices2(0, NULL, 0) - aka we
did not return the total devices list.

Reviewed-by: Simon Ser <contact@emersion.fr>
2021-02-26 13:02:56 +00:00
Simon Ser
632f59fcbf xf86drm: warn about GEM handle reference counting
Users need to be careful when using drmPrimeHandleToFD or
drmPrimeFDToHandle directly. Mention GBM as a solution.

See [1] for an example mistake.

[1]: https://gitlab.freedesktop.org/drm/nouveau/-/issues/43#note_772661

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2021-02-26 13:01:04 +00:00
Simon Ser
523b3658aa xf86drmMode: add drmIsKMS
If a device has a primary node, it doesn't necessarily mean it's
suitable for KMS usage. For instance, render-only drivers also
expose primary nodes.

The check is extracted from Weston [1].

The motivation for this new function is two-fold:

- Avoid an unnecessary GETRESOURCES call. To check whether a
  primary node is suitable for KMS, we don't actually need to
  retrieve the object IDs we just need to check the counts.
- Avoid confusion in user-space and make sure user-space implements
  the check properly. For instance, wlroots doesn't [2]: it uses
  drmGetVersion which succeeds with render-only drivers.

[1]: https://gitlab.freedesktop.org/wayland/weston/-/blob/master/libweston/backend-drm/drm.c#L2689
[2]: a290d7a78d/backend/session/session.c (L268)

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2021-02-26 12:56:46 +01:00
Leo Liu
1225171bd5 amdgpu_drm: sync up with the latest amdgpu_drm.h based on drm-next (https://cgit.freedesktop.org/drm/drm)
What are these headers?
Adding currently missing stuff from https://cgit.freedesktop.org/drm/drm/tree/include/uapi/drm/amdgpu_drm.h based on
the latest commit there:

commit f730f39eb981af249d57336b47cfe3925632a7fd (HEAD -> drm-next, tag: drm-next-2021-02-19, origin/drm-next, origin/HEAD)
Merge: 4f8ad4045b38 81ce8f04aa96
Author: Dave Airlie <airlied@redhat.com>
Date:   Fri Feb 19 13:54:29 2021 +1000

    Merge tag 'drm-intel-next-fixes-2021-02-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Which headers go where?
From https://cgit.freedesktop.org/drm/drm/tree/include/uapi/drm/amdgpu_drm.h to
https://cgit.freedesktop.org/mesa/drm/tree/include/drm/amdgpu_drm.h

When and which headers to update?
If the kernel uapi drm header changes, the header here should be sync-ed.

When and how to update these files
The steps for generating this patch:

 - Switch to freedesktop drm-next kernel branch (https://cgit.freedesktop.org/drm/drm);
 - Install the headers via `make headers_install';
 - Copy from kernel "include/uapi/drm/amdgpu_drm.h" to libdrm "include/drm/amdgpu_drm.h";
 - generate the patch;

The commits from drm-next (https://cgit.freedesktop.org/drm/drm) are:

Mauro Carvalho Chehab (1)
c45dd3bda1c809eb120452597097e14a96b58c1f drm/amdgpu: fix some kernel-doc markups

Huang Rui(3)
6fbcb00c7984fa7d49af2c361453c0397cdea400 drm/amdgpu: add TOC firmware definition
1e483203965bdab466af0739c1edf7da07da241d drm/amdgpu: add uapi to define van gogh memory type
f7b2cdb23abf62bc3d33c2e0b0009a09412ff475 drm/amdgpu: add uapi to define van gogh series

Pierre-Eric Pelloux-Prayer(1)
16c642ec3fe9a144fbe1e97dc56f13a6308f1381 drm/amdgpu: new ids flag for tmz (v2)

Yong Zhao(1)
130c88931f6cbdb4513d307b4a13fcfff08a8041 drm/amdgpu: Improve the MTYPE comments

Signed-off-by: Leo Liu <leo.liu@amd.com>
2021-02-21 16:48:39 -05:00
Tejas Upadhyay
3b6cfb20fb intel: add INTEL_ADLS_IDS to the pciids list
This enables drm_intel_bufmgr on ADLS

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2021-02-18 10:44:10 +00:00
Tejas Upadhyay
9086ff9daf intel: sync i915_pciids.h with kernel
Align with kernel commits:

0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Landwerlin, Lionel G <lionel.g.landwerlin@intel.com>
2021-02-18 10:12:28 +00:00
Alex Deucher
869ef0e4b2 amdgpu: update marketing names
From 20.45 release.

Acked-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-15 10:07:15 -05:00
Victor Hugo Vianna Silva
a43cac24db Avoid some compiler errors for tests/util/pattern.c
- Remove one unused variable.
- Convert two int-s into 'unsigned int'.
Motivated by a failed build of Chromium.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Victor Hugo Vianna Silva <victor.vianna10@gmail.com>
2021-02-10 21:14:47 +00:00
Emil Velikov
8cb12a2528 xf86drm: cap number of reported devices by drmGetDevice(2)
Do as the documentation says - cap the number of reported devices to the
requested amount - aka max_devices. Otherwise we risk out-of-bound access
for users of the API.

Issue: https://gitlab.freedesktop.org/mesa/drm/-/issues/56
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
2021-02-10 19:29:27 +00:00
Sonny Jiang
19f0a9cb87 tests/amdgpu/vcn: clean abundant codes
Remove useless codes.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2021-01-23 15:31:00 -05:00
James Zhu
2315bcddd6 tests/amdgpu: add vcn test support for dimgrey_cavefish
add dimgrey_cavefish chip id in vcn test

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2021-01-23 15:31:00 -05:00
Tao Zhou
10377d661a tests/amdgpu: add vcn test support for navy_flounder
add navy_flounder chip id in vcn test

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
2021-01-23 15:31:00 -05:00
Fabio Estevam
5f85a6d98b tests/util: Add mxsfb-drm driver
Add an entry for the "mxsfb-drm" driver, so that the test utilities
work with the mxsfb driver without passing the -M argument.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2021-01-22 11:17:58 +01:00
Heiko Becker
62b9a3eee9 meson: Also search for rst2man.py
That's what upstream docutils installs by default.

Signed-off-by: Heiko Becker <heirecka@exherbo.org>
2021-01-21 11:27:30 +01:00
Valentin Churavy
10dd3eb6d5 Use dep_rt in amdgpu/meson.build
The amdgpu implementation uses `clock_gettime` so it needs to check whether it needs to link
against `-librt`.

Signed-off-by: Valentin Churavy <v.churavy@gmail.com>
2021-01-11 13:40:39 -05:00
Simon Ser
a55042e2c6
Bump version to 2.4.104
Signed-off-by: Simon Ser <contact@emersion.fr>
2021-01-11 17:18:20 +01:00
Antonin Décimo
cdd14e92e9 headers: drm: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - b10733527bfd864605c33ab2e9a886eec317ec39

The changes were as follows (shortlog from
14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f):

core: (drm_mode.h)

Alexander A. Klimov (1):
      drm: Replace HTTP links with HTTPS ones

Noralf Trønnes (1):
      drm: Add SPI connector type

Oleg Vasilev (1):
      drm: report dp downstream port type as a subconnector property

Simon Ser (1):
      drm: document that blobs are ref'counted

Uma Shankar (3):
      drm: Add HDR source metadata property
      drm: Fixed doc warnings in drm uapi header
      drm: Fix docbook warnings in hdr metadata helper structures

core: (drm_fourcc.h)

Adam Jackson (1):
      drm/fourcc: Fix undefined left shift in DRM_FORMAT_BIG_ENDIAN macros

Bas Nieuwenhuizen (2):
      drm/fourcc: Add AMD DRM modifiers.
      drm/fourcc: Fix modifier field mask for AMD modifiers.

Ben Davis (2):
      drm: drm_fourcc: add NV15, Q410, Q401 YUV formats
      drm: drm_fourcc: Add uncompressed AFBC modifier

Brian Starkey (1):
      drm: drm_fourcc: Add generic alias for 16_16_TILE modifier

Dave Airlie (1):
      Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux into drm-next

Dhinakaran Pandiyan (2):
      drm/framebuffer: Format modifier for Intel Gen-12 render compression
      drm/framebuffer: Format modifier for Intel Gen-12 media compression

James Jones (1):
      drm: Generalized NV Block Linear DRM format mod

Maarten Lankhorst (1):
      Backmerge remote-tracking branch 'drm/drm-next' into drm-misc-next

Matteo Franchin (1):
      drm/fourcc: Add AXBXGXRX106106106106 format

Mika Kahola (1):
      uapi/drm/drm_fourcc.h: Note on platform specificity for format modifiers

Neil Armstrong (2):
      drm/fourcc: Add modifier definitions for describing Amlogic Video Framebuffer Compression
      drm/fourcc: fix Amlogic Video Framebuffer Compression macro

Raymond Smith (1):
      drm/fourcc: Add Arm 16x16 block modifier

Simon Ser (4):
      drm/fourcc: document modifier uniqueness requirements
      drm: deprecate DRM_FORMAT_MOD_NONE
      drm/fourcc: add table describing AMD modifiers bit layout
      drm/fourcc: fix AMD modifiers PACKERS field doc

Signed-off-by: Antonin Décimo <antonin.decimo@gmail.com>
2021-01-11 16:12:38 +00:00
Simon Ser
4f0fe66369
Remove outdated comments about stdint.h
We include stdint.h unconditionally in the header. We don't require
users to include it manually before xf86drmMode.h.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2021-01-11 17:08:01 +01:00
Simon Ser
b82ed182ca
Remove definitions duplicated from drm_mode.h
I don't exactly know why these were duplicated before. Maybe libdrm
didn't always vendored drm_mode.h from the kernel? In any case, we now
do, so instead of having copy-pasted definitions, just include our
vendored version which cannot be outdated.

Contrary to what the comment says, drm.h doesn't include drm_mode.h, so
we need to add the include.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2021-01-11 17:05:47 +01:00
Emmanuel Vadot
d034db142d tests/amdgpu: Fix on FreeBSD
FreeBSD have endian.h under the sys directory.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
2020-12-12 11:34:17 +00:00
Luben Tuikov
d4fdeaf19b tests/amdgpu: Fix a typo
Fix a typo: "TZM" --> "TMZ"

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-11 16:51:35 -05:00
Nicolas Caramelli
1a2b1a6cac tests/modetest: remove bracket in dump_connectors()
Signed-off-by: Nicolas Caramelli <caramelli.devel@gmail.com>
2020-12-11 16:35:20 +00:00
Simon Ser
31dc14840f xf86drmMode.h: use ANSI C99 arrays
This avoids the use of a GNU-specific extension in public headers. Also
see [1].

[1]: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/80#note_707458

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2020-12-10 09:45:39 +00:00
Simon Ser
df373424c5 Document drmModeConnection
Signed-off-by: Simon Ser <contact@emersion.fr>
2020-12-10 09:24:42 +00:00
Simon Ser
05b0a955d3
man: convert to reStructuredText
DocBook makes it hard to write and maintain docs. Hopefully
reStructuredText can make this less painful.

The man pages were converted from DocBook to reStructuredText via
Pandoc:

    pandoc -s -f docbook -t rst -o man/drm.7.rst man/drm.xml

And then manual editing to fixup e.g. references to other man pages. To
compare the result with the DocBook version, this command was used:

    rst2man man/drm-kms.7.rst | man -l -

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2020-12-10 10:17:19 +01:00
Lubomir Rintel
9a7afcf198 tests/etnaviv_2d_test: check whether the rendering is correct
Instead of always dumping the rendered picture, check whether it matches
the expectations. This makes more sense for automated testing.

Retain the ability to dump the picture instead of checking it when a
file name is given as an argument. This also removes use of a hardcoded
file name in a world writable directory, which is an unsafe thing to
do anyway.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-12-09 16:00:51 +01:00
Lubomir Rintel
9638207005 tests/etnaviv_2d_test: pick the 2D core
Run the test on a core capable of 2D rendering instead of hardcoding to
core zero.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-12-09 16:00:47 +01:00
Lubomir Rintel
f35acf6d3f tests/etnaviv_2d_test: explain the errors
Just so that it's obvious what failed and why.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-12-09 16:00:43 +01:00
Thong Thai
fc479e133e tests/amdgpu/vcn: update to not use asic_id for Renoir
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-06 14:41:14 +00:00
Dave Airlie
5dea8f56ee Bump version to 2.4.103
Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-11-04 13:19:09 +10:00
Lucas Stach
c2e940a8be tests/util: Add imx-dcss driver
This makes the test utilities work with the i.MX DCSS driver without the
necessity of using the -M argument.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2020-10-28 10:56:18 +01:00
Paul Gofman
ad7cf9d75c xf86drm.c: Use integer logarithm.
log() is affected by FP control word and can provide inaccurate result.

Fixes Killer Instinct under Wine not being able to find AMD vulkan
device.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Paul Gofman <pgofman@codeweavers.com>
2020-10-28 09:18:47 +10:00
Tianci.Yin
3e9f211303 tests/amdgpu: disable VCN test if no VCN ring available(v2)
If KMD has no VCN support, remove the VCN test.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
2020-10-23 16:22:11 +08:00
Carsten Haitzler
3ec26b03ee tests: add komeda to list of modules to look for for testing
komeda is one of the supported GPUs in the kernel tree so this adds it
to libdrm modules to look for in tests.

Signed-off-by: Carsten Haitzler <carsten.haitzler@arm.com>
2020-10-16 15:14:45 +01:00
Alex Deucher
ce1387b591 amdgpu: only enable security tests on raven family
It's the only asic with support at the moment.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:47:05 -04:00
Luben Tuikov
253e0383a3 tests/amdgpu: Secure bounce test (v4)
Implement secure bounce test. Steps implemented
as outlined by Christian K.

v2: Remove gpu_info; add comment describing
    the purpose and steps of the test.
v3: Parameterize "secure" in amdgpu_bo_lcopy() and
    amdgpu_bo_move(). Set them both to 0.
    Allocate buffer Bob to be non-TMZ.
v4: Fix an off-by-one bug which was causing
    the test to segfault.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:47:00 -04:00
Luben Tuikov
18a0291273 tests/amdgpu: Remove forward declarations
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:55 -04:00
Aaron Liu
24b9c9ca47 test/amdgpu: enable security suite tests
This patch enables security suite tests.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:50 -04:00
Aaron Liu
eb1a17039f test/amdgpu: add drm version checking for security suite
Adding drm version checking for security suite.
drm version need to be at least 3.37.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:45 -04:00
Aaron Liu
238acd6f3d tests/amdgpu: add test to submit a sdma command with secure context
This patch add test to submit a sdma command with secure context.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:40 -04:00
Aaron Liu
38c44cccdc tests/amdgpu: add atomic dma command to verify the secure buffer (v2)
DMA's atomic behavir is unlike GFX,If the comparing data is not
equal to destination data,
For GFX, loop again till gfx timeout(system hang).
For DMA, loop again till timer expired and then send interrupt.
So testcase can't use interrupt mechanism.
We take another way to verify. When the comparing data is not
equal to destination data, overwrite the source data to the destination
buffer. Otherwise, original destination data unchanged.
So if the bo_cpu data is overwritten, the result is passed.

Steps:
1. use linear write packet to write 0xdeadbeaf to secure buffer,
2. use atmoic packet and ATOMIC_CMPSWAP_RTN_32 opcode to compare
the cmp_data(0xdeadbeaf) to the written data which has been encrypted.

v2: add the case of (dest_data != cmp_data).

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:34 -04:00
Aaron Liu
00087856fc tests/amdgpu: add test to submit a gfx command with secure context
This patch is to test the command submission with secure context.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:29 -04:00
Aaron Liu
5de99b1fa6 tests/amdgpu: add atomic_mem cp_packet to verify the secure buffer
Secure buffer is only able to be read with trusted ip block.
So we need use GFX ip to read it back instead of CPU.
Steps:
1. use write_data packet to write 0xdeadbeaf to secure buffer,
2. use atmoic_mem packet and ATOMIC_CMPSWAP_RTN_32 opcode to compare
the cmp_data(0xdeadbeaf) to the written data which has been encrypted.
If the result is equal, then overwrite the src_data(0x12345678) to the
secure buffer and return directly. Otherwise loop again until gfx timeout
and the secure buffer data unchanged.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:22 -04:00
Aaron Liu
b352ef44b8 tests/amdgpu: expand secure param for exec_cs_helper (v2)
This patch expands secure param for amdgpu_test_exec_cs_helper_raw.
The flag is transfered to kernel with cs.

v2: squash in change from context to IB flag

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:16 -04:00
Huang Rui
0cefd4cecd tests/amdgpu: add device handle as input param for exec_cs_helper and write_linear_helper (v4)
This patch is to add add device handle as input param for exec_cs_helper
and write_linear_helper.

Because they are needed in security tests.

v2: fix typo that basic tests should be un-secure.
v3: refine the function implementation.
v4: remove amdgpu_cs_ctx_create3 calling.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:11 -04:00
Huang Rui
76ceb8b806 tests/amdgpu: expand write linear helper for security (v3)
This patch expand write linear helper for security to submit the command
with secure context.

v2: refine the function implementation.
v3: remove amdgpu_cs_ctx_create3.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:05 -04:00
Huang Rui
cfe55a0451 tests/amdgpu: add secure buffer allocation test for invisible VRAM
This patch is to add secure buffer allocation test for invisible VRAM.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:46:00 -04:00
Huang Rui
e63b775e5a tests/amdgpu: add secure buffer allocation test for system memory
This patch is to add secure buffer allocation test for system memory.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:50 -04:00
Huang Rui
2c0e4991d7 tests/amdgpu: add security test suite (v2)
This patch is to add a new test suite to store security tests.
In Raven+ asics, it will support TMZ (trust memory zone), and it is
page-based protection feature.

v2: remove tests/amdgpu/Makefile.am and update to
tests/amdgpu/meson.build

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:41 -04:00
Alex Deucher
2420768d02 amdgpu: sync up amdgpu_drm.h with latest from kernel
From drm-next:

commit c41219fda6e04255c44d37fd2c0d898c1c46abf1
Merge: e20bb857dea2 d96536f0fe69
Author: Dave Airlie <airlied@redhat.com>
Date:   Thu May 21 10:44:32 2020 +1000

    Merge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

    Fix for TypeC power domain toggling on resets (Cc: stable).
    Two compile time warning fixes.

    Signed-off-by: Dave Airlie <airlied@redhat.com>
    From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200520123227.GA21104@jlahtine-desk.ger.corp.intel.com

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:31 -04:00
Le Ma
6e10ac07c8 tests/amdgpu: disable unsupported test cases for Arcturus
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:27 -04:00
Le Ma
bbaec1283f tests/amdgpu: move arcturus asic check function to common place
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:22 -04:00
James Zhu
70c97212b8 tests/amdgpu/vcn: add Arcturus decode test support
Add Arcturus decode test support only

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:17 -04:00
Le Ma
236a139f09 tests/amdgpu: disable gfx engine basic test cases for Arcturus
Since Arcturus has no gfx pipeline(CPG), cases below is not suitable:
  - Command submission Test (GFX)
  - Command submission Test (Multi-Fence)
  - Sync dependency Test

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:45:11 -04:00
Le Ma
301b4b64d0 tests/amdgpu: create Active function for basic test suite
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:44:58 -04:00
Le Ma
ba0d45eca6 tests/amdgpu: add function to check Asic is Arcturus
Since Arcturus has no gfx engine, add function to blacklist gfx related test.

Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-15 13:44:34 -04:00
Alex Deucher
5de99aebba amdgpu: add marketing names from 20.40
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05 11:33:10 -04:00
Tapani Pälli
bb7433c1c6 intel: add INTEL_DG1_IDS to the pciids list
This enables drm_intel_bufmgr on DG1 and allows us to pass dmabuf
import/export related tests with Piglit.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2020-09-30 13:37:48 +03:00
sitanliu
77687f8d6e amdgpu: add device IDs for Raven, Picasso and Renoir 2020-09-03 23:51:28 +08:00
Adam Miszczak
a9591d66fe intel: sync i915_pciids.h with kernel
Add DG1 and clean-up VLV PCI IDs.

Align with kernel commits:
f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
fd38cdb81105 ("drm/i915/dg1: Add DG1 PCI IDs")

Signed-off-by: Adam Miszczak <adam.miszczak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-08-27 09:06:04 +00:00
Jeremy Cline
5bd6a7659e man: Update the bug URL to gitlab.freedesktop.org
Point users to the GitLab issue tracker instead of Bugzilla, which is no
longer used.

Signed-off-by: Jeremy Cline <jcline@redhat.com>
2020-08-27 08:10:12 +00:00
sunil kumar dora sermsity
a84caff71b intel: Add PCI ID support to RKL platform
Missing RKL PCI ID preventing below test cases to succeed on RKL Platform.
    igt@kms_frontbuffer_tracking
    igt@kms_draw-crc
    igt@kms_big_fb

    Signed-off-by: sunil kumar dora sermsity <sunilx.kumar.dora.sermsity@intel.com>
    Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2020-08-21 20:02:53 +00:00
Pavan Kumar Ramayanam
0a1aefe560 amdgpu: Add Device IDs for Embedded Raven2 platforms
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-19 22:30:23 -04:00
José Roberto de Souza
669e1087ab intel: sync i915_pciids.h with kernel
Two new patches landed in kernel adding new PCI ids:
123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids")
52797a8e8529 ("drm/i915/ehl: Add new PCI ids")

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
2020-07-08 10:44:53 -07:00
Leo Liu
f449081628 tests/amdgpu: clear the extension flag
This is workaround of firmware issue, and the change has no impact
on the legacy HW.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
2020-06-18 10:08:23 -04:00
Leo Liu
f806d438d6 tests/amdgpu: clear msg decode flag
It is not used for VCN from VCN1, but VCN3 use it
for other feature, so clear it, because we don't
use the feature for now

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
2020-06-18 10:08:23 -04:00
Leo Liu
7b9d4bbdd5 tests/amdgpu: add VCN3.0 regs support
VCN3.0 has its own set of internal regs

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
2020-06-18 10:08:23 -04:00
Heiko Thiery
c7d8941288 xf86drm.c: fix build failure
./xf86drm.c: In function 'drmNodeIsDRM':
../xf86drm.c:2825:7: error: "__FreeBSD__" is not defined [-Werror=undef]
 #elif __FreeBSD__
       ^
../xf86drm.c: In function 'drmGetMinorNameForFD':
../xf86drm.c:2938:7: error: "__FreeBSD__" is not defined [-Werror=undef]
 #elif __FreeBSD__
       ^
../xf86drm.c: In function 'drmParsePciBusInfo':
../xf86drm.c:3258:7: error: "__FreeBSD__" is not defined [-Werror=undef]
 #elif __FreeBSD__
       ^
../xf86drm.c: In function 'drmParsePciDeviceInfo':
../xf86drm.c:3427:7: error: "__FreeBSD__" is not defined [-Werror=undef]
 #elif __FreeBSD__
       ^
../xf86drm.c: In function 'drmGetDeviceNameFromFd2':
../xf86drm.c:4305:7: error: "__FreeBSD__" is not defined [-Werror=undef]
 #elif __FreeBSD__
       ^

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2020-06-06 07:16:45 +02:00
Eric Engestrom
5ab6031699 core: use O_RDONLY instead of ambiguous 0 flag
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2020-05-28 17:17:26 +02:00
Alex Deucher
9fbae6f6ad amdgpu: add marketing names from 20.10
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-27 17:16:28 -04:00
Dave Airlie
bb70ab82fd Bump version to 2.4.102
Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-05-27 06:33:09 +10:00
Emil Velikov
bf602a2d67 modetest: Add a new "-r" option to set a default mode
This option finds all connected connector and then sets its preferred
mode on it. If no preferred mode is available, first mode is used.

This option must be set w/o any mode or plane.

This allows for a quick test on all connected outputs.

Loosely based on the work by Ezequiel Garcia <ezequiel@collabora.com>

Changes since Ezequiel's work:
 - implement atomic codepath
 - set all connectors
 - pick correct crtc
 - don't set -r by default
 - nearly identical output in atomic and non-atomic codepaths

v2:
 - Use the crtc->crtc_id, instead of the plane's current crtc_id

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
a04c8abb86 modetest: reorder atomic path alike the non-atomic
Makes the code a tiny bit more symmetrical.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
e341176d9f modetest: don't error out of final AtomicCommit
The very final drmModeAtommicCommit tears down the existing mode/plane
setup. Following it we clean up other misc state laying around.

Chances are that it will not fail, but in the extremely unlikely case it
does, there's nothing one can do.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
3d88c993a4 modetest: factor out atomic pageflip test
Move the hunk of code into a function, making the overall flow easier to
follow and providing some symmetry to the non-atomic path.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
d928cd803a modetest: push pipe_resolve_connectors() to set_mode
The function is closely related to pipe_find_crtc_and_mode() so we might
as well keep them together.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
3b9585d88e modetest: move pipe_resolve_connectors() further up
Move the function above set_mode, since we'll be using it from there as
of next commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
bdb9b82cf7 modetest: unify {,atomic_}set_mode()
Instead of duplicating the exact same code across the two functions,
fold them into one.

For some strange reason git diff may show atomic_clear_mode() as changed
The function in untouched, despite the misleading output.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
544fab624d modetest: get the crtc_id from the pipe_arg
Makes the code shorter and easier to read.

Currently if the user has not set the crtc_id, we fetch the crtc yet do
not "bother" setting the id - do so.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:35 +01:00
Emil Velikov
336c04220c modetest: introduce and use get_crtc_by_id() and get_crtc_mask()
Let's make the code shorter, this avoid crashes (when drmModeGetCrtc()
fails) by using a couple of helpers. As get_resources() considers the
drmModeGetCrtc() fail non-fatal, we might as well handle it properly.

v2: Add a comment above the unreachable abort() (Eze)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:09:14 +01:00
Emil Velikov
ef58af6dfc modetest: close the device on exit
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:04:01 +01:00
Emil Velikov
53fde76ce3 modetest: remove drmMode{,Plane}Res
There's no point in keeping these around since we already fetch the
complete data set. Add respective count_ variables and greatly simplify
the existing code.

Extra brownie points for:
 - using the inverse order in free_resources()
 - don't memory leak the connector properties
 - free the properties themselves, instead of only the objects

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:03:52 +01:00
Emil Velikov
823669c6c0 modetest: add and use bo_fb_create() helper
Flesh out the bo_create + drmModeAddFB2 dance into a helper and use it.
Currently we're duplicating that in 4 places, many of which leaking et
al.

As a bonus point this highlights that the atomic_set_plane() seems tad
buggy. That'll be fixed with separate commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:03:41 +01:00
Emil Velikov
900ed60848 modetest: set atomic cap, _only_ when needed
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:03:32 +01:00
Emil Velikov
69f25d6a29 modetest: move basic args check before open()
Don't bother opening the device node, if the args combination is invalid

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:03:27 +01:00
Emil Velikov
24c0c44c8d modetest: remove cursor/page_flipping_supported stubs
The two functions have been stubs for ages. The alluded generic ioctls
never came to be, assumingly because all new drivers support those.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:03:18 +01:00
Emil Velikov
9ffcbf5cd9 modetest: simplify "dump all" logic
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2020-05-19 21:02:45 +01:00
Jose Maria Casanova Crespo
c997baf590 meson: require valgrind 3.10.0 to enable it with freedreno
Freedreno uses VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE that was
introduced in Valgrind 3.10.0

Raspbian Buster includes Valgrind 3.7.0, so when valgrind is installed
as freedreno is build by default the build becomes broken. So lets
require 3.10 to enable valgrind when freedreno is built.

v2: Keep the arguments listed in the same order (Emil Velikov)

Closes: https://gitlab.freedesktop.org/mesa/drm/-/issues/37
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-05-07 02:57:55 +00:00
Karol Herbst
bfa782c5f6 nouveau: sync up with nouveau_abi16.h and nouveau_drm.h
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
2020-05-06 23:17:48 +02:00
Boram Park
7915b0a68d drm mode : fix memory leak when freeing drmModePropertyPtr
Closes: https://gitlab.freedesktop.org/mesa/drm/-/issues/5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2020-05-05 11:47:18 +01:00
Emmanuel Vadot
5aa83dd6fa libdrm: drmGetDeviceNameFromFd: Always return /dev/dri/ node for FreeBSD
Since we now always returns the /dev/dri/ node for
drmGet<nodetype>DeviceNameFromFd, be consistant with the names returned
in drmGetDeviceNameFromFd.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
2020-05-04 21:19:58 +02:00
Emmanuel Vadot
f52e2b20ed libdrm: drmGetMinorNameFromFd: Fix FreeBSD variant
Fix the FreeBSD variant by getting the node type represented by fd to deduce
the target minor name.
We then return the full /dev/dri/<minorname><id> version.

Fix: #41
Fixes: 6818a50b12
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
2020-05-04 21:19:58 +02:00
Karol Herbst
5ec177b398 nouveau: fix compile error with -DDEBUG on newer gcc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-05-04 11:58:10 +02:00
Nicholas Bishop
05727548a1 libdrm: intel: add DRM_RDWR flag in drm_intel_bo_gem_export_to_prime
This is similar to b81d44d587: the
DRM_RDWR flag is needed for mmap to work.

Signed-off-by: Nicholas Bishop <nicholasbishop@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-30 11:12:37 +00:00
Nicholas Bishop
dd562b1efd intel: properly escape sed pattern for tests
The sed was incorrectly modifying e.g. "nicholasbishop" to
"nicholasbop". The updated pattern will only match `.sh` at the end of
the string.

Signed-off-by: Nicholas Bishop <nicholasbishop@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-27 15:53:58 +00:00
Leo Liu
fd7f3746e3 tests/amdgpu/vcn: add Renoir VCN2.0 decode support
Renoir is the same family as Raven, but it's with VCN2.0,
so it has to use VCN2.0 reg set

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-By: Thong Thai <thong.thai@amd.com>
2020-04-26 11:39:19 -04:00
Scott Anderson
bf63f8acdc libdrm: Handle usb_interface devices for usb parsing
Currently the code expects that the device found at
/sys/char/$maj:$min/device for USB devices is a "usb_device". However,
at least for some devices, such as for the udl driver, they are instead
a "usb_interface".

A usb_interface is a child of the usb_device we're interested in, so we
walk up one in the /sys path to get there.

For example, with a USB device I have, trimmed to show the relevant
information:
```
$ udevadm info /dev/dri/card1
P: /devices/pci0000:00/0000:00:01.3/0000:02:00.0/usb1/1-4/1-4:1.0/drm/card1
E: DEVTYPE=drm_minor
$ udevadm info /sys/devices/pci0000:00/0000:00:01.3/0000:02:00.0/usb1/1-4/1-4:1.0
E: DEVTYPE=usb_interface
E: DRIVER=udl
$ udevadm info /sys/devices/pci0000:00/0000:00:01.3/0000:02:00.0/usb1/1-4
E: DEVTYPE=usb_device
E: DRIVER=usb
E: BUSNUM=001
E: DEVNUM=009
```

Signed-off-by: Scott Anderson <scott@anderso.nz>
2020-04-24 08:53:53 +00:00
Mikhail Golubev
57df07572c xf86drm: Check non-absolute path only for virtio based devices
This fixes bug in drmParseSubsystemType() that cases situation when
subsequent call to readlink() from get_subsystem_type() will result in
EACCESS.

Signed-off-by: Mikhail Golubev <mikhail.golubev@opensynergy.com>
2020-04-24 08:24:46 +00:00
Peter Seiderer
9001c93b7f tests/amdgpu: needs atomic_ops
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Acked-by: Alex Deucher alexander.deucher@amd.com
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-22 23:54:36 -04:00
Emil Velikov
cf1afec017 tests: install drmdevice
Just like the other tests (tools really) install drmdevice. It is a
simple tool which is useful for basic check/testing.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2020-04-21 18:50:23 +01:00
Emmanuel Vadot
1600fe1130 tests/nouveau/threaded: adapt ioctl signature for FreeBSD
FreeBSD also use (int, unsigned long int, ...) like GLIBC.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
e321dd7a4d libdrm: Implement drmParsePciDeviceInfo for FreeBSD
The FreeBSD kernel expose a pseudo-device /dev/pci to obtain information
about present PCI device.
Uee the PCIOCGETCONF ioctl on this device to look up the desired device
information.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
44bcf9c0ce libdrm: get_pci_path is Linux only so add an ifdef
Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
379113724f libdrm: Add get_sysctl_pci_bus_info for FreeBSD
The FreeBSD drm driver expose a sysctl hw.dri.%d.busid which contain
the busid.
Use this sysctl to parse the busid information based on the major/minor
that allow us to implement FreeBSD support for drmParsePciBusInfo.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
bb584b8fd2 libdrm: drmCheckModesettingSupported: fix for FreeBSD
FreeBSD only support up to 10 GPUs not 16.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
24e68525dc libdrm: drmCheckModesettingSupported: Fix for FreeBSD
Remove some useless busid rewritting.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
13c9de39a6 libdrm: drmGetDeviceNameFromFd2: Add FreeBSD variant
The FreeBSD variant of drmGetDeviceNameFromFd can already handle
the different node type so just call it.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
41f3a7b3e5 libdrm: Default to PCI for FreeBSD
FreeBSD have some support for DRM on !PCI device but no code is currently
upstream. Default to PCI for now.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
57c50cfc45 libdrm: drmGetMinorNameForFD: Add FreeBSD variant
Use the FreeBSD variant function to obtain the minor name and the
device node.
Return the correct path based on where the node is (drm/ versus dri/).

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
6818a50b12 libdrm: drmGetDeviceNameFromFd: Add FreeBSD variant
Get the major/minor via fstat and after checking that this is a drm node
construct the full device node name using devname.
Note that we should be able to use fdevname to avoid calling fstat + devname
but for some reason it doesn't work on drm node (probably due to how the device
node are created in the linux compat code for drm on FreeBSD).

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:26:54 +02:00
Emmanuel Vadot
c55a1e564c libdrm: drmGetMinorType: Add FreeBSD version
Resolve the minor type based on the device node path.
The minor type is either in /dev/drm/X where X is the type or
in a Linux-compatible device node in /dev/dri/
This means we need the major number on FreeBSD so add it to the function
arguments.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 19:25:36 +02:00
Emmanuel Vadot
4fbcc9a6a7 xf86drm: Remove ifdef for FreeBSD and DRM_MAJOR
FreeBSD devfs only provides on the fly generated major/minor.
The major number is irrelevant for FreeBSD so remove the special case.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 18:39:48 +02:00
Emmanuel Vadot
1c8d2b73a6 libdrm: drmNodeIsDRM: Add FreeBSD variant
FreeBSD devfs have on the gly generated major minor so we cannot use them
to test if the device is a drm node.
Instead get the devfs node name and test if it is in a subdirectory "drm/"
or "dri/".
Historycally DRM device on FreeBSD are created in /dev/drm/ and link are
present in /dev/dri/ for compatibility reason.

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-04-21 18:39:48 +02:00
Eric Engestrom
1f8ada8023 meson: don't detect <sys/sysctl.h> on Linux
The header is not required on Linux, and is in fact deprecated in glibc 2.30+

Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Cc: Niclas Zeising <zeising@daemonic.se>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Niclas Zeising <zeising@daemonc.se>
2020-04-20 23:48:08 +00:00
James Zhu
8cef557062 tests/amdgpu/vcn: add dummy feedback message
Latest VCN firmware has feedback header check.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2020-04-16 16:01:37 -04:00
Timo Aaltonen
27fa47a738 Bump version to 2.4.101 2020-04-03 14:39:47 +03:00
Pierre-Eric Pelloux-Prayer
b9bf42d3e1 amdgpu: increase cpu_map_count storage size
Mesa expects to be able to map the same buffer, without unmapping it.
This leads to problem on long-running program.

On the other hand, libdrm uses cpu_map_count as a refcount and expects
its value to decrease so it can unmap buffers.

The previoulsy proprosed fix (https://patchwork.freedesktop.org/patch/258005/)
stopped increased the counter when it went past INT_MAX.

This commit instead proposes to use a larger type to store cpu_map_count.
The outcome is the same: long running apps will not crash, only the
implementation differs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1423
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-03-23 13:18:01 +01:00
Swathi Dhanavanthri
bb4e154d3d intel: sync i915_pciids.h with kernel
Changes:
3882581753d1 ("drm/i915/tgl: Add new PCI IDs to TGL")

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: Timo Aaltonen <timo.aaltonen@canonical.com>
2020-03-23 13:51:19 +02:00
Daniel Stone
665c0f7fd8 Add DRM_MODE_CONNECTOR_WRITEBACK to xf86drmMode.h
xf86drmMode.h currently duplicates the connector-type definitions from
drm_mode.h. Add DRM_MODE_CONNECTOR_WRITEBACK, which is only visible
through a client cap, from drm_mode.h.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2020-03-17 12:19:10 +00:00
Michel Dänzer
fe06ee2054 tests: Only copy con->modes[0] if it exists
con->modes can be NULL. Fixes crash in that case.

Closes: https://gitlab.freedesktop.org/mesa/drm/issues/34
Reviewed-by: Daniel Stone <daniels@collabora.com>
2020-02-27 12:21:09 +01:00
Vasyl Vavrychuk
8a73372e62 xf86drm: fix subsystem type lookup for virtio mmio-based devices
Currently the code assumes that a virtio based device is always located
on the PCI bus.

Modify the parser to make it check the device's parent directory to
determine on which bus it is located.

Output for virtio-pci is the PCI bus.
Output for virtio-mmio is the Platform bus.

Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@opensynergy.com>
Signed-off-by: Mikhail Golubev <Mikhail.Golubev@opensynergy.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
2020-02-24 21:53:41 +00:00
Vasyl Vavrychuk
c4eae71d7e xf86drm: generalize the device subsystem type parsing code
Move the code, which used to get the device subsystem type from a device
path in sysfs, to a separate function to be reusable.

Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@opensynergy.com>
Signed-off-by: Mikhail Golubev <Mikhail.Golubev@opensynergy.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
2020-02-24 21:53:41 +00:00
Eric Engestrom
2c0a01261d tests: drop redundant and slow random test
Suggested by Emil [1]:
> Feel free to drop the random test altogether. It's an old public API
> no active users (pretty ancient code uses it) and the in-tree users
> drmSL and drmHash already have respective tests.

This test takes minutes to run, while all the other tests combined take
barely more than a second.

Dropping it also helps the CI by avoiding random timeouts when `random`
takes more than the 4 minutes (!) we've allowed for it.

[1] https://gitlab.freedesktop.org/mesa/drm/merge_requests/26#note_390066

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-02-15 12:14:00 +00:00
Huang Rui
a42eb3dfde amdgpu: clean up the cs structure variable
This patch is to use generic variables as the input of amdgpu_cs_submit_raw2.
Because amdgpu_cs_submit_one won't handle IOCTL directly.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-02-12 19:55:22 +08:00
Huang Rui
c483259248 amdgpu: remove the un-used chunk_array
This array won't be used.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-02-12 19:55:16 +08:00
Huang Rui
cf9eb78a89 amdgpu: use amdgpu_cs_submit_raw2 in amdgpu_cs_submit
So far, amdgpu_cs_submit_raw2 is mainly used for upper layer (Mesa), however,
amdgpu_cs_submit is used for current all unit tests. Our intention is that the
unit tests can actually verify the API which is really used.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-02-12 19:55:09 +08:00
Huang Rui
fca0849af3 amdgpu: use alloca for dependencies and sem_dependencies
Use alloca instead of malloc, then we don't need free them at the end of this
function.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-02-12 19:52:37 +08:00
Daniel Stone
d8731e9eec Add drmModeGetFB2
Add a wrapper around the getfb2 ioctl, which returns extended
framebuffer information mirroring addfb2, including multiple planes and
modifiers.

Changes since v7:
 - add new symbols to core-symbol.txt (Eric Engestrom)

Changes since v5:
 - style change

Changes since v4:
 - Set fb_id at init instead of memclear() and set (Eric Engestrom)

Changes since v3:
 - remove unnecessary null check in drmModeFreeFB2 (Daniel Stone)

Changes since v2:
 - getfb2 ioctl has been merged upstream
 - sync include/drm/drm.h in a seperate patch

Changes since v1:
 - functions should be drm_public
 - modifier should be 64 bits
 - update ioctl number

Signed-off-by: Juston Li <juston.li@intel.com>
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2020-02-12 10:23:44 +11:00
Juston Li
63d914d479 include/drm: sync up drm.h
a) delta: Adds DRM_IOCTL_MODE_GETFB2
  b) Generated using make headers_install
  c) Taken from drm-next-misc:
        commit 3ff4c24bdb1f494c217c80348f9db4896043ed81
        Author: Lyude Paul <lyude@redhat.com>
        Date:   Fri Jan 17 17:47:48 2020 -0500

        drm/dp_mst: Fix indenting in drm_dp_mst_topology_mgr_set_mst()

Signed-off-by: Juston Li <juston.li@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2020-02-12 10:23:44 +11:00
Alex Deucher
5c8ff57732 amdgpu: add new marketing names from 19.50
Add new marketing names.

Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-01 12:12:19 -05:00
Imre Deak
933729720b intel: drm_intel_bo_gem_create_from_* on platforms w/o HW tiling
Platforms without a HW detiler doesn't support the get_tiling IOCTL.
Fix the drm_intel_bo_gem_create_from_* functions assuming the default
no-tiling, no-swizzling setting for the GEM buffer in this case.

v2:
- Add the missing gem handle IOCTL parameter. (Eric)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2020-01-28 15:32:39 +02:00
Eric Engestrom
074947ee4b meson: always define whether headers exist
Combined with -Wundef (added in 75758d2ccf & enforced in ba17673eed),
this provides absolute safety against #ifdef typos.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-01-23 17:00:12 +00:00
Eric Engestrom
077e64292c meson: add symbols check for core libdrm
All the libdrm_* submodules have symbols checks, no reason to keep core
libdrm wild.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2020-01-23 16:55:04 +00:00
Ezequiel Garcia
07d48a4c00 modetest: Fix segmentation fault
When a mode is set with just a connector "-s foo",
we get a nasty segmentation fault. Fix it.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2020-01-21 17:56:23 +00:00
John Stultz
899da0f486 libdrm: modetest: Allow selecting modes by index
Often there are many similar modes, which cannot be selected
via modetest due to its simple string matching.

This change adds a mode index in the display output, which can
then be used to specify a specific modeline to be set.

Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Rob Clark <robdclark@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: John Stultz <john.stultz@linaro.org>
[emil: rebase]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2020-01-21 17:56:23 +00:00
Luben Tuikov
c9d4540bf6 tests/amdgpu: Fix buffer overflow (v3)
This patch fixes the following warning:
-Wformat-overflow=

v2: Use the correct strlcat(3).
v3: Use strncat(3) and remove libbsd dependency.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-08 13:21:40 -05:00
Luben Tuikov
29a5a85dae tests/amdgpu: Fix unused function warning (v2)
This patch fixes:
-Wunused-function

v2: Always enable amdgpu_ras_test().

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-08 13:20:57 -05:00
Luben Tuikov
cb3d067587 tests/amdgpu: Fix various warnings (v2)
This patch fixes the following warnings:
-Wformat=
-Wmaybe-uninitialized
-Wmisleading-indentation
-Wstringop-truncation
-Wunused-function
-Wunused-variable

It also removes forward declarations and moves
global functions to the bottom, keeping locals
at the top, in ras_tests.c.

v2: Fix compilation.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-08 13:18:50 -05:00
Marek Olšák
9ebfac15a5 Revert "tests/amdgpu: Fix various warnings"
This reverts commit fb1634583f.
2020-01-07 14:44:47 -05:00
Marek Olšák
54b982dc6a Revert "tests/amdgpu: Fix unused function warning (v2)"
This reverts commit 4ff499cd85.
2020-01-07 14:44:47 -05:00
Marek Olšák
b9600be207 Revert "tests/amdgpu: Fix buffer overflow (v3)"
This reverts commit 680542ce08.
2020-01-07 14:44:47 -05:00
Luben Tuikov
7fdebb02ff tests/amdgpu: Proper format for "-l"
Proper format for command line option "-l",
listing the supported and unsupported tests:

1) Add an aligned column header.

2) Align all fields into columns.

3) Fixed length fields, come before the last
column, which is a variable length field.

4) Variable length field, which is the name of the
test, goes in the last column.

5) If a suite is disabled, do not iterate over its
tests, as they'd naturally be all disabled.

Now the output looks like this:
$sudo ./amdgpu_test -l
 What: ID:   Status: Name
Suite:  1:  ENABLED: Basic Tests
 Test:  1:  ENABLED: Query Info Test
 Test:  2:  ENABLED: Userptr Test
 Test:  3: DISABLED: bo eviction Test
 Test:  4:  ENABLED: Command submission Test (GFX)
 Test:  5:  ENABLED: Command submission Test (Compute)
 Test:  6:  ENABLED: Command submission Test (Multi-Fence)
 Test:  7:  ENABLED: Command submission Test (SDMA)
 Test:  8:  ENABLED: SW semaphore Test
 Test:  9: DISABLED: Sync dependency Test
 Test: 10: DISABLED: Dispatch Test (Compute)
 Test: 11: DISABLED: Dispatch Test (GFX)
 Test: 12: DISABLED: Draw Test
 Test: 13: DISABLED: GPU reset Test
Suite:  2:  ENABLED: BO Tests
 Test:  1:  ENABLED: Export/Import
 Test:  2: DISABLED: Metadata
 Test:  3:  ENABLED: CPU map/unmap
 Test:  4:  ENABLED: Memory alloc Test
 Test:  5:  ENABLED: Memory fail alloc Test
 Test:  6:  ENABLED: Find bo by CPU mapping
Suite:  3: DISABLED: CS Tests
Suite:  4: DISABLED: VCE Tests
Suite:  5:  ENABLED: VCN Tests
 Test:  1:  ENABLED: VCN DEC create
 Test:  2:  ENABLED: VCN DEC decode
 Test:  3:  ENABLED: VCN DEC destroy
 Test:  4:  ENABLED: VCN ENC create
 Test:  5:  ENABLED: VCN ENC decode
 Test:  6:  ENABLED: VCN ENC destroy
Suite:  6: DISABLED: UVD ENC Tests
Suite:  7: DISABLED: Deadlock Tests
Suite:  8:  ENABLED: VM Tests
 Test:  1:  ENABLED: resere vmid test
 Test:  2:  ENABLED: unaligned map
 Test:  3:  ENABLED: vm mapping test
Suite:  9: DISABLED: RAS Tests
Suite: 10:  ENABLED: SYNCOBJ TIMELINE Tests
 Test:  1:  ENABLED: syncobj timeline test
$_

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-07 14:38:36 -05:00
Luben Tuikov
680542ce08 tests/amdgpu: Fix buffer overflow (v3)
This patch fixes the following warning:
-Wformat-overflow=

v2: Use the correct strlcat(3).
v3: Use strncat(3) and remove libbsd dependency.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-07 14:38:36 -05:00
Luben Tuikov
4ff499cd85 tests/amdgpu: Fix unused function warning (v2)
This patch fixes:
-Wunused-function

v2: Always enable amdgpu_ras_test().

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-07 14:38:36 -05:00
Luben Tuikov
fb1634583f tests/amdgpu: Fix various warnings
This patch fixes the following warnings:
-Wformat=
-Wmaybe-uninitialized
-Wmisleading-indentation
-Wstringop-truncation
-Wunused-function
-Wunused-variable

It also removes forward declarations and moves
global functions to the bottom, keeping locals
at the top, in ras_tests.c.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
2020-01-07 14:38:36 -05:00
Yifan Zhang
ed96524001 tests/amdgpu: fix a amdgpu_test hang issue on some platforms.
The computer ring test name mis-match in different files,
thus may be set with TRUE on wrong platforms.

Change-Id: I0b918ff8faf08c9c9f1ad55f4dcd18f66b956901
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-12-30 20:25:52 -05:00
Scott Anderson
c70bd7b705 meson: Replace 'config.h' with config_file
This fixes an issue with libdrm failing to build when used as a meson
subproject. Using 'config.h' directly will cause it to possibly refer to
the wrong file.

By using `@0@.format(config_file)`, it will be transformed into the
correct relative path, e.g. `./config.h` in normal build,
`./subprojects/libdrm/config.h` in subproject build.

Signed-off-by: Scott Anderson <scott@anderso.nz>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-17 23:07:53 +00:00
Eric Engestrom
edafcf18e5 add a minimal .gitignore back
It was entirely deleted along with autotools, but adding this simple one
will cover most people's needs.

Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-17 22:37:39 +00:00
Eric Engestrom
6d3f06f666 gitlab-ci: rename build folder to simply build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-17 22:29:11 +00:00
José Roberto de Souza
4c31d1181b intel: sync i915_pciids.h with kernel
Changes:
651cc835d5f6 ("drm/i915: Add new EHL/JSL PCI ids")
b6a8781a447c ("drm/i915/cml: Remove unsupport PCI ID")
8717c6b7414f ("drm/i915/cml: Separate U series pci id from origianl list.")

v2: added the latest CML changes

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-17 13:27:46 -08:00
Devarsh Thakkar
7f82714522 modetest: Use floating vrefresh while dumping mode
Add function to derive floating value of vertical
refresh rate from drm mode using pixel clock,
horizontal total size and vertical total size.

Use this function to find suitable mode having vrefresh
value which is matching with user provided vrefresh value.

If user doesn't provide any vrefresh value in args then
update vertical refresh rate value in pipe args using this
function.

Also use this function for printing floating vrefresh while
dumping all available modes.

This will give more accurate picture to user for available modes
differentiated by floating vertical refresh rate and help user
select more appropriate mode using suitable refresh rate value.

V4:
1) While setting mode, print mode name and vrefresh using struct
   drmModeModeInfo instead of struct pipe_args.
2) Revert back to using a float value instead of float *
   for vrefresh arg in connector_find_mode().

V3:
1) Change name of function used to derive refresh rate.

V2:
1) Don't use inline function for deriving refresh rate from mode.
2) If requested mode not found, print refresh rate only
   if user had provided it in args.

Signed-off-by: Devarsh Thakkar <devarsh.thakkar@xilinx.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2019-12-11 17:47:31 +02:00
Flora Cui
31a6ec141a tests/amdgpu: add gfx ring bad slow draw test
for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:46:53 -05:00
Flora Cui
5e1f6533a0 tests/amdgpu: add gfx ring draw hang test
for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:46:53 -05:00
Flora Cui
71b9e68d99 tests/amdgpu: add bad slow dispatch test
add gfx/compute bad slow dispatch test for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:46:53 -05:00
Flora Cui
d72b9189c4 tests/amdgpu: add dispatch hang test
add compute/gfx dispatch hang test for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:46:53 -05:00
Flora Cui
67017ea07e tests/amdgpu: update draw test for gfx9
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:46:53 -05:00
changzhu
d93856fe82 tests/amdgpu: enable dispatch/draw tests for Renoir
It can run dispatch/draw tests on new renoir chips. So it needs to
enable dispatch/draw tests for Renoir again.

Change-Id: I3a72a4bbfe0fc663ee0e3e58d8e9c304f513e568
Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
2019-12-09 15:46:53 -05:00
Thomas Petazzoni
8c51195039 xf86atomic: require CAS support in libatomic_ops
Since AO_compare_and_swap_full() is used by libdrm, AO_REQUIRE_CAS
must be defined before including <atomic_ops.h> so that we are sure
that CAS support will be provided. This is necessary to make sure that
the AO_compare_and_swap_full() function will be provided on all
architectures, including the ones that don't have built-in CAS support
such as SPARCv8.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-06 21:57:12 +00:00
Lauren Post
8c1185d22c Add ARM support into xf86drm.h
This provides support for Xorg interface.  Without this the vivante
samples will hang during close requiring a reboot

[Adapted from yocto project]
Upstream-Status: Pending
Signed-off-by: Lauren Post <lauren.post@freescale.com>
Signed-off-by: Evan Kotara <evan.kotara@freescale.com>
[Thomas: change CAS code to only be used on ARMv6/ARMv7, and not
ARMv4/ARMv5, which don't support ldrex/strex. If no CAS implementation
is provided libdrm falls back to a system call for locking/unlocking.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
---
Changes v1 -> v2:
  - add comment explaining exclusion of ARMv4/ARMv5 and lower
2019-12-05 22:35:58 +01:00
Peter Seiderer
8de2696213 meson.build: fix intel atomics detection
Use the stronger compiler.link() test (instead of the weaker
compiler.compile()) to fix the intel atomics detection.

Fixes false positive in case of sparc compile (buildroot toolchain).

Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-05 13:25:30 +00:00
Alex Deucher
02e1d0ff8b amdgpu: add new marketing names from 19.30
Add new marketing names.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-12-04 17:26:44 -05:00
Pierre-Eric Pelloux-Prayer
325a063ab5 gitlab-ci: update to current ci-templates master
To workaround skopeo issues.

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-03 16:17:14 +01:00
Ross Burton
cd77f114ca tests/nouveau/threaded: adapt ioctl signature
POSIX says ioctl() has the signature (int, int, ...) but glibc has decided to
use (int, unsigned long int, ...) instead.

Use a #ifdef to adapt the replacement function as appropriate.

Signed-off-by: Ross Burton <ross.burton@intel.com>

[Taken from https://raw.githubusercontent.com/openembedded/openembedded-core/master/meta/recipes-graphics/drm/libdrm/musl-ioctl.patch]
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-28 22:01:34 +01:00
xinxu@loongson.cn
0287602015 tests/amdgpu/basic_tests.c: change BUFFER_SIZE used in Userptr Test adjust to PAGE_SIZE
Userptr Test will fail on PAGE_SIZE bigger than BUFFER_SIZE(8 * 1024)

Signed-off-by: xinxu <xinxu@loongson.cn>


(cherry picked from commit fb7dfdc5fb58795365b70117c3eb625f2edb8f06)
2019-11-25 21:23:43 -05:00
Devarsh Thakkar
a2d588fe12 modetest: Add support for setting mode having floating vertical refresh rate
For the scenario where user may require to modeset with a mode
supporting a fractional value for vertical refresh-rate,
appropriate mode can be selected by searching for mode
having matching fractional vertical refresh rate using
below equation.

vrefresh = (1000 * pixel clock) / (htotal * vtotal) Hz.

We do this way since driver doesn't return float value of vrefresh
as it use int for vrefresh in struct drm_mode_info, but we can derive
the actual value using pixel clock, horizontal total size and
vertical total size values.

So for e.g. if user want to select mode having 59.94 Hz as refresh rate
then with this patch it be can done as shown in below command,
given there is an appropriate mode is available :

modetest -M xlnx -s 39:1920x1080-59.94@BG24 -v

NOTE: Above command was tested on xilinx DRM driver with DP
monitor which was supporting mode having 59.94 Hz refresh rate.

V2: Update commit message
V3: Update with below changes as per review comments :
  1) Use epsilon for vrefresh comparison
  2) Use implicit type-casting wherever possible
V4: Keep patch version history on main commit message

Signed-off-by: Devarsh Thakkar <devarsh.thakkar@xilinx.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2019-11-25 16:13:43 +02:00
Eric Engestrom
9d48895425 gitlab-ci: add PowerPC build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-23 00:37:06 +00:00
Eric Engestrom
a39c34e64a gitlab-ci: add aarch64 & armhf builds
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-15 03:10:56 +00:00
Eric Engestrom
202d10a9e2 gitlab-ci: add x86 (32 bits) build
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-15 03:07:21 +00:00
Eric Engestrom
55be53d65f gitlab-ci: set up cross build infra
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-15 03:05:53 +00:00
Eric Engestrom
1128fa10d6 gitlab-ci: drop arch build down to daily builds
Suggested-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-12 23:37:41 +00:00
Simon Ser
d5682defcd Fix missing stdlib includes in xf86drmMode.h
Including xf86drmMode.h results in undefined references to uint32_t
and ssize_t. Include the stdlib headers that define them to allow the
file to be included without xf86drm.h.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-12 00:16:58 +00:00
Eric Engestrom
73d826be4d meson: drop old symbols check environment
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
dbd4320ad6 tegra: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
451e054328 radeon: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
0cfa21d55e omap: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
574778100e nouveau: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
35fa20f1fd libkms: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
1386b99027 intel: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
6c819350af freedreno: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
2763cd390e exynos: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
ff832d734b etnaviv: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
791297e94d amdgpu: convert to new symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
303cf6bbf3 meson: import Mesa's symbols check script
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Eric Engestrom
a7996fda4c freedreno: drop leftover symbol from the export list
Fixes: 09cbccff55 ("freedreno: remove deprecated ringmarker API")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-11 22:57:14 +00:00
Chunming Zhou
0a7ad7df14 libdrm: wrap new flexible syncobj query interface v2
v2: nit-picks fix

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Christian König <Christian.Koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
For the xf86drm.[ch] part : Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-26 03:11:14 +00:00
Chunming Zhou
07f6717595 sync up drm.h
a) delta: drm: use pad as flags in drm_syncobj_timeline_array.
    b) Generated using make headers_install.
    c) Generated from origin/drm-misc-next commit 949561eb85bcee10248e7da51d44a0325d5e0d1b"

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
2019-10-26 03:11:14 +00:00
Eric Engestrom
c69c9c4f4e gitlab-ci: pre-build containers to improve CI run time and reliability
Shaves about 50% off the build time on both debian and arch builds.
(yeah, I know, it's very small anyway compared to mesa, but we might
 want to add more things in the future)

This also makes the build no longer dependent on external websites:
once the image is build, only fdo-internal services are used.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-10-20 20:08:57 +01:00
Eric Engestrom
fc933651b1 Revert "Revert "libdrm: remove autotools support""
The external tooling issue has been fixed, so we can delete autotools
again :)
2019-10-18 18:05:45 +01:00
Marek Olšák
0190f49a13 Bump the version to 2.4.100 for autotools 2019-10-16 17:35:55 -04:00
Marek Olšák
51e3bb5665 Revert "libdrm: remove autotools support"
This reverts commit f057dc91e9.
2019-10-16 17:33:28 -04:00
Marek Olšák
05734951d6 Bump the version to 2.4.100 2019-10-16 15:27:05 -04:00
Marek Olšák
00320d7d68 amdgpu: add amdgpu_cs_query_reset_state2 for AMDGPU_CTX_OP_QUERY_STATE2
This is a better GPU reset query.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-10-15 15:20:38 -04:00
Marek Olšák
9a61cf4e0e include: update amdgpu_drm.h
Generated from kernel commit:
    815fb4c9d7da862 "drm/amdgpu: return tcc_disabled_mask to userspace"

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-10-15 14:30:31 -04:00
Nirmoy Das
3b0a41d93b test/amdgpu: don't free unused bo handle
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-10-15 13:18:12 +02:00
Eric Engestrom
f057dc91e9 libdrm: remove autotools support
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-14 16:07:20 +00:00
Eric Engestrom
e4f090f3c2 RELEASING: update instructions to use meson instead of autotools
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2019-10-14 15:57:26 +00:00
Eric Engestrom
dddeff5028 *-symbols-check: let meson figure out how to execute the scripts
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-10-04 09:43:00 +01:00
Emil Velikov
9b1e084253 *-symbols-check: use normal shell over bash
None of the tests are bash specific. Tested with bash, zsh, dash, mksh
and ksh.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Niclas Zeising <zeising@daemonic.se>
Reviewed-by: Niclas Zeising <zeising@daemonic.se>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-10-04 09:42:46 +01:00
Niclas Zeising
4083e8f2c6 meson.build: Fix header detection on FreeBSD
FreeBSD requires sys/types.h for sys/sysctl.h, add it as part of the
includes when checking for headers.
Instead of splitting out the check for sys/sysctl.h from the other
header checks, just add sys/types.h to all header checks.

v2 [Emil]
 - add inline comment
 - drop bash/sh hunk

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Niclas Zeising <zeising@daemonic.se>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-10-04 09:36:07 +01:00
Niclas Zeising
7e46f4dc80 meson.build: Fix typo
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-09-28 12:04:57 +01:00
Le Ma
0c427545cd tests/amdgpu: add the missing deactivation case for dispatch test
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-18 07:54:26 -05:00
Guchun Chen
c51809fa67 amdgpu: add ras feature capability check in inject test
When running ras inject test, it's needed to be aligned
with kernel's ras enablement.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-16 07:57:10 -05:00
Guchun Chen
58fc6d6eae amdgpu: add ras inject unit test
Both UMC and GFX ras single_correctable
inject tests are added.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-16 07:57:10 -05:00
Guchun Chen
018169bfba amdgpu: delete test configuration file
Json package dependence is removed from amdgpu_test,
so this json configuration file is not needed any more.

Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-16 07:57:10 -05:00
Guchun Chen
cb637bc17b amdgpu: remove json package dependence
Except CUnit library, no additional external
library should be needed when compiling amdgpu_test.
This will keep this binary self containing.

Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-16 07:57:10 -05:00
Eric Engestrom
827a2a2042 meson: fix sys/mkdev.h detection on Solaris
On Solaris, sys/sysmacros.h has long-deprecated copies of major() & minor()
but not makedev().
sys/mkdev.h has all three and is the preferred choice.

Let's make sure we check for all 3 major(), minor() and makedev().

Fixes build failure with error:
../xf86drm.c: In function ‘drmOpenMinor’:
../xf86drm.c:454:30: error: implicit declaration of function ‘makedev’ [-Werror=implicit-function-declaration]
  454 |         return drmOpenDevice(makedev(DRM_MAJOR, minor), minor, type);
      |                              ^~~~~~~

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Tested-by: Alan Coopersmith <alan.coopersmith@oracle.com>
2019-09-14 22:22:03 +01:00
Anusha Srivatsa
10cd9c3da8 intel: sync i915_pciids.h with kernel
Add the new CML PCI IDS.

Align with kernel commit:
bfc4c359b2822 ("drm/i915/cml: Add Missing PCI IDs")

This is in sync with kernel header as of:
0747590267e7 ("drm-tip: 2019y-08m-30d-18h-03m-18s UTC integration manifest")

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2019-09-06 13:12:14 -07:00
Guchun Chen
14922551aa amdgpu: add umc ras inject test configuration
Both umc single_correctable and multi_uncorrectable
inject types are added.

Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-08 12:20:27 -05:00
Guchun Chen
1ef1e4db96 tests/amdgpu/ras: refine ras inject test
Ras inject test framework is invalid with original codes,
so refine it to make it work on top of kernel ras inject
feature enablement.

Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-08 12:19:38 -05:00
Guchun Chen
0000162504 amdgpu: add gfx ras inject configuration file
This configuration file will be picked up when
running gfx ras inject tests by amdgpu_test tool.
For the time being, only add those tests that are
successfully trafficked. In addition, this file
can also be modified by user to add or delete ras
inject unit tests for different IP blocks/subblocks.

Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-08 12:19:06 -05:00
Le Ma
98996fd021 tests/amdgpu: divide dispatch test into compute and gfx
for better clarification

v2: accordingly change dispatch_test caller in gpu_reset test

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 22:08:01 -05:00
Flora Cui
b0f2d60ba7 tests/amdgpu: disable reset test for now
ASIC hang randomly.

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02 22:07:18 -05:00
Rodrigo Vivi
6652cf8673 intel: Add support for EHL
Add the PCI ID import for EHL.

Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-07-29 17:00:12 -07:00
Rodrigo Vivi
e4f164575c intel: add the TGL 12 PCI IDs and macros
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-07-29 17:00:08 -07:00
Lucas De Marchi
3bda60fd14 intel: sync i915_pciids.h with kernel
Straight copy from the kernel file, aligned with drm-intel-next-queued
commit cb823ed9915b ("drm/i915/gt: Use intel_gt as the primary object
for handling resets")

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-07-29 16:55:40 -07:00
Flora Cui
3aba0f3889 tests/amdgpu: add gpu reset test
1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
2019-07-19 16:42:28 +08:00
Flora Cui
0247b19dc0 tests/amdgpu: fix for dispatch/draw test
1. skip test if there's no desired ring
2. clear shader buffer
3. update command buffer for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2019-07-19 16:42:19 +08:00
Eric Engestrom
331e51e32f xf86drm: dedupe drmGetDeviceName() logic
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-03 13:06:21 +01:00
Eric Engestrom
6869e4cea7 xf86drm: use max size of drm node name instead of arbitrary size
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-03 13:06:21 +01:00
Eric Engestrom
0d5ea07736 xf86drm: dedupe #defines
Adapted from a local patch carried by DragonFlyBSD:
bc056f88f7/graphics/libdrm/files/patch-xf86drm.h

Patch is sadly uncredited (a bot authored the commit), so I can't credit
the author here either.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-03 13:06:21 +01:00
Jonathan Gray
293b95e815 xf86drm: open correct render node on non-linux
drm render nodes have the same major as drm primary devices but offset
the minor by a base of 128.

I expected the name of the device to have numbering starting at 0 when
these non-linux codepaths were added (before OpenBSD had render nodes).

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-03 12:28:15 +01:00
Jonathan Gray
13e2c35603 xf86drm: test for render nodes before primary nodes
Unlike Linux the OpenBSD primary "drm" device name is substring of the
"drmR" render node device name and strncmp() tests resulted in render
nodes being flagged as primary nodes.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-03 12:26:54 +01:00
Ilia Mirkin
dcc586c66c tests/util: fix incorrect memset argument order
Make it actually clear the LUT.

Reported-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-03 00:19:39 -04:00
Marek Olšák
b2103fa325 Bump version to 2.4.99 2019-07-02 14:36:25 -04:00
Michel Dänzer
1ec0df8a25 amdgpu: Rename fd_mutex/list to dev_mutex/list
Seems to better reflect what they're for.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-07-01 11:32:05 +02:00
Michel Dänzer
a1bde9b6d8 amdgpu: Add BO handle to table in amdgpu_bo_create
Simplifies its callers.

dev->bo_table_mutex is now always held when amdgpu_bo_create is called
(this was already the case in amdgpu_bo_import).

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-07-01 11:31:59 +02:00
Michel Dänzer
b12282db9c amdgpu: Pass file descriptor directly to amdgpu_close_kms_handle
And propagate drmIoctl's return value.

This allows replacing all remaining open-coded DRM_IOCTL_GEM_CLOSE
ioctl calls with amdgpu_close_kms_handle calls.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-07-01 11:31:51 +02:00
Marek Vasut
cecedcb8a1 etnaviv: Fix double-free in etna_bo_cache_free()
The following situation can happen in a multithreaded OpenGL application.
A BO is submitted from etna_cmd_stream #1 with flags set for read.
A BO is submitted from etna_cmd_stream #2 with flags set for write.
This triggers a flush on stream #1 and clears the BO's current_stream
pointer. If at this point, stream #2 attempts to queue BO again, which
does happen, the BO will be added to the submit list twice. The Linux
kernel driver correctly detects this and warns about it with "BO at
index %u already on submit list" kernel message.

However, when cleaning the BO cache in etna_bo_cache_free(), the BO
which was submitted twice will also be free()d twice, this triggering
a glibc double free detector.

The fix is easy, even if the BO does not have current_stream set,
iterate over current streams' list of BOs before adding the BO to it
and verify that the BO is not yet there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2019-06-28 16:17:19 +02:00
Michel Dänzer
46cb2aa1ed amdgpu: Update amdgpu_bo_handle_type_kms_noimport documentation
To reflect current reality.

Reviewed-by: Christian König <christian.koenig@amd.com>
2019-06-25 17:59:10 +02:00
Michel Dänzer
e246114c46 amdgpu: Move union declaration to top of amdgpu_cs_ctx_override_priority
Avoids compiler warning:

../../amdgpu/amdgpu_cs.c: In function 'amdgpu_cs_ctx_override_priority':
../../amdgpu/amdgpu_cs.c:155:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
  union drm_amdgpu_sched args;
  ^~~~~

Reviewed-by: Christian König <christian.koenig@amd.com>
2019-06-25 17:58:31 +02:00
Lucas Stach
8849aa87fb etnaviv: drop etna_bo_from_handle symbol
There is no implementation and also no users, so there is no point
in keeping it in the API.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-06-24 16:21:07 +02:00
Ilia Mirkin
08bd098d84 util: fix include path for drm_mode.h
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-06-22 14:56:49 -04:00
Ilia Mirkin
f2da507a04 modetest: add FP16 format support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:36 -04:00
Ilia Mirkin
5d0e9dec3f modetest: add the ability to specify fill patterns on the commandline
Instead of hacking the binary every time, we can now specify directly.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:33 -04:00
Ilia Mirkin
bfc469f241 modetest: add C8 support to generate SMPTE pattern
This includes logic to configure the LUT accordingly.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:29 -04:00
Ilia Mirkin
557d1a2e6f modetest: add an add_property_optional variant that does not print errors
As new features are added and others are declared to be legacy, it's
nice to be able to implement fallbacks. As such, create a
property-setting variant that does not generate errors which can very
well be entirely expected.

Will be used for gamma control in a future change.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:25 -04:00
Ilia Mirkin
78ea933460 modetest: don't pretend that atomic mode includes a format
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:20 -04:00
Ilia Mirkin
def955c09e util: add cairo drawing for 30bpp formats when available
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:14 -04:00
Ilia Mirkin
b59d14e7fc util: add fp16 format support
This change adds support for all current patterns.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:08 -04:00
Ilia Mirkin
e5442195fb util: add gradient pattern
The idea is to have a horizontal pattern split into two with the top and
bottom halves having different precision. This allows one to see whether
10bpc support is working properly or not, as there are many pieces to
the puzzle beyond the basic format support (gamma ramps, bpc encodings,
etc).

This is really only useful on 10bpc formats, but we also add support for
8bpc formats to ease testing. In the future, this could be applied to
16bpc formats as well.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:34:05 -04:00
Ilia Mirkin
32401fe5ce util: fix MAKE_RGBA macro for 10bpp modes
We need to shift the values up, otherwise we'd end up with a negative
shift. This works for up-to 16-bit components, which is fine for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:33:55 -04:00
Ilia Mirkin
8d27deced9 util: add C8 format, support it with SMPTE pattern
This also adds a helper to generate a color LUT, which has to be used in
conjunction with the C8 indexed format.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2019-06-22 13:29:54 -04:00
Leo Liu
0eaf5df553 tests/amdgpu/vcn: add VCN2.0 decode support
With different register offsets from VCN1.0

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-06-21 12:46:21 -04:00
Tao Zhou
dbab346bb1 libdrm/amdgpu: add new vram type (GDDR6) for navi10
AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10

Reviewed-by: Tim Writer <Tim.Writer@amd.com>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-06-21 12:46:18 -04:00
Hawking Zhang
9f2e558ca3 libdrm/amdgpu: add new member in drm_amdgpu_device_info for navi10
pa_sc_tile_steering_override is a new member introduced for gfx10

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-06-21 12:46:12 -04:00
Huang Rui
74efcc7b9f amdgpu: add navi family id
Reviewed-by: Tim Writer <Tim.Writer@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-06-21 12:46:06 -04:00
Chunming Zhou
5db0f7692d enable syncobj test depending on capability
Feature is controlled by DRM_CAP_SYNCOBJ_TIMELINE drm capability.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2019-06-11 15:55:33 +02:00
Chunming Zhou
f3e6d22baa update drm.h
a) delta: only DRM_CAP_SYNCOBJ_TIMELINE
   b) Generated using make headers_install.
   c) Generated from origin/drm-misc-next commit 982c0500fd1a8012c31d3c9dd8de285129904656"

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Suggested-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2019-06-11 15:54:06 +02:00
Michel Dänzer
922d929942 amdgpu: Add amdgpu_cs_syncobj_transfer to amdgpu-symbol-check
Fixes make check. Trivial.
2019-05-16 14:43:22 +02:00
Chunming Zhou
7ab471ed85 add syncobj timeline tests v3
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
6a72661c33 wrap transfer interfaces
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
6bb5cc174b expose timeline signal/export/import interfaces v2
v2: adapt to new one transfer ioctl

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
12712eb6e3 add timeline signal/transfer ioctls v2
v2: use one transfer ioctl

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
46f930d962 wrap syncobj timeline query/wait APIs for amdgpu v3
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
ec6ae51e80 add timeline wait/query ioctl v2
v2: drop export/import

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Chunming Zhou
642ec7fc34 add cs chunk for syncobj timeline
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-16 12:07:18 +02:00
Seung-Woo Kim
b39377d66a xf86drm: Fix possible memory leak with drmModeGetPropertyPtr()
In drmModeGetPropertyPtr(), from upper error path, it calls free
but with just next error path, it does not call. Fix the possible
memory leak.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-05-03 12:47:42 +01:00
Seung-Woo Kim
6a7d1329db tests/libkms-test-plane: fix possbile memory leak
The pointer p aquired with drmModeGetPlane() is not free in error
path. Fix possible memory leak by calling drmModeFreePlane() in
the error path.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2019-04-25 11:08:21 +01:00
Hemant Hariyani
357ef59882 libdrm: omap: Add DRM_RDWR flag to dmabuf export
Allows mmap on dmabuf fd with MAP_SHARED and PROT_WRITE.

This fixes boot failures with Android (likely w/ closed source
user-space drivers) that were caused due to mmap() returning
error.

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
[picked and updated commitmsg from http://git.ti.com/cgit/cgit.cgi/android/external-libdrm.git/]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Alistair Strachan <astrachan@google.com>
[jstultz: Tweaked commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:58:27 +01:00
Adrian Salido
763f646d7f libdrm: reduce number of reallocations in drmModeAtomicAddProperty
When calling drmModeAtomicAddProperty allocation of memory
happens as needed in increments of 16 elements. This can be very
slow if there are multiple properties to be updated in an Atomic
Commit call.

Increase this to as many as can fit in a memory PAGE to avoid
having to reallocate memory too often.

Also this patch has a small one line perf tweak in
drmModeAtomicDuplicate() to only memcpy items to the cursor
position in order avoid copying the entire item array if its
mostly empty.

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[jstultz: Expanded commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:58:16 +01:00
Prabhanjan Kandula
225d73fd3b libdrm: Avoid additional drm open close
Avoid additional drm device open and close.

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:57:59 +01:00
John Stultz
51553dd0e0 libdrm: amdgpu: Initialize unions with memset rather than "= {0}"
Clang complains when initializing unions using "= {0}"
so instead use memset.

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:57:26 +01:00
Sean Paul
ebbb8f9cbf libdrm: Use mmap64 instead of __mmap2
__mmap2 isn't supported on all platforms, mmap64 is the right way
to do this in android.

Also folds in a fix from Stéphane Marchesin <marcheu@chromium.org>

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[jstultz: Folded in Stéphane's fix]
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:55:13 +01:00
John Stultz
818033deff libdrm: Android.mk: Add minimal Android platform check
Add a check to error out on Android version K(4.4) or
lower.

This is due to dependency added in a previous commit on mmap64,
which was introduced with Android L.

Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-04-25 10:55:02 +01:00
Emil Velikov
be3b07617f Bump the version to 2.4.98
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-19 16:31:38 +01:00
Bas Nieuwenhuizen
232dc3305d amdgpu: Add context priority override function.
This way we can override the priority of a single context using a
master fd.

Since we cannot usefully create an amdgpu device of a master fd
without the fd deduplication kicking in this takes a plain fd.

This can be used by e.g. radv to get high priority contexts using
a master fd from the primary node or a lease.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2019-04-18 10:39:32 +02:00
Lubomir Rintel
0b474eab3d tests/util: Add armada-drm driver
This makes the test utilities work with the Armada driver without the
necessity of using the -M argument.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-17 18:52:04 +01:00
Emil Velikov
439a4c0361 Revert "libdrm: Fix issue about differrent domainID but same BDF"
This reverts commit 56c21f877b.

There were issues pointed out during review that were not addressed.
Would love to have this re-land, once those are addressed.
2019-04-17 18:31:31 +01:00
Fritz Koenig
f8f8b2b9b0 tests/modetest: add QCOM_COMPRESSED to supported modifiers list
Signed-off-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-17 18:28:08 +01:00
Eric Engestrom
360292c7ab fix various typos
Saw a couple of typos fixes in the patch DragonFlyBSD carries [1], so
I ran codespell (a spell checker for code) on the whole repo.

[1] https://github.com/DragonFlyBSD/DPorts/blob/master/graphics/libdrm/files/patch-xf86drm.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-17 18:23:25 +01:00
Eric Engestrom
ad8bec1ed8 amdgpu/tests: drop unused local vars
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-17 18:18:10 +01:00
Pan, Xinhui
fcf80e2fd7 amdgpu: Fix a structure initialization issue
struct drmPciBusInfo has been aligned to 6 bytes. So memcmp will access
the last byte which is not initialized.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-12 11:38:41 -05:00
Ayan Halder
210bfdf8f8 headers: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f

The changes were as follows :-

core: (drm.h, drm_fourcc.h, drm_mode.h)
- Added 'struct drm_syncobj_transfer', 'struct drm_syncobj_timeline_wait' and 'struct drm_syncobj_timeline_array'
- Added various DRM_IOCTL_SYNCOBJ_ ioctls
- Added some new RGB and YUV formats
- Added 'DRM_FORMAT_MOD_VENDOR_ALLWINNER'
- Added 'SAMSUNG' and Arm's 'AFBC' and 'ALLWINNER' format modifiers
- Added 'struct drm_mode_rect'

i915:
- Added struct 'struct i915_user_extension' and various 'struct drm_i915_gem_context_'
- Added different modes of per-process Graphics Translation Table

Changes from v1:-
- Removed the changes to 'msm_drm.h' as it breaks the build for 'freedreno' platform.

Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-12 16:33:38 +01:00
xinhui pan
b4fbc6d70c drm/amdgpu: support test mask
support per device test mask. Skip inject test on non-server card.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-04 13:45:19 -05:00
xinhui pan
b21d23e3ba amdgpu: add ras tests
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-04 13:44:37 -05:00
Alex Deucher
028cbfff63 amdgpu: update amdgpu_drm.h from drm-next for 5.2
From drm-next commit b4e4538a0ab5079ae5dc401970e11f0ff2ba13a7

Adds support for:
- RAS queries
- context priority updates
- CS chunks support for scheduled dependencies
- IB flag for GDS max wave id

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-04 13:42:16 -05:00
Gurchetan Singh
4835d74cc1 virtgpu: Update kernel header
Generated using make headers_install.

This brings in the in/out fence support for explicit
synchronization.

v2: don't use experimental kernel branch

Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2019-04-03 20:11:55 -04:00
Anusha
ae836decb4 intel: sync i915_pciids.h with kernel
Add CML and EHL PCI IDs, and one more for ICL. This is in sync with
kernel header as of b024ab9b2d3a ("drm/i915/bios: iterate over child
devices to initialize ddi_port_info")

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-25 14:34:13 -07:00
Cui, Flora
a85b31c973 tests/amdgpu: minor fix for dispatch/draw test
1. clear cmd buffer
2. make amdgpu_memcpy_dispatch_test static
3. tab/space fix

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-20 21:38:52 -05:00
Cui, Flora
852a9d20ad tests/amdgpu: add memcpy draw test
add memcpy draw test for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Tested-by: Rui Teng <rui.teng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Cui, Flora
00dd9b72a1 tests/amdgpu: add memset draw test
add memset draw test for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Tested-by: Rui Teng <rui.teng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Cui, Flora
c1ced0bafd tests/amdgpu: add memcpy dispatch test
add memcpy dispatch test for gfx9

Signed-off-by: Flora Cui <flora.cui@amd.com>
Tested-by: Rui Teng <rui.teng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Cui, Flora
8db4e2db41 tests/amdgpu: add memset dispatch test
add memset dispatch test for gfx9
v2: disable dispatch test for other ASICs

Signed-off-by: Flora Cui <flora.cui@amd.com>
Tested-by: Rui Teng <rui.teng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Cui, Flora
8c6dbd7938 tests/amdgpu: add deadlock test for sdma
deadlock test for sdma will cause gpu recoverty.
disable the test for now until GPU reset recovery could survive at least
1000 times test.

v2: add modprobe parameter

Reviewed-and-tested-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Alex Deucher
c8bc69a165 amdgpu: add marketing name for AMD Radeon VII
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-03-18 10:49:52 -05:00
Andreas Baierl
4735ca71af xf86drm: Fix segmentation fault while parsing device info
This fixes a bug, which was introduced with commit ee798b98
"xf85drm: de-duplicate drmParse{Platform.Host1x}{Bus,Device}Info".
where accessing *compatible[i] with i>0 results in a segfault.

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Fixes: ee798b9847 "xf85drm: de-duplicate drmParse{Platform.Host1x}{Bus,Device}Info"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
[Eric: add the same fix to the free() below]
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-12 11:55:31 +00:00
Tapani Pälli
0b032a645e libkms: update list of intel_drivers for Android build
Add new iris driver, remove deprecated ilo driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-11 09:12:41 +02:00
Seung-Woo Kim
d54e546852 configure.ac fix build error for config.h in autotools
After the commit 0926f0af54 ("meson,configure: include config.h
automatically"), there is build error for autotools because
config.h is not included. Fix the error by adding "-include
config.h" to CPPFLAGS instead of CFLAGS from configure.ac.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=106561
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 0926f0af54 "meson,configure: include config.h automatically"
2019-02-26 10:39:36 +00:00
Emily Deng
56c21f877b libdrm: Fix issue about differrent domainID but same BDF
For multiple GPUs which has the same BDF, but has different domain ID,
the drmOpenByBusid will return the wrong fd when startx.

The reproduce sequence as below:
1. Call drmOpenByBusid to open Card0, then will return the right fd0, and the
fd0 is master privilege;
2. Call drmOpenByBusid to open Card1. In function drmOpenByBusid, it will
open Card0 first, this time, the fd1 for opening Card0 is not master
privilege, and will call drmSetInterfaceVersion to identify the
domain ID feature, as the fd1 is not master privilege, then drmSetInterfaceVersion
will fail, and then won't compare domain ID, then return the wrong fd for Card1.

Solution:
First loop search the best match fd about drm 1.4.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-22 16:02:12 -05:00
Eric Engestrom
1592d471bb gitlab-ci: fix archlinux builds
base/archlinux has been replaced with archlinux/base, which is
maintained directly by the archlinux community.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-19 11:59:12 +00:00
Eric Engestrom
e09f327765 freedreno: revert bad freedreno/atomic_ops commits
This reverts 6d2379857b "xf86atomic: #undef internal define"
and b541d21a0a "freedreno: remove always-defined #ifdef".

I didn't realise at the time that freedreno/freedreno_ringbuffer.h gets
installed, and then used by Mesa for instance. These two commits were
fine in libdrm, but broke Mesa which needs to use struct fd_ringbuffer
but doesn't need to access ::refcnt. The hack that I removed serves to
keep the struct at the correct size while only exposing the ::refcnt
member within libdrm.

Fixes: 6d2379857b "xf86atomic: #undef internal define"
Fixes: b541d21a0a "freedreno: remove always-defined #ifdef"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-19 09:50:26 +00:00
Eric Engestrom
eba6609b7b xf86drm: fix return type for drmIsMaster()
Xserver has struct members named `bool`, which means the last commit
breaks its build with errors like this:

  error: two or more data types in declaration specifiers
  Bool bool;
       ^

Fix this by making it return a 0/1 integer, with the same semantic as
the boolean it was before.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109587
Fixes: 17dfe3ac93 "xf86drm: Add drmIsMaster()"
Cc: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-08 18:52:36 +00:00
Christopher James Halse Rogers
17dfe3ac93 xf86drm: Add drmIsMaster()
We can't use drmSetMaster to query whether or not a drm fd is master
because it requires CAP_SYS_ADMIN, even if the fd *is* a master fd.

Pick DRM_IOCTL_MODE_ATTACHMODE as a long-deprecated ioctl that is
DRM_MASTER but not DRM_ROOT_ONLY as the probe by which we can detect
whether or not the fd is master.

This is useful for code that might get master by open()ing the drm device
while no other master exists, but can't call drmSetMaster itself because
it's not running as root or is in a container, where container-root isn't
real-root.

v2: Use the AUTH_MAGIC request rather than MODE_ATTACHMODE, as it's more
    clearly related to master status.

v3: [Emil] Don't expose internals, check for -EACCES.

Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-07 17:43:01 +00:00
Rodrigo Vivi
70a1ae89be intel: sync i915_pciids.h with kernel
Straight copy from the kernel file.

Add more PCI Device IDs for Coffee Lake, Ice Lake,
and Amber Lake. It also include a reorg on Whiskey Lake IDs.

Align with kernel commits:

5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-02-04 10:45:53 -08:00
Emil Velikov
ee798b9847 xf85drm: de-duplicate drmParse{Platform.Host1x}{Bus,Device}Info
The functions are virtually identical, fold them up.

v2: foo -> tmp_name (Eric)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-04 15:28:55 +00:00
Emil Velikov
3df8a7f01a xf86drm: fallback to MODALIAS for OF less platform devices
Some devices can lack OF data or it may not be available in the uevent
file. Fallback to the MODALIAS data in those cases.

We strip any leading "MODALIAS=.*:" thus the resulting information is
compatible with existing code in Mesa.

v2: foo -> tmp_name

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Lucas Stach <l.stach@pengutronix.de> (v1)
2019-02-04 15:26:32 +00:00
Alex Deucher
6415bd3ced amdgpu: add some raven marketing names
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01 00:26:48 -05:00
Marek Olšák
b7a7a90336 Bump the version to 2.4.97 2019-01-22 11:18:47 -05:00
Marek Olšák
f19afaa519 amdgpu: add a faster BO list API
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-01-16 16:39:25 -05:00
Marek Olšák
98cff551b0 amdgpu: update amdgpu_drm.h
it's in kernel 5.0

Reviewed-by: Christian König <christian.koenig@amd.com>
2019-01-16 11:57:18 -05:00
Alex Deucher
cfab2fc33d amdgpu: update to latest marketing names from 18.50
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-10 10:15:59 -05:00
Eric Engestrom
403f3c92fd README: reflow the project description to improve readability
Also, move the sentence about "who would use libdrm" into its own paragraph,
as it is something people discovering libdrm will want to know.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-03 18:41:32 +00:00
Eric Engestrom
6d2379857b xf86atomic: #undef internal define
Thanks to the #error just above, any file including this header can only
see one state for this macro: defined, with the value `1`.
Let's just #undef it once we're done using it in here so that other
files don't misconstrue any meaning to it.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-03 18:36:46 +00:00
Eric Engestrom
b541d21a0a freedreno: remove always-defined #ifdef
While at it, let's include xf86atomic.h explicitly, instead of relying
on some other file accidentally including it before including this file.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-03 18:36:26 +00:00
Mauro Rossi
597725e951
android: Fix 32-bit app crashing in 64-bit Android
Seemingly the 64-bit int is always aligned to 8 in LP64.
But this is not hold in LP32.

Consequently sizeof(gralloc_drm_handle_t) are different
between LP64 (which is 18 ints) and LP32 (which is 16 ints).
As a result, 32-bit apps will crash in 64-bit OS since the
checking handle->base.numInts != GRALLOC_GBM_HANDLE_NUM_INTS
is true.

Fix it by always aligning 64-bit int to 8. Besides, to avoid
additional padding, just exchange the order of data_owner
and modifier. It aligns modifier to 8 natually.
This makes gralloc_drm_handle_t fit in 16 ints perfectly.

(v2) gralloc_drm_handle.h patch now applied in gralloc_handle.h
     and GRALLOC_HANDLE_VERSION updated to 4

Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
2018-12-18 21:18:19 +01:00
Lucas De Marchi
2c02f1e610 gitignore: add _build
This is the directory used by meson/autotools (at least in the
.gitlab-ci configuration) so ignore the whole dir.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-17 12:49:55 -08:00
Lucas De Marchi
d8e615f975 gitignore: sort file
LANG=C sort -u .gitignore | sponge .gitignore

This way it's easier to keep track of the entries.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-17 12:49:55 -08:00
Leo Liu
866ada1b37 tests/amdgpu/vcn: fix the nop command in IBs
Just make them properly i.e. put 0 to the Nop reg

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-14 12:21:12 -05:00
François Tigeot
8f2e09251e libdrm: Use DRM_IOCTL_GET_PCIINFO on DragonFly
It is a cleaner and less fragile way to get PCI IDs than the one
currently used by local DPorts patches.

Signed-off-by: François Tigeot <ftigeot@wolfpond.org>
2018-12-13 20:39:02 -05:00
François Tigeot
200e9e98a2 xf86drm: implement drmParseSubsystemType for DragonFly
Like on OpenBSD, the DragonFly BSD kernel only contains
pci drm drivers.

Signed-off-by: François Tigeot <ftigeot@wolfpond.org>
2018-12-13 20:39:02 -05:00
Andrey Grodzovsky
ba45adb2a1 amdgpu/test: Enable deadlock test for CI family (gfx7)
I retested GPU recovery with  Bonaire ASIC and it works.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
2018-12-11 15:41:06 -05:00
Christian König
b28b823762 amdgpu: add VM test to exercise max/min address space
Make sure the kernel doesn't crash if we map something at the minimum/maximum address.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-12-05 14:41:17 +01:00
Eric Anholt
89700ab0aa drm: Attempt to parse SPI devices as platform bus devices.
For ARM systems with tinydrm displays attached to SPI, the bus name is
/spi but we have platform device info for the rest.  Fixes
eglInitialize() failures on hx8357d since the EGL_EXT_device_drm
changes.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 20:36:13 -08:00
Eric Anholt
9b28c5aea3 Avoid hardcoded strlens in drmParseSubsystemType().
Having people count characters is error-prone, when we could just have
a computer do it.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 20:36:02 -08:00
Eric Engestrom
e642f480b8 tests: skip drmdevice test if the machine doesn't have any drm device
Error message was invalid too, negative values aren't the number of
devices, they're errno error codes.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2018-11-11 18:39:57 +00:00
Eric Engestrom
8c1fddc640 meson: fix typo in compiler flag
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-11-09 10:59:11 +00:00
Eric Engestrom
0f2f38bf06 xf86drmHash: remove unused loop variable
Reported-by: Jan Vesely <jano.vesely@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
2018-11-09 10:59:11 +00:00
Andrey Grodzovsky
0be850441f amdgpu/test: Disable deadlock tests for all non gfx8/9 ASICs.
Since only for those ASICs gpu reset is enabled by deafult.
Also update disable message and fix identation .

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-02 16:22:49 -04:00
Andrey Grodzovsky
b3dec018df amdgpu/test: Add illegal register and memory access test v2
Illegal access will cause CP hang followed by job timeout and
recovery kicking in.
Also, disable the suite for all APU ASICs until GPU
reset issues for them will be resolved and GPU reset recovery
will be enabled by default.

v2:
Add KV to deasbled APUs list and add comments regarding
necessary kernel amdgpu paramteres to run the tests.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-01 14:57:49 -04:00
Daniel Vetter
9d07fbf593 doc: Rename README&CONTRIBUTING to .rst
Looks much neater on the gitlab UI, e.g. on my personal libdrm fork:

https://gitlab.freedesktop.org/danvet/drm

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2018-10-17 17:17:19 +02:00
Rob Clark
5a3bdc7add Bump to version 2.4.96
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-16 10:32:43 -04:00
Rob Clark
f94075c3c5 freedreno/msm: fix c90 warning
Wasn't really sure how to switch the silly -Wdeclaration-after-statement
flag off on a per directory basis.  So make the code uglier instead.
2018-10-14 11:23:17 -04:00
Rob Clark
b730f5c8c5 freedreno/kgsl: fix build
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-14 11:23:03 -04:00
Rob Clark
032258b7f7 freedreno/msm: handle ring-reloc to other stateobjs
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:24:12 -04:00
Rob Clark
413a49a068 freedreno/msm: simplify msm_ringbuffer_flush()
Now that it doesn't have to deal with ringmarkers we can simplify the
reloc handling.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:23:54 -04:00
Rob Clark
880871b378 freedreno/msm: use hashtable to track submit.cmds table
With streaming stateobjs to upload uniforms, the submit.cmds table gets
much larger, and iterating over it for each ring to ring reloc starts
getting expensive.

TODO if we have flag to pass when constructing parent rb, we could
avoid dynamically allocating this and bo_table in get_cmd() or bo2idx

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:23:35 -04:00
Rob Clark
5c4722e907 freedreno/msm: simplify emit_reloc_ring() vfunc
Now that it doesn't have to deal with the ringmarker case, we can make
some simplifications.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:23:12 -04:00
Rob Clark
96b625240c freedreno/msm: remove reset of linked rings
The msm_cmd isn't refcount'd, so with stateobj rb's that have
independent lifecycle, this is no longer a safe thing to do.
Really, now that there is a bo-cache for rb's, fd_ringbuffer_reset()
should be deprecated because it adds a bunch of pointless complexity.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:22:49 -04:00
Rob Clark
09cbccff55 freedreno: remove deprecated ringmarker API
It's usage in mesa was removed more than two years ago.  And it stands
in the way of some optimizations needed to reduce the overhead of hw
stateobjs (ie. CP_SET_DRAW_STATE, where the # of cmds in the submit
ioctl goes up significantly).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:22:20 -04:00
Rob Clark
33faf339c3 freedreno/msm: support suballocation for stateobj rb's
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:21:53 -04:00
Rob Clark
bf001648a9 freedreno: add flags param for rb creation
For now, we want a way for gallium to be able to provide hints for the
upcoming rb suballocation.  But could be useful for other things down
the road.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:20:43 -04:00
Rob Clark
a8a0061926 freedreno: expose refcnt'ing on ringbuffers
Move this out of msm_ringbuffer backend so that the gallium driver can
refcnt rb's

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:18:43 -04:00
Rob Clark
566b1d9f93 freedreno/msm: get rid of ring_bo unref hack
Since 28328298 'freedreno: move ring_cache behind fd_bo_del()' this hack
is no longer necessary.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 17:12:22 -04:00
Rob Clark
f9dadcece6 xf86drmHash: remove redundant zero init
drmMalloc() is already calloc()

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-10-13 15:39:01 -04:00
Andrey Grodzovsky
21f1176458 amdgpu/test: Fix deadlock tests for AI and RV v2
Seems like AI and RV requires uncashed memory mapping to be able
to pickup value written to memory by CPU after the WAIT_REG_MEM
command was already launched.
.
Enable the test for AI and RV.

v2:
Update commit description.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-10-10 14:38:19 -04:00
Andrey Grodzovsky
eabc4cb35c amdgpu/test: Allow BO mapping flags to be passed in tests
v2:
Call amdgpu_bo_va_op_raw directly in amdgpu_bo_alloc_and_map_raw
Move amdgpu_bo_alloc_and_map_raw into C file to avoid including
unistd.h in amdgpu_test.h

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-10-10 14:38:19 -04:00
Thomas Hellstrom
f839258341 libdrm: Allow dynamic drm majors on linux
To determine whether a device node is a drm device node or not, the code
currently compares the node's major number to the static drm major device
number.

This breaks the standalone vmwgfx driver on XWayland dri clients,
https://cgit.freedesktop.org/mesa/vmwgfx
and any future attempt to introduce dynamic device numbers for drm.

So instead of checking for the device major, instead check for the presence
of the /sys/dev/char/<major>:<minor>/device/drm directory.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2018-10-09 14:47:09 +02:00
Emil Velikov
4f1c765396 Bump to version 2.4.95
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-04 15:22:38 +01:00
Emil Velikov
86326a2c53 intel: include i915_pciids.h in the tarball
Fixes: 4e81d4f9c9 ("intel: add generic functions to check PCI ID")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-04 15:22:30 +01:00
Emil Velikov
7dea956d38 Revert "Bump to version 2.4.95"
This reverts commit 6e50a309af.
2018-10-04 15:22:18 +01:00
Emil Velikov
6e50a309af Bump to version 2.4.95
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-04 15:08:17 +01:00
Ayan Kumar Halder
1b18f508c8 libdrm: headers: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 2dc7bad71cd310dc94d1c9907909324dd2b0618f

The changes were as follows :-

  core: (drm.h, drm_fourcc.h, drm_mode.h)
    - Added client capabilities for ASPECT_RATIO and WRITEBACK_CONNECTORS
    - Added Arm AFBC modifiers
    - Added BROADCOM's SAND and UIF modifiers
    - Added Qualcomm's modifiers
    - Added some picture aspect ratio and content type options
    - Added some drm mode flags
    - Added writeback connector id

  amdgpu:
    - Added GEM domain mask
    - Added some GEM flags
    - Added some hardware ip flags
    - Added chunk id and IB fence.
    - Added some query ids

  i915:
    -Added an IOCTL (I915_PARAM_MMAP_GTT_COHERENT)

  qxl:
    - Minor changes

  tegra:
    - Added some comments about struct drm_tegra* members
    - Modified DRM_IOCTL_TEGRA_CLOSE_CHANNEL

  vc4:
    - Added some members for 'struct drm_vc4_submit_cl'

Changes in v2:
    - Mentioned 'libdrm' in the commit header.

Changes in v3:
    - Removed the changes to radeon_drm.h, sis_drm.h and via_drm.h as suggested by
      Emil Velikov <emil.l.velikov@gmail.com>

Changes in v4:
    - Removed the changes to vmwgfx_drm.h as it caused a build break ie
      'make check' failed.

Change-Id: I018a06f65bf4a6a68400ab252b9cd05d041299b3
Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-04 14:51:09 +01:00
Emil Velikov
e08b7f2234 gitlab-ci: pass the correct toggles to configure
Trivial typos - s/admgpu/amdgpu/;s/vmwfgx/vmwgfx/

Fixes: 4a9030dc8b ("add gitlab-ci builds of libdrm")
Cc: Brian Starkey <brian.starkey@arm.com>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-04 14:49:26 +01:00
Ezequiel Garcia
5775741d16 tests/util: Add support for sun4i-drm driver
This is the DRM driver for all Allwinner (sunxi) platforms.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-04 14:46:47 +01:00
Lucas De Marchi
f6b4737e2f android: make symbols hidden by default
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-04 14:42:54 +01:00
Emil Velikov
99c3540dd4 *-symbols-check: error out when using unset variables
It will make bugs like the one fixed with previous patch dead obvious.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-04 14:39:27 +01:00
Emil Velikov
660643e498 automake: set NM before running the tests
Set/export the NM variable since it may not be set already.

Fixes: 4f08bfe96d ("*-symbol-check: Don't hard-code nm executable")
Cc: Heiko Becker <heirecka@exherbo.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-04 14:39:06 +01:00
Daniel Stone
946fa21966 CI: Capture test logs as GitLab artifacts
GitLab CI already captures all the stdout/stderr output from the build
process as the log. However, some other important information is hidden
in other log files.

Taken from Wayland, capture logs from the configuration process as well
as from every check.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: Lucas De Marchi <lucas.de.marchi@gmail.com>
Cc: Eric Engeström <eric.engestrom@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
[Emil: use wildcard to match the artefacts]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-04 14:37:07 +01:00
Stefan Agner
8d44918a7d modeprint: print encoder type
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-04 14:26:48 +01:00
Stefan Agner
eaed5c8825 modeprint: use libutil to lookup strings
Use libutil to lookup connector type names and state. This also
makes sure that the latest connector type addition "DPI" gets
printed correctly.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-10-04 14:26:16 +01:00
Eric Engestrom
4ec31fc31a freedreno: add missing drm_public
Fixes: 9a1470fb41 "freedreno: annotate public functions"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-20 19:28:56 +01:00
Eric Engestrom
0785257462 omap: fix symbol annotations
Fixes: f3f7266d94 "omap: annotate public functions"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2018-09-20 19:28:09 +01:00
Eric Engestrom
ff8cb2402a radeon: add missing drm_public exports
Fixes: 9f45264815 "radeon: annotate public functions"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108006
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2018-09-20 19:28:05 +01:00
Eric Engestrom
4b737cde8f nouveau: add missing drm_public exports
Fixes: d7320bfcdd "nouveau: annotate public functions"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108006
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
2018-09-20 18:23:52 +01:00
Eric Engestrom
a2920ea6a8 intel: add missing drm_public exports
Fixes: 36bb0ea47b "intel: annotate public functions"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108006
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
2018-09-20 18:23:19 +01:00
Lucas De Marchi
1e3fcc495b autotools: make symbols hidden by default
Now that symbols that should be exported are annotated accordingly, make
all the rest hidden by default.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
ba808253bc meson: make symbols hidden by default
Now that symbols that should be exported are annotated accordingly, make
all the rest hidden by default.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
67967e9b5c exynos: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
exynos-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
d1db9dd200 tegra: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
tegra-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
9f45264815 radeon: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
radeon-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
f3f7266d94 omap: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
omap-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
9a1470fb41 freedreno: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
freedreno-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
3441a18c3a etnaviv: annotate public functions
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

In which /tmp/a.txt contains the public symbols from
etnaviv-symbol-check. The idea here will be to switch the default
visibility to hidden so we don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
26f9ce50e1 libdrm: annotate public functions
This was done with:
nm --dynamic --defined-only build/libdrm.so | \
	grep " T " | \
	grep -v _fini | grep -v _init | \
	cut -d' ' -f3 > /tmp/a.txt

while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

Then the alignment of function arguments were manually fixed all over.
The idea here will be to switch the default visibility to hidden so we
don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
e15e3a65b8 amdgpu: annotate public functions
This was done with:
nm --dynamic --defined-only build/amdgpu/libdrm_amdgpu.so | \
	grep amdgpu_ | \
	cut -d' ' -f3 > /tmp/a.txt

while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		line=$((line-1))
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

Then the alignment of function arguments were manually fixed all over.
The idea here will be to switch the default visibility to hidden so we
don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
d7320bfcdd nouveau: annotate public functions
This was done with:
nm --dynamic --defined-only build/nouveau/libdrm_nouveau.so | \
	grep nouveau_ | \
	cut -d ' ' -f3 > /tmp/a.txt

while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		line=$((line-1))
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

Then some corner cases were manually fixed. The idea here will be to
switch the default visibility to hidden so we don't export symbols we
shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
6229895cc5 libkms: annotate public functions
This was done with:
nm --dynamic --defined-only build/libkms/libkms.so | \
	grep kms_ | \
	cut -d' ' -f3 > /tmp/a.txt

while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

The idea here will be to switch the default visibility to hidden so we
don't export symbols we shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi
36bb0ea47b intel: annotate public functions
This was done with:
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		line=$((line-1))
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

Then some corner cases were manually fixed. "a.txt" above contains the
symbols collected from intel/intel-symbol-check. The idea here will be
to switch the default visibility to hidden so we don't export symbols we
shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:44 -07:00
Eric Engestrom
a9463bdb01 headers/README: fix/add link to drm-next
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-18 19:39:22 +01:00
Christian König
b46945e2dc test/amdgpu: add GDS, GWS and OA tests
Add allocation tests for GDW, GWS and OA.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-18 14:56:40 +02:00
Christian König
864d4501b9 test/amdgpu: add proper error handling v2
Otherwise the calling function won't notice that something is wrong.

v2: check map result as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-18 14:56:22 +02:00
Christian König
c40bd3cbf8 amdgpu: remove invalid check in amdgpu_bo_alloc
The heap is checked by the kernel and not libdrm, to make it even worse
it prevented allocating resources other than VRAM and GTT.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-18 14:53:30 +02:00
Rob Clark
28328298ca freedreno: move ring_cache behind fd_bo_del()
So that it isn't bypassing normal refcnt'ing.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-09-14 13:41:44 -04:00
Rob Clark
3b64b54e32 freedreno: fix spelling typo
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-09-14 13:41:44 -04:00
Christian König
5bd5f7b25e tests/amdgpu: add unaligned VM test
Make a VM mapping which is as unaligned as possible.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-09-14 14:13:03 +02:00
Emil Velikov
473e2d2e67 intel: annotate the intel genx helpers as private
They're used internally and never meant to be part of the API.
Add the drm_private notation, which should resolve that.

v2: (Rodrigo) Add missing include.
v3: (Rodrigo) Keep includes grouped per Eric suggestion.

Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 4e81d4f9c9 ("intel: add generic functions to check PCI ID")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-12 08:47:18 -07:00
Eric Engestrom
7f7c28dbd4 gitlab-ci: use templates to deduplicate the build commands
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-09-06 16:22:10 +01:00
Lucas De Marchi
c55f1b9b29 intel: get gen once for gen >= 9
We don't need to call IS_GEN() for each gen >= 9: we can rather use the
new intel_is_genx() helper to iterate the pciids array once.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:48 -07:00
Lucas De Marchi
584ca8fe53 intel: make gen9 use generic gen macro
The 2 PCI IDs that are used for the command line overrid mechanism
were left defined. The rest can be gone and then we just use the kernel
defines.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:41 -07:00
Lucas De Marchi
bf9df763d6 intel: make gen10 use generic gen macro
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:35 -07:00
Lucas De Marchi
8e7eb3bcfe intel: make gen11 use generic gen macro
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:27 -07:00
Lucas De Marchi
4e81d4f9c9 intel: add generic functions to check PCI ID
This will allow platforms to reuse kernel IDs instead of manually
keeping them in sync. In most of the cases we only need to extend
IS_9XX().  Current platforms that fit this requirement can be ported
over to use this macro. Right now it's a nop since it doesn't have any
PCI ID added.

The i915_pciids.h header is in sync with kernel tree on
drm-tip 2018y-08m-20d-21h-41m-11s.

v2: - move to a separate .c so we can have the array in a single
      compilation unit
    - use a single array for all gens
    - add real functions to get or check gen by pciid
    - define our own pci device struct rather than inherit the one
      kernel uses: we can throw away most of the fields

v3: - add comment to keep ids sorted by gen
    - remove misleading comment about all gens

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:04 -07:00
Eric Engestrom
9030a0f453 xf86drm: rename "real_path" to "pci_path"
"real_path" was getting confusing when there are other *paths in the
same functions.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-09-05 18:28:23 +01:00
Eric Engestrom
564995316e xf86drm: merge get_normal_pci_path() into get_real_pci_path()
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-09-05 18:28:14 +01:00
Tom Anderson
b06d71bb22 Fix build with -std=c11
typeof() is a GNU extension that will only work when the compiler is passed
-std=gnu*.  __typeof__() works with -std=c*, however.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-05 13:09:29 +01:00
Eric Engestrom
4a9030dc8b add gitlab-ci builds of libdrm
It currently does 4 builds: 2 using Meson and 2 using Autotools, 2 using
the latest dependencies on ArchLinux and 2 using very old dependencies
on Debian (including manually building libpciaccess to have the oldest
version supported, to make sure it keeps being supported).

All the build options are turned on for both Meson and Autotools.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2018-09-04 15:41:31 +01:00
Daniel Vetter
4d87c2e203 Add basic CONTRIBUTING file
I picked up a bunch of the pieces from wayland's version:

https://gitlab.freedesktop.org/wayland/wayland/blob/master/CONTRIBUTING.md

The weston one is fairly similar. Then I rather massively trimmed it
down since in reality libdrm is a bit a dumping ground with very few
real rules. The commit rights and CoC sections I've copied verbatim
from igt respectively drm-misc. Weston/Wayland only differ in their
pick of how many patches you need (10 instead of 5). I think for
libdrm this is supremely relevant, since most everyone will get their
commit rights by contributing already to the kernel or mesa and having
commit rights there already.

Anyway, I figured this is good to get the rules documented, even if
there's mostly not many rules.

Note: This references maintainers in a MAINTAINERS file, which needs
to be created first.

Note: With the gitlab migration the entire commit rights process is
still a bit up in the air. But gitlab commit rights and roles are
hierarchical, so we can do libdrm-only maintainer/commiter roles
("Owner" and "Developer" in gitlab-speak). This should avoid
conflating libdrm roles with mesa roles, useful for those pushing to
libdrm as primarily kernel contributors.

v2: Comments from Emil:
- Recommend subject prefix.
- Fix copypaste fumbles, this isn't igt/wayland ...

v3: Comments from Marek:
- libdrm moved to mesa, update the document. Atm the entire account
  request situation is entirely not clear for gitlab and mesa
  projects, so that's a bit up in the air. Also, should probably send
  an announcement to dri-devel@, which didn't happen.
- amd folks don't submit their patches to dri-devel, document that.
  Probably applies to other drivers too.

v4: Comments from Rob:
- Also include kernel/userspace in the commit counts criteria, due to
  libdrm's special role as a glue library.

v5: Summarize the irc discussion on gitlab roles in the commit message
a bit.

v6: Some grammer stuff from Eric E.

v7: Use --local in git config (Eric E.)

Cc: Dave Airlie <airlied@gmail.com>
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com> (v4)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v6)
Acked-by: Emil Velikov <emil.l.velikov@gmail.com> (v6)
Acked-by: Marek Olšák <marek.olsak@amd.com> (v5)
Acked-by: Dave Airlie <airlied@redhat.com>
References: https://gitlab.freedesktop.org/wayland/weston/blob/master/CONTRIBUTING.md
References: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html#commit-rights
References: https://cgit.freedesktop.org/drm/igt-gpu-tools/tree/CONTRIBUTING#n54
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2018-09-04 14:15:26 +02:00
Qiang Yu
580bd83fb4 amdgpu: amdgpu_bo_inc_ref don't return dummy int
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-09-03 12:37:32 +02:00
Qiang Yu
937d62ea69 amdgpu: add amdgpu_bo_inc_ref() function.
For Pro OGL be able to work with upstream libdrm.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-09-03 10:55:53 +02:00
Junwei Zhang
f177251088 amdgpu: add error return value for finding bo by cpu mapping (v2)
If nothing is found, error should be returned.

v2: udpate the error value different from parameter check

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-09-01 11:57:34 +02:00
Michel Dänzer
f3d90e8db4 amdgpu-symbol-check: Add amdgpu_find_bo_by_cpu_mapping
Fixes: 4d454424e1 ("amdgpu: add a function to find bo by cpu mapping
                      (v2)"
2018-08-27 11:50:55 +02:00
Emil Velikov
bcb9d976cd xf86drm: fallback to normal path when realpath fails
Earlier commit reworked our sysfs handling to use realpath.
Sadly that backfired since the Firefox sandboxing mechanism rejects
that. Despite the files/folders being in the allowed list, of the
sandboxing mechanism.

Oddly enough, the Chromium sandboxing doesn't complain about any of
this.

Since there are no Firefox releases with the fix, add a temporary
solution which falls back to the original handling.

Sadly, this won't work for virgl.

v2: drop return type - function cannot return NULL (Eric)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107516
Fixes: a02900133b ("xf86drm: introduce a get_real_pci_path() helper")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-24 13:37:33 +01:00
Kristian H. Kristensen
8389c54548 Bump to version 2.4.94 2018-08-23 14:38:37 -07:00
Tanmay Shah
f0c642e8df libdrm: add msm drm uapi header
msm_drm.h file Generated using make headers_install.

Generated from
tree - git://people.freedesktop.org/~airlied/linux
branch - drm-next
commit - 6d08b06e67cd117f6992c46611dfb4ce267cd71e

Remove freedreno/msm/msm_drm.h to maintain only
one copy of msm_drm.h and change freedreno Makefile
and meson.build file accordingly.

v2: Remove private freedreno/msm/msm_drm.h
v3: meson.build update
v3: README update (by anholt)

Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-08-23 08:48:45 -07:00
Junwei Zhang
f31fd57c60 amdgpu: add a function to create amdgpu bo internally (v4)
a helper function to create and initialize amdgpu bo

v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and rebase

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-08-17 12:55:11 +02:00
Junwei Zhang
3d8b6ea664 amdgpu: free flink bo in bo import
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-08-17 12:54:36 +02:00
Michel Dänzer
c6493f360e amdgpu: Eliminate void* arithmetic in amdgpu_find_bo_by_cpu_mapping
Arithmetic using void* pointers isn't defined by the C standard, only as
a GCC extension. Avoids compiler warnings:

../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:554:48: warning: pointer of type ‘void *’ used in arithmetic [-Wpointer-arith]
   if (cpu >= bo->cpu_ptr && cpu < (bo->cpu_ptr + bo->alloc_size))
                                                ^
../../amdgpu/amdgpu_bo.c:561:23: warning: pointer of type ‘void *’ used in subtraction [-Wpointer-arith]
   *offset_in_bo = cpu - bo->cpu_ptr;
                       ^

v2: Use uintptr_t instead of char*, don't change function signature
    (Junwei Zhang)

Fixes: 4d454424e1 ("amdgpu: add a function to find bo by cpu mapping
                     (v2)")
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-17 09:12:42 +02:00
Likun Gao
cc472c5bb3 amdgpu: Disable deadlock test suite for RV
disable deadlock test suite for RV

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-16 13:45:20 -05:00
Christian König
bc4c9f4422 amdgpu: fix off by one in handle_table_insert
Stupid me, max_key must always be larger than key.

Signed-off-by: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/107552
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-16 08:50:04 +02:00
Michel Dänzer
1e12c16d76 amdgpu: Use uint32_t i in amdgpu_find_bo_by_cpu_mapping
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:

../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of integer expressions of different signedness: ‘int’ and ‘uint32_t’ {aka ‘unsigned int’} [-Wsign-compare]
  for (i = 0; i < dev->bo_handles.max_key; i++) {
                ^
../../amdgpu/amdgpu_bo.c:558:8: warning: comparison of integer expressions of different signedness: ‘int’ and ‘uint32_t’ {aka ‘unsigned int’} [-Wsign-compare]
  if (i < dev->bo_handles.max_key) {
        ^

Fixes: 4d454424e1 ("amdgpu: add a function to find bo by cpu mapping
                     (v2)")
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-15 10:34:59 +02:00
Rodrigo Vivi
6e30031788 intel: Add a new CFL PCI ID.
One more CFL ID added to spec.

Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")

v2: fix commit subject.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2018-08-14 16:06:54 -07:00
Rob Clark
879d7c0298 freedreno: fix use-after-free with stateobj rb's
We could be dropping last reference in ->flush(), so clear the entry in
the parent rb's table to avoid deref'ing after free'd.

Also, ring_bo_del()'s use of ring_cache expects that it is dropping the
last reference.  So drop our ref to the stateobj's ring_bo first.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-08-08 14:31:17 -04:00
Rob Clark
a43940eb91 freedreno: don't leak stateobj rb refs
One stateobj can be emitted multiple times in a single cmdstream, but
only the first time is a cmd entry added to the parent.  Since it will
be only unref'd once after flush, we should only ref it the first time
it is emitted (ie. the time it is added to cmd table).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2018-08-08 14:31:17 -04:00
Junwei Zhang
f4f61e5ec8 tests/amdgpu: add test for finding bo by CPU mapping
Add a test for API to query bo by CPU mapping

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-08-08 12:37:49 +02:00
Junwei Zhang
4d454424e1 amdgpu: add a function to find bo by cpu mapping (v2)
Userspace needs to know if the user memory is from BO or malloc.

v2: update mutex range and rebase

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-08-08 12:37:49 +02:00
Junwei Zhang
f49dccbb24 amdgpu: add bo from user memory to handle table
When create bo from user memory, add it to handle table
for future query.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2018-08-08 12:37:49 +02:00
Benjamin Gaignard
f693c468c1 tests/util: Add support for stm module
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-07 15:40:35 +01:00
Mike Lothian
649d4e60fa libdrm: Fix amdgpu build failure
Use the correct files to build libdrm_amdgpu.

Signed-of-by: Mike Lothian <mike@fireburn.co.uk>
Fixes: d6cb0ee408 ("amdgpu: remove the hash table implementation")
Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-07 13:58:21 +01:00
Benjamin Gaignard
93220283cb tests/modetest: Add atomic support
If "-a" option is set this make modetest use atomic API instead
of legacy API.

Test the frame rate ("-v") it does a loop and swap between two
framebuffer for each active planes.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-07 13:39:20 +01:00
Christian König
cbf0bb7f19 amdgpu: always add all BOs to handle table
This way we can always find a BO structure by its handle.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:27:39 +02:00
Christian König
d6cb0ee408 amdgpu: remove the hash table implementation
Not used any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:27:33 +02:00
Christian König
9a38e850a5 amdgpu: use handle table for flink names
Instead of the hash use the handle table.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:27:28 +02:00
Christian König
bde850bc32 amdgpu: use handle table for KMS handles
Instead of the hash use the handle table.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:27:22 +02:00
Christian König
52370cc6eb amdgpu: add handle table implementation v2
The kernel handles are dense and the kernel always tries to use the
lowest free id. Use this to implement a more efficient handle table
by using a resizeable array instead of a hash.

v2: add handle_table_fini function, extra key checks,
    fix typo in function name

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:27:16 +02:00
Christian König
7aa1a51133 amdgpu: stop using the hash table for fd_tab
We have so few devices that just walking a linked list is probably
faster.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-and-Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
2018-08-07 13:26:59 +02:00
317 changed files with 24581 additions and 21651 deletions

109
.gitignore vendored
View file

@ -1,108 +1 @@
bsd-core/*/@
bsd-core/*/machine
*~
*.1
*.3
*.5
*.7
*.flags
*.ko
*.ko.cmd
*.la
*.lo
*.log
*.mod.c
*.mod.o
*.o
*.o.cmd
*.sw?
*.trs
.depend
.deps
.libs
.tmp_versions
.*check*
.*install*
Makefile
Makefile.in
TAGS
aclocal.m4
autom4te.cache
build-aux
bus_if.h
compile
config.guess
config.h
config.h.in
config.log
config.status
config.sub
configure
configure.lineno
cscope.*
depcomp
device_if.h
drm.kld
drm_pciids.h
export_syms
i915.kld
install-sh
libdrm/config.h.in
libdrm.pc
libdrm_intel.pc
libdrm_nouveau.pc
libdrm_radeon.pc
libdrm_omap.pc
libdrm_exynos.pc
libdrm_freedreno.pc
libdrm_amdgpu.pc
libdrm_vc4.pc
libdrm_etnaviv.pc
libkms.pc
libtool
ltmain.sh
mach64.kld
man/.man_fixup
mga.kld
missing
mkinstalldirs
opt_drm.h
pci_if.h
r128.kld
radeon.kld
savage.kld
sis.kld
stamp-h1
tdfx.kld
via.kld
tests/auth
tests/amdgpu/amdgpu_test
tests/dristat
tests/drmdevice
tests/drmsl
tests/drmstat
tests/getclient
tests/getstats
tests/getversion
tests/hash
tests/lock
tests/openclose
tests/random
tests/setversion
tests/updatedraw
tests/modeprint/modeprint
tests/modetest/modetest
tests/name_from_fd
tests/proptest/proptest
tests/kms/kms-steal-crtc
tests/kms/kms-universal-planes
tests/kmstest/kmstest
tests/vbltest/vbltest
tests/radeon/radeon_ttm
tests/exynos/exynos_fimg2d_event
tests/exynos/exynos_fimg2d_perf
tests/exynos/exynos_fimg2d_test
tests/etnaviv/etnaviv_2d_test
tests/etnaviv/etnaviv_cmd_stream_test
tests/etnaviv/etnaviv_bo_cache_test
man/*.3
/build*

265
.gitlab-ci.yml Normal file
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@ -0,0 +1,265 @@
# This is the tag of the docker image used for the build jobs. If the
# image doesn't exist yet, the containers stage generates it.
#
# In order to generate a new image, one should generally change the tag.
# While removing the image from the registry would also work, that's not
# recommended except for ephemeral images during development: Replacing
# an image after a significant amount of time might pull in newer
# versions of gcc/clang or other packages, which might break the build
# with older commits using the same tag.
#
# After merging a change resulting in generating a new image to the
# main repository, it's recommended to remove the image from the source
# repository's container registry, so that the image from the main
# repository's registry will be used there as well.
.templates_sha: &template_sha c6aeb16f86e32525fa630fb99c66c4f3e62fc3cb # see https://docs.gitlab.com/ee/ci/yaml/#includefile
include:
- project: 'freedesktop/ci-templates'
ref: *template_sha
file:
- '/templates/debian.yml'
- '/templates/freebsd.yml'
- '/templates/ci-fairy.yml'
variables:
FDO_UPSTREAM_REPO: mesa/libdrm
FDO_REPO_SUFFIX: "$BUILD_OS/$BUILD_ARCH"
stages:
- "Base container"
- "Build"
.ci-rules:
rules:
- when: on_success
# CONTAINERS
.os-debian:
variables:
BUILD_OS: debian
FDO_DISTRIBUTION_VERSION: bookworm
FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
# bump this tag every time you change something which requires rebuilding the
# base image
FDO_DISTRIBUTION_TAG: "2024-06-25.0"
.debian-x86_64:
extends:
- .os-debian
variables:
BUILD_ARCH: "x86-64"
.debian-aarch64:
extends:
- .os-debian
variables:
BUILD_ARCH: "aarch64"
.debian-armv7:
extends:
- .os-debian
variables:
BUILD_ARCH: "armv7"
FDO_DISTRIBUTION_PLATFORM: linux/arm/v7
.os-freebsd:
variables:
BUILD_OS: freebsd
FDO_DISTRIBUTION_VERSION: "14.2"
FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess textproc/py-docutils cairo'
# bump this tag every time you change something which requires rebuilding the
# base image
FDO_DISTRIBUTION_TAG: "2025-05-22.0"
.freebsd-x86_64:
extends:
- .os-freebsd
variables:
BUILD_ARCH: "x86_64"
# Build our base container image, which contains the core distribution, the
# toolchain, and all our build dependencies. This will be reused in the build
# stage.
x86_64-debian-container_prep:
extends:
- .ci-rules
- .debian-x86_64
- .fdo.container-build@debian
stage: "Base container"
variables:
GIT_STRATEGY: none
aarch64-debian-container_prep:
extends:
- .ci-rules
- .debian-aarch64
- .fdo.container-build@debian
tags:
- aarch64
stage: "Base container"
variables:
GIT_STRATEGY: none
armv7-debian-container_prep:
extends:
- .ci-rules
- .debian-armv7
- .fdo.container-build@debian
tags:
- aarch64
stage: "Base container"
variables:
GIT_STRATEGY: none
FDO_BASE_IMAGE: "arm32v7/debian:$FDO_DISTRIBUTION_VERSION"
x86_64-freebsd-container_prep:
extends:
- .ci-rules
- .freebsd-x86_64
- .fdo.qemu-build@freebsd@x86_64
stage: "Base container"
variables:
GIT_STRATEGY: none
# Core build environment.
.build-env:
variables:
MESON_BUILD_TYPE: "-Dbuildtype=debug -Doptimization=0 -Db_sanitize=address,undefined"
# OS/architecture-specific variants
.build-env-debian-x86_64:
extends:
- .fdo.suffixed-image@debian
- .debian-x86_64
- .build-env
needs:
- job: x86_64-debian-container_prep
artifacts: false
.build-env-debian-aarch64:
extends:
- .fdo.suffixed-image@debian
- .debian-aarch64
- .build-env
variables:
# At least with the versions we have, the LSan runtime makes fork unusably
# slow on AArch64, which is bad news since the test suite decides to fork
# for every single subtest. For now, in order to get AArch64 builds and
# tests into CI, just assume that we're not going to leak any more on
# AArch64 than we would on ARMv7 or x86-64.
ASAN_OPTIONS: "detect_leaks=0"
tags:
- aarch64
needs:
- job: aarch64-debian-container_prep
artifacts: false
.build-env-debian-armv7:
extends:
- .fdo.suffixed-image@debian
- .debian-armv7
- .build-env
tags:
- aarch64
needs:
- job: armv7-debian-container_prep
artifacts: false
.build-env-freebsd-x86_64:
variables:
# Compiling with ASan+UBSan appears to trigger an infinite loop in the
# compiler shipped with FreeBSD 13.0, so we only use UBSan here.
# Additionally, sanitizers can't be used with b_lundef on FreeBSD.
MESON_BUILD_TYPE: "-Dbuildtype=debug -Db_sanitize=undefined -Db_lundef=false"
extends:
- .fdo.suffixed-image@freebsd
- .freebsd-x86_64
- .build-env
needs:
- job: x86_64-freebsd-container_prep
artifacts: false
# BUILD
.do-build:
extends:
- .ci-rules
stage: "Build"
variables:
GIT_DEPTH: 10
script:
- meson setup build
--fatal-meson-warnings --auto-features=enabled
-D udev=true
- ninja -C build
- ninja -C build test
- DESTDIR=$PWD/install ninja -C build install
artifacts:
when: on_failure
paths:
- build/meson-logs/*
.do-build-qemu:
extends:
- .ci-rules
stage: "Build"
script:
# Start the VM and copy our workspace to the VM
- /app/vmctl start
- scp -r $PWD "vm:"
# The `set +e is needed to ensure that we always copy the meson logs back to
# the workspace to see details about the failed tests.
- |
set +e
/app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson setup build --fatal-meson-warnings --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
set -ex
scp -r vm:$CI_PROJECT_NAME/build/meson-logs .
/app/vmctl exec "ninja -C $CI_PROJECT_NAME/build install"
mkdir -p $PREFIX && scp -r vm:$PREFIX/ $PREFIX/
# Finally, shut down the VM.
- /app/vmctl stop
artifacts:
when: on_failure
paths:
- build/meson-logs/*
# Full build and test.
x86_64-debian-build:
extends:
- .build-env-debian-x86_64
- .do-build
aarch64-debian-build:
extends:
- .build-env-debian-aarch64
- .do-build
armv7-debian-build:
extends:
- .build-env-debian-armv7
- .do-build
# Daily build
meson-arch-daily:
rules:
- if: '$SCHEDULE == "arch-daily"'
when: on_success
- when: never
image: archlinux/archlinux:base-devel
before_script:
- pacman -Syu --noconfirm --needed
cairo
cunit
libatomic_ops
libpciaccess
meson
valgrind
python-docutils
extends: .do-build
x86_64-freebsd-build:
extends:
- .build-env-freebsd-x86_64
- .do-build-qemu

97
Android.bp Normal file
View file

@ -0,0 +1,97 @@
//
// Copyright © 2011-2012 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice (including the next
// paragraph) shall be included in all copies or substantial portions of the
// Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
// IN THE SOFTWARE.
//
subdirs = ["*"]
build = ["Android.sources.bp"]
cc_defaults {
name: "libdrm_defaults",
cflags: [
// XXX: Consider moving these to config.h analogous to autoconf.
"-DMAJOR_IN_SYSMACROS=1",
"-DHAVE_VISIBILITY=1",
"-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1",
"-Wall",
"-Werror",
"-Wno-deprecated-declarations",
"-Wno-format",
"-Wno-gnu-variable-sized-type-not-at-end",
"-Wno-implicit-function-declaration",
"-Wno-int-conversion",
"-Wno-missing-field-initializers",
"-Wno-pointer-arith",
"-Wno-unused-parameter",
"-Wno-unused-variable",
],
export_system_include_dirs: ["."],
}
cc_library_headers {
name: "libdrm_headers",
vendor_available: true,
host_supported: true,
defaults: ["libdrm_defaults"],
export_include_dirs: ["include/drm", "android"],
apex_available: [
"//apex_available:platform",
"com.android.virt",
],
}
genrule {
name: "generated_static_table_fourcc_h",
out: ["generated_static_table_fourcc.h"],
srcs: ["include/drm/drm_fourcc.h"],
tool_files: ["gen_table_fourcc.py"],
cmd: "python3 $(location gen_table_fourcc.py) $(in) $(out)",
}
// Library for the device
cc_library {
name: "libdrm",
recovery_available: true,
vendor_available: true,
host_supported: true,
defaults: [
"libdrm_defaults",
"libdrm_sources",
],
generated_headers: [
"generated_static_table_fourcc_h",
],
export_include_dirs: ["include/drm", "android"],
cflags: [
"-Wno-enum-conversion",
"-Wno-pointer-arith",
"-Wno-sign-compare",
"-Wno-tautological-compare",
],
apex_available: [
"//apex_available:platform",
"com.android.virt",
],
}

View file

@ -1,18 +0,0 @@
# XXX: Consider moving these to config.h analogous to autoconf.
LOCAL_CFLAGS += \
-DMAJOR_IN_SYSMACROS=1 \
-DHAVE_VISIBILITY=1 \
-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1
LOCAL_CFLAGS += \
-Wno-error \
-Wno-unused-parameter \
-Wno-missing-field-initializers \
-Wno-pointer-arith \
-Wno-enum-conversion
# Quiet down the build system and remove any .h files from the sources
LOCAL_SRC_FILES := $(patsubst %.h, , $(LOCAL_SRC_FILES))
LOCAL_EXPORT_C_INCLUDE_DIRS += $(LOCAL_PATH)
LOCAL_PROPRIETARY_MODULE := true

View file

@ -1,69 +0,0 @@
#
# Copyright © 2011-2012 Intel Corporation
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
# IN THE SOFTWARE.
#
LIBDRM_COMMON_MK := $(call my-dir)/Android.common.mk
LOCAL_PATH := $(call my-dir)
LIBDRM_TOP := $(LOCAL_PATH)
include $(CLEAR_VARS)
# Import variables LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES
include $(LOCAL_PATH)/Makefile.sources
#static library for the device (recovery)
include $(CLEAR_VARS)
LOCAL_MODULE := libdrm
LOCAL_SRC_FILES := $(LIBDRM_FILES)
LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \
$(LOCAL_PATH)/include/drm \
$(LOCAL_PATH)/android
LOCAL_C_INCLUDES := \
$(LOCAL_PATH)/include/drm
include $(LIBDRM_COMMON_MK)
include $(BUILD_STATIC_LIBRARY)
# Shared library for the device
include $(CLEAR_VARS)
LOCAL_MODULE := libdrm
LOCAL_SRC_FILES := $(LIBDRM_FILES)
LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \
$(LOCAL_PATH)/include/drm \
$(LOCAL_PATH)/android
LOCAL_SHARED_LIBRARIES := \
libcutils
LOCAL_C_INCLUDES := \
$(LOCAL_PATH)/include/drm
include $(LIBDRM_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)
include $(call all-makefiles-under,$(LOCAL_PATH))

12
Android.sources.bp Normal file
View file

@ -0,0 +1,12 @@
// Autogenerated with Android.sources.bp.mk
cc_defaults {
name: "libdrm_sources",
srcs: [
"xf86drm.c",
"xf86drmHash.c",
"xf86drmRandom.c",
"xf86drmSL.c",
"xf86drmMode.c",
],
}

25
Android.sources.bp.mk Normal file
View file

@ -0,0 +1,25 @@
# Usage: make -f path/to/Android.sources.bp.mk NAMES=<> >Android.sources.bp
#
# It will read the Makefile.sources in the current directory, and
# write <NAME>_FILES to stdout as an Android.bp cc_defaults module.
.PHONY: all
all:
@# Do nothing
include Makefile.sources
empty :=
indent := $(empty) $(empty)
$(info // Autogenerated with Android.sources.bp.mk)
$(foreach NAME,$(NAMES), \
$(eval lower_name := $(shell echo $(PREFIX)$(NAME) | tr 'A-Z' 'a-z')) \
$(info ) \
$(info cc_defaults {) \
$(info $(indent)name: "$(lower_name)_sources",) \
$(info $(indent)srcs: [) \
$(foreach f,$(filter %.c,$($(NAME)_FILES)), \
$(info $(indent)$(indent)"$(f)",)) \
$(info $(indent)],) \
$(info }))

105
CONTRIBUTING.rst Normal file
View file

@ -0,0 +1,105 @@
Contributing to libdrm
======================
Submitting Patches
------------------
Patches should be sent to dri-devel@lists.freedesktop.org, using git
send-email. For patches only touching driver specific code one of the driver
mailing lists (like amd-gfx@lists.freedesktop.org) is also appropriate. See git
documentation for help:
http://git-scm.com/documentation
Since dri-devel is a very busy mailing list please use --subject-prefix="PATCH
libdrm" to make it easier to find libdrm patches. This is best done by running
git config --local format.subjectprefix "PATCH libdrm"
The first line of a commit message should contain a prefix indicating what part
is affected by the patch followed by one sentence that describes the change. For
examples:
amdgpu: Use uint32_t i in amdgpu_find_bo_by_cpu_mapping
The body of the commit message should describe what the patch changes and why,
and also note any particular side effects. For a recommended reading on
writing commit messages, see:
http://who-t.blogspot.de/2009/12/on-commit-messages.html
Your patches should also include a Signed-off-by line with your name and email
address. If you're not the patch's original author, you should also gather
S-o-b's by them (and/or whomever gave the patch to you.) The significance of
this is that it certifies that you created the patch, that it was created under
an appropriate open source license, or provided to you under those terms. This
lets us indicate a chain of responsibility for the copyright status of the code.
For more details:
https://developercertificate.org/
We won't reject patches that lack S-o-b, but it is strongly recommended.
Review and Merging
------------------
Patches should have at least one positive review (Reviewed-by: tag) or
indication of approval (Acked-by: tag) before merging. For any code shared
between drivers this is mandatory.
Please note that kernel/userspace API header files have special rules, see
include/drm/README.
Coding style in the project loosely follows the CodingStyle of the linux kernel:
https://www.kernel.org/doc/html/latest/process/coding-style.html?highlight=coding%20style
Commit Rights
-------------
Commit rights will be granted to anyone who requests them and fulfills the
below criteria:
- Submitted a few (5-10 as a rule of thumb) non-trivial (not just simple
spelling fixes and whitespace adjustment) patches that have been merged
already. Since libdrm is just a glue library between the kernel and userspace
drivers, merged patches to those components also count towards the commit
criteria.
- Are actively participating on discussions about their work (on the mailing
list or IRC). This should not be interpreted as a requirement to review other
peoples patches but just make sure that patch submission isn't one-way
communication. Cross-review is still highly encouraged.
- Will be regularly contributing further patches. This includes regular
contributors to other parts of the open source graphics stack who only
do the oddball rare patch within libdrm itself.
- Agrees to use their commit rights in accordance with the documented merge
criteria, tools, and processes.
To apply for commit rights ("Developer" role in gitlab) send a mail to
dri-devel@lists.freedesktop.org and please ping the maintainers if your request
is stuck.
Committers are encouraged to request their commit rights get removed when they
no longer contribute to the project. Commit rights will be reinstated when they
come back to the project.
Maintainers and committers should encourage contributors to request commit
rights, as especially junior contributors tend to underestimate their skills.
Code of Conduct
---------------
Please be aware the fd.o Code of Conduct also applies to libdrm:
https://www.freedesktop.org/wiki/CodeOfConduct/
See the gitlab project owners for contact details of the libdrm maintainers.
Abuse of commit rights, like engaging in commit fights or willfully pushing
patches that violate the documented merge criteria, will also be handled through
the Code of Conduct enforcement process.
Happy hacking!

View file

@ -1,175 +0,0 @@
# Copyright 2005 Adam Jackson.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# on the rights to use, copy, modify, merge, publish, distribute, sub
# license, and/or sell copies of the Software, and to permit persons to whom
# the Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
include Makefile.sources
ACLOCAL_AMFLAGS = -I m4 ${ACLOCAL_FLAGS}
AM_MAKEFLAGS = -s
AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-udev \
--enable-libkms \
--enable-intel \
--enable-radeon \
--enable-amdgpu \
--enable-nouveau \
--enable-vc4 \
--enable-vmwgfx \
--enable-omap-experimental-api \
--enable-exynos-experimental-api \
--enable-freedreno \
--enable-freedreno-kgsl\
--enable-tegra-experimental-api \
--enable-etnaviv-experimental-api \
--enable-install-test-programs \
--enable-cairo-tests \
--enable-manpages \
--enable-valgrind
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm.pc
if HAVE_LIBKMS
LIBKMS_SUBDIR = libkms
endif
if HAVE_INTEL
INTEL_SUBDIR = intel
endif
if HAVE_NOUVEAU
NOUVEAU_SUBDIR = nouveau
endif
if HAVE_RADEON
RADEON_SUBDIR = radeon
endif
if HAVE_AMDGPU
AMDGPU_SUBDIR = amdgpu
endif
if HAVE_OMAP
OMAP_SUBDIR = omap
endif
if HAVE_EXYNOS
EXYNOS_SUBDIR = exynos
endif
if HAVE_FREEDRENO
FREEDRENO_SUBDIR = freedreno
endif
if HAVE_TEGRA
TEGRA_SUBDIR = tegra
endif
if HAVE_VC4
VC4_SUBDIR = vc4
endif
if HAVE_ETNAVIV
ETNAVIV_SUBDIR = etnaviv
endif
if BUILD_MANPAGES
if HAVE_MANPAGES_STYLESHEET
MAN_SUBDIR = man
endif
endif
SUBDIRS = \
. \
$(LIBKMS_SUBDIR) \
$(INTEL_SUBDIR) \
$(NOUVEAU_SUBDIR) \
$(RADEON_SUBDIR) \
$(AMDGPU_SUBDIR) \
$(OMAP_SUBDIR) \
$(EXYNOS_SUBDIR) \
$(FREEDRENO_SUBDIR) \
$(TEGRA_SUBDIR) \
$(VC4_SUBDIR) \
$(ETNAVIV_SUBDIR) \
data \
tests \
$(MAN_SUBDIR)
libdrm_la_LTLIBRARIES = libdrm.la
libdrm_ladir = $(libdir)
libdrm_la_LDFLAGS = -version-number 2:4:0 -no-undefined
libdrm_la_LIBADD = @CLOCK_LIB@ -lm
libdrm_la_CPPFLAGS = -I$(top_srcdir)/include/drm
AM_CFLAGS = \
$(WARN_CFLAGS) \
$(VALGRIND_CFLAGS)
libdrm_la_SOURCES = $(LIBDRM_FILES)
libdrmincludedir = ${includedir}
libdrminclude_HEADERS = $(LIBDRM_H_FILES)
klibdrmincludedir = ${includedir}/libdrm
klibdrminclude_HEADERS = $(LIBDRM_INCLUDE_H_FILES)
if HAVE_VMWGFX
klibdrminclude_HEADERS += $(LIBDRM_INCLUDE_VMWGFX_H_FILES)
endif
EXTRA_DIST = \
include/drm/README \
amdgpu/meson.build \
data/meson.build \
etnaviv/meson.build \
exynos/meson.build \
freedreno/meson.build \
intel/meson.build \
libkms/meson.build \
man/meson.build \
nouveau/meson.build \
omap/meson.build \
radeon/meson.build \
tegra/meson.build \
tests/amdgpu/meson.build \
tests/etnaviv/meson.build \
tests/exynos/meson.build \
tests/kms/meson.build \
tests/kmstest/meson.build \
tests/meson.build \
tests/modeprint/meson.build \
tests/modetest/meson.build \
tests/nouveau/meson.build \
tests/proptest/meson.build \
tests/radeon/meson.build \
tests/tegra/meson.build \
tests/util/meson.build \
tests/vbltest/meson.build \
vc4/meson.build \
meson.build \
meson_options.txt
copy-headers :
cp -r $(kernel_source)/include/uapi/drm/*.h $(top_srcdir)/include/drm/
commit-headers : copy-headers
git add include/drm/*.h
git commit -am "Copy headers from kernel $$(GIT_DIR=$(kernel_source)/.git git describe)"

View file

@ -1,44 +0,0 @@
LIBDRM_FILES := \
xf86drm.c \
xf86drmHash.c \
xf86drmHash.h \
xf86drmRandom.c \
xf86drmRandom.h \
xf86drmSL.c \
xf86drmMode.c \
xf86atomic.h \
libdrm_macros.h \
libdrm_lists.h \
util_double_list.h \
util_math.h
LIBDRM_H_FILES := \
libsync.h \
xf86drm.h \
xf86drmMode.h
LIBDRM_INCLUDE_H_FILES := \
include/drm/drm.h \
include/drm/drm_fourcc.h \
include/drm/drm_mode.h \
include/drm/drm_sarea.h \
include/drm/i915_drm.h \
include/drm/mach64_drm.h \
include/drm/mga_drm.h \
include/drm/nouveau_drm.h \
include/drm/qxl_drm.h \
include/drm/r128_drm.h \
include/drm/radeon_drm.h \
include/drm/amdgpu_drm.h \
include/drm/savage_drm.h \
include/drm/sis_drm.h \
include/drm/tegra_drm.h \
include/drm/vc4_drm.h \
include/drm/via_drm.h \
include/drm/virtgpu_drm.h
LIBDRM_INCLUDE_ANDROID_H_FILES := \
android/gralloc_handle.h
LIBDRM_INCLUDE_VMWGFX_H_FILES := \
include/drm/vmwgfx_drm.h

59
README
View file

@ -1,59 +0,0 @@
libdrm - userspace library for drm
This is libdrm, a userspace library for accessing the DRM, direct
rendering manager, on Linux, BSD and other operating systems that
support the ioctl interface. The library provides wrapper functions
for the ioctls to avoid exposing the kernel interface directly, and
for chipsets with drm memory manager, support for tracking relocations
and buffers. libdrm is a low-level library, typically used by
graphics drivers such as the Mesa DRI drivers, the X drivers, libva
and similar projects. New functionality in the kernel DRM drivers
typically requires a new libdrm, but a new libdrm will always work
with an older kernel.
Compiling
---------
libdrm has two build systems, a legacy autotools build system, and a newer
meson build system. The meson build system is much faster, and offers a
slightly different interface, but otherwise provides an equivalent feature set.
To use it:
meson builddir/
By default this will install into /usr/local, you can change your prefix
with --prefix=/usr (or `meson configure builddir/ -Dprefix=/usr` after
the initial meson setup).
Then use ninja to build and install:
ninja -C builddir/ install
If you are installing into a system location you will need to run install
separately, and as root.
Alternatively you can invoke autotools configure:
./configure
By default, libdrm will install into the /usr/local/ prefix. If you
want to install this DRM to replace your system copy, pass
--prefix=/usr and --exec-prefix=/ to configure. If you are building
libdrm from a git checkout, you first need to run the autogen.sh
script. You can pass any options to autogen.sh that you would other
wise pass to configure, or you can just re-run configure with the
options you need once autogen.sh finishes.
Next step is to build libdrm:
make
and once make finishes successfully, install the package using
make install
If you are installing into a system location, you will need to be root
to perform the install step.

63
README.rst Normal file
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@ -0,0 +1,63 @@
libdrm - userspace library for drm
----------------------------------
This is libdrm, a userspace library for accessing the DRM, direct rendering
manager, on Linux, BSD and other operating systems that support the ioctl
interface.
The library provides wrapper functions for the ioctls to avoid exposing the
kernel interface directly, and for chipsets with drm memory manager, support
for tracking relocations and buffers.
New functionality in the kernel DRM drivers typically requires a new libdrm,
but a new libdrm will always work with an older kernel.
libdrm is a low-level library, typically used by graphics drivers such as
the Mesa drivers, the X drivers, libva and similar projects.
Syncing with the Linux kernel headers
-------------------------------------
The library should be regularly updated to match the recent changes in the
`include/uapi/drm/`.
libdrm maintains a human-readable version for the token format modifier, with
the simpler ones being extracted automatically from `drm_fourcc.h` header file
with the help of a python script. This might not always possible, as some of
the vendors require decoding/extracting them programmatically. For that
reason one can enhance the current vendor functions to include/provide the
newly added token formats, or, in case there's no such decoding
function, to add one that performs the tasks of extracting them.
For simpler format modifier tokens there's a script (gen_table_fourcc.py) that
creates a static table, by going over `drm_fourcc.h` header file. The script
could be further modified if it can't handle new (simpler) token format
modifiers instead of the generated static table.
Compiling
---------
To set up meson:
meson builddir/
By default this will install into /usr/local, you can change your prefix
with --prefix=/usr (or `meson configure builddir/ -Dprefix=/usr` after
the initial meson setup).
Then use ninja to build and install:
ninja -C builddir/ install
If you are installing into a system location you will need to run install
separately, and as root.
AMDGPU ASIC table file
----------------------
The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at
`$PREFIX/share/libdrm`, but it is possible to specify a set of alternative
paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment
variable with one or more colon-separated paths where to search for the
`amdgpu.ids` file.
For this option to be available, the C library must support secure_getenv()
function. In systems without it (like NetBSD), this option won't be available.

View file

@ -9,33 +9,22 @@ However, this is up to whoever is driving the feature in question.
Follow these steps to release a new version of libdrm:
1) Bump the version number in configure.ac and meson.build. We seem
to have settled for 2.4.x as the versioning scheme for libdrm, so
just bump the micro version.
1) Bump the version number in meson.build. We seem to have settled for
2.4.x as the versioning scheme for libdrm, so just bump the micro
version.
2) Run autoconf and then re-run ./configure so the build system
picks up the new version number.
2) Run `ninja -C builddir/ dist` to generate the tarballs.
Make sure that the version number of the tarball name in
builddir/meson-dist/ matches the number you bumped to. Move that
tarball to the libdrm repo root for the release script to pick up.
3) Verify that the code passes "make distcheck". Running "make
distcheck" should result in no warnings or errors and end with a
message of the form:
3) Push the updated main branch with the bumped version number:
=============================================
libdrm-X.Y.Z archives ready for distribution:
libdrm-X.Y.Z.tar.gz
libdrm-X.Y.Z.tar.bz2
=============================================
Make sure that the version number reported by distcheck and in
the tarball names matches the number you bumped to in configure.ac.
4) Push the updated master branch with the bumped version number:
git push origin master
git push origin main
assuming the remote for the upstream libdrm repo is called origin.
5) Use the release.sh script from the xorg/util/modular repo to
4) Use the release.sh script from the xorg/util/modular repo to
upload the tarballs to the freedesktop.org download area and
create an announce email template. The script takes one argument:
the path to the libdrm checkout. So, if a checkout of modular is

16
amdgpu/Android.bp Normal file
View file

@ -0,0 +1,16 @@
build = ["Android.sources.bp"]
cc_library_shared {
name: "libdrm_amdgpu",
cflags: [
"-DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\""
],
defaults: [
"libdrm_defaults",
"libdrm_amdgpu_sources",
],
vendor: true,
shared_libs: ["libdrm"],
}

View file

@ -1,19 +0,0 @@
LOCAL_PATH := $(call my-dir)
include $(CLEAR_VARS)
# Import variables LIBDRM_AMDGPU_FILES, LIBDRM_AMDGPU_H_FILES
include $(LOCAL_PATH)/Makefile.sources
LOCAL_MODULE := libdrm_amdgpu
LOCAL_SHARED_LIBRARIES := libdrm
LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES)
LOCAL_CFLAGS := \
-DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\"
LOCAL_REQUIRED_MODULES := amdgpu.ids
include $(LIBDRM_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)

15
amdgpu/Android.sources.bp Normal file
View file

@ -0,0 +1,15 @@
// Autogenerated with Android.sources.bp.mk
cc_defaults {
name: "libdrm_amdgpu_sources",
srcs: [
"amdgpu_asic_id.c",
"amdgpu_bo.c",
"amdgpu_cs.c",
"amdgpu_device.c",
"amdgpu_gpu_info.c",
"amdgpu_vamgr.c",
"amdgpu_vm.c",
"handle_table.c",
],
}

View file

@ -1,51 +0,0 @@
# Copyright © 2008 Jérôme Glisse
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
# IN THE SOFTWARE.
#
# Authors:
# Jérôme Glisse <glisse@freedesktop.org>
include Makefile.sources
AM_CFLAGS = \
$(WARN_CFLAGS) \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
libdrmdatadir = @libdrmdatadir@
AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\"
libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
libdrm_amdgpu_ladir = $(libdir)
libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined
libdrm_amdgpu_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
libdrm_amdgpu_la_SOURCES = $(LIBDRM_AMDGPU_FILES)
amdgpu_asic_id.lo: $(top_srcdir)/data/amdgpu.ids
libdrm_amdgpuincludedir = ${includedir}/libdrm
libdrm_amdgpuinclude_HEADERS = $(LIBDRM_AMDGPU_H_FILES)
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_amdgpu.pc
TESTS = amdgpu-symbol-check
EXTRA_DIST = $(TESTS)

View file

@ -1,16 +0,0 @@
LIBDRM_AMDGPU_FILES := \
amdgpu_asic_id.c \
amdgpu_bo.c \
amdgpu_cs.c \
amdgpu_device.c \
amdgpu_gpu_info.c \
amdgpu_internal.h \
amdgpu_vamgr.c \
amdgpu_vm.c \
util_hash.c \
util_hash.h \
util_hash_table.c \
util_hash_table.h
LIBDRM_AMDGPU_H_FILES := \
amdgpu.h

View file

@ -1,21 +1,12 @@
#!/bin/bash
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.am/libdrm_amdgpuinclude_HEADERS
FUNCS=$($NM -D --format=bsd --defined-only ${1-.libs/libdrm_amdgpu.so} | awk '{print $3}' | while read func; do
( grep -q "^$func$" || echo $func ) <<EOF
__bss_start
_edata
_end
_fini
_init
amdgpu_bo_alloc
amdgpu_bo_cpu_map
amdgpu_bo_cpu_unmap
amdgpu_bo_export
amdgpu_bo_free
amdgpu_bo_import
amdgpu_bo_inc_ref
amdgpu_bo_list_create_raw
amdgpu_bo_list_destroy_raw
amdgpu_bo_list_create
amdgpu_bo_list_destroy
amdgpu_bo_list_update
@ -23,6 +14,7 @@ amdgpu_bo_query_info
amdgpu_bo_set_metadata
amdgpu_bo_va_op
amdgpu_bo_va_op_raw
amdgpu_bo_va_op_raw2
amdgpu_bo_wait_for_idle
amdgpu_create_bo_from_user_mem
amdgpu_cs_chunk_fence_info_to_data
@ -33,6 +25,8 @@ amdgpu_cs_create_syncobj2
amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
amdgpu_cs_ctx_override_priority
amdgpu_cs_ctx_stable_pstate
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
@ -40,38 +34,57 @@ amdgpu_cs_fence_to_handle
amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_query_reset_state2
amdgpu_query_sw_info
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
amdgpu_cs_submit_raw2
amdgpu_cs_syncobj_export_sync_file
amdgpu_cs_syncobj_export_sync_file2
amdgpu_cs_syncobj_import_sync_file
amdgpu_cs_syncobj_import_sync_file2
amdgpu_cs_syncobj_query
amdgpu_cs_syncobj_query2
amdgpu_cs_syncobj_reset
amdgpu_cs_syncobj_signal
amdgpu_cs_syncobj_timeline_signal
amdgpu_cs_syncobj_timeline_wait
amdgpu_cs_syncobj_transfer
amdgpu_cs_syncobj_wait
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
amdgpu_device_get_fd
amdgpu_device_initialize
amdgpu_device_initialize2
amdgpu_find_bo_by_cpu_mapping
amdgpu_get_marketing_name
amdgpu_query_buffer_size_alignment
amdgpu_query_crtc_from_id
amdgpu_query_firmware_version
amdgpu_query_gds_info
amdgpu_query_gpu_info
amdgpu_query_gpuvm_fault_info
amdgpu_query_heap_info
amdgpu_query_hw_ip_count
amdgpu_query_hw_ip_info
amdgpu_query_info
amdgpu_query_sensor_info
amdgpu_query_uq_fw_area_info
amdgpu_query_video_caps_info
amdgpu_read_mm_registers
amdgpu_va_manager_alloc
amdgpu_va_manager_init
amdgpu_va_manager_deinit
amdgpu_va_range_alloc
amdgpu_va_range_alloc2
amdgpu_va_range_free
amdgpu_va_get_start_addr
amdgpu_va_range_query
amdgpu_vm_reserve_vmid
amdgpu_vm_unreserve_vmid
EOF
done)
test ! -n "$FUNCS" || echo $FUNCS
test ! -n "$FUNCS"
amdgpu_create_userqueue
amdgpu_free_userqueue
amdgpu_userq_signal
amdgpu_userq_wait

View file

@ -42,6 +42,10 @@ extern "C" {
#endif
struct drm_amdgpu_info_hw_ip;
struct drm_amdgpu_info_uq_fw_areas;
struct drm_amdgpu_bo_list_entry;
struct drm_amdgpu_userq_signal;
struct drm_amdgpu_userq_wait;
/*--------------------------------------------------------------------------*/
/* --------------------------- Defines ------------------------------------ */
@ -86,8 +90,8 @@ enum amdgpu_bo_handle_type {
/** DMA-buf fd handle */
amdgpu_bo_handle_type_dma_buf_fd = 2,
/** KMS handle, but re-importing as a DMABUF handle through
* drmPrimeHandleToFD is forbidden. (Glamor does that)
/** Deprecated in favour of and same behaviour as
* amdgpu_bo_handle_type_kms, use that instead of this
*/
amdgpu_bo_handle_type_kms_noimport = 3,
};
@ -137,6 +141,12 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
*/
typedef struct amdgpu_va *amdgpu_va_handle;
/**
* Define handle dealing with VA allocation. An amdgpu_device
* owns one of these, but they can also be used without a device.
*/
typedef struct amdgpu_va_manager *amdgpu_va_manager_handle;
/**
* Define handle for semaphore
*/
@ -526,6 +536,20 @@ int amdgpu_device_initialize(int fd,
uint32_t *minor_version,
amdgpu_device_handle *device_handle);
/**
* Same as amdgpu_device_initialize() except when deduplicate_device
* is false *and* fd points to a device that was already initialized.
* In this case, amdgpu_device_initialize would return the same
* amdgpu_device_handle while here amdgpu_device_initialize2 would
* return a new handle.
* amdgpu_device_initialize() should be preferred in most situations;
* the only use-case where not-deduplicating devices make sense is
* when one wants to have isolated device handles in the same process.
*/
int amdgpu_device_initialize2(int fd, bool deduplicate_device,
uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle);
/**
*
* When access to such library does not needed any more the special
@ -545,6 +569,19 @@ int amdgpu_device_initialize(int fd,
*/
int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
/**
*
* /param device_handle - \c [in] Device handle.
* See #amdgpu_device_initialize()
*
* \return Returns the drm fd used for operations on this
* device. This is still owned by the library and hence
* should not be closed. Guaranteed to be valid until
* #amdgpu_device_deinitialize gets called.
*
*/
int amdgpu_device_get_fd(amdgpu_device_handle device_handle);
/*
* Memory Management
*
@ -678,7 +715,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
amdgpu_bo_handle *buf_handle);
/**
* Free previosuly allocated memory
* Validate if the user memory comes from BO
*
* \param dev - [in] Device handle. See #amdgpu_device_initialize()
* \param cpu - [in] CPU address of user allocated memory which we
* want to map to GPU address space (make GPU accessible)
* (This address must be correctly aligned).
* \param size - [in] Size of allocation (must be correctly aligned)
* \param buf_handle - [out] Buffer handle for the userptr memory
* if the user memory is not from BO, the buf_handle will be NULL.
* \param offset_in_bo - [out] offset in this BO for this user memory
*
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
amdgpu_bo_handle *buf_handle,
uint64_t *offset_in_bo);
/**
* Free previously allocated memory
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param buf_handle - \c [in] Buffer handle to free
@ -697,6 +757,16 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
*/
int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
/**
* Increase the reference count of a buffer object
*
* \param bo - \c [in] Buffer object handle to increase the reference count
*
* \sa amdgpu_bo_alloc(), amdgpu_bo_free()
*
*/
void amdgpu_bo_inc_ref(amdgpu_bo_handle bo);
/**
* Request CPU access to GPU accessible memory
*
@ -741,6 +811,37 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
uint64_t timeout_ns,
bool *buffer_busy);
/**
* Creates a BO list handle for command submission.
*
* \param dev - \c [in] Device handle.
* See #amdgpu_device_initialize()
* \param number_of_buffers - \c [in] Number of BOs in the list
* \param buffers - \c [in] List of BO handles
* \param result - \c [out] Created BO list handle
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()
*/
int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
uint32_t number_of_buffers,
struct drm_amdgpu_bo_list_entry *buffers,
uint32_t *result);
/**
* Destroys a BO list handle.
*
* \param bo_list - \c [in] BO list handle.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
*/
int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
/**
* Creates a BO list handle for command submission.
*
@ -846,6 +947,36 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
*/
int amdgpu_cs_ctx_free(amdgpu_context_handle context);
/**
* Override the submission priority for the given context using a master fd.
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param master_fd - \c [in] The master fd to authorize the override.
* \param priority - \c [in] The priority to assign to the context.
*
* \return 0 on success or a a negative Posix error code on failure.
*/
int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
amdgpu_context_handle context,
int master_fd,
unsigned priority);
/**
* Set or query the stable power state for GPU profiling.
*
* \param dev - \c [in] device handle
* \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE
* \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_*
* \param out_flags - \c [out] output current stable pstate
*
* \return 0 on success otherwise POSIX Error code.
*/
int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context,
uint32_t op,
uint32_t flags,
uint32_t *out_flags);
/**
* Query reset state for the specific GPU Context
*
@ -862,6 +993,21 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context);
int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs);
/**
* Query reset state for the specific GPU Context.
*
* \param context - \c [in] GPU Context handle
* \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_*
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_cs_ctx_create()
*
*/
int amdgpu_cs_query_reset_state2(amdgpu_context_handle context,
uint64_t *flags);
/*
* Command Buffers Management
*
@ -1029,6 +1175,26 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info);
/**
* Query FW area related information.
*
* The return size is query-specific and depends on the "type" parameter.
* No more than "size" bytes is returned.
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param type - \c [in] AMDGPU_HW_IP_*
* \param ip_instance - \c [in] HW IP index.
* \param info - \c [out] The pointer to return value
*
* \return 0 on success\n
* <0 - Negative POSIX error code
*
*/
int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev,
unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_uq_fw_areas *info);
/**
* Query heap information
*
@ -1142,6 +1308,39 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
unsigned size, void *value);
/**
* Query information about video capabilities
*
* The return sizeof(struct drm_amdgpu_info_video_caps)
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE)
* \param size - \c [in] Size of the returned value.
* \param value - \c [out] Pointer to the return value.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
unsigned size, void *value);
/**
* Query information about VM faults
*
* The return sizeof(struct drm_amdgpu_info_gpuvm_fault)
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param size - \c [in] Size of the returned value.
* \param value - \c [out] Pointer to the return value.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size,
void *value);
/**
* Read a set of consecutive memory-mapped registers.
* Not all registers are allowed to be read by userspace.
@ -1168,6 +1367,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
*/
#define AMDGPU_VA_RANGE_32_BIT 0x1
#define AMDGPU_VA_RANGE_HIGH 0x2
#define AMDGPU_VA_RANGE_REPLAYABLE 0x4
/**
* Allocate virtual address range
@ -1198,7 +1398,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
* \notes \n
* It is client responsibility to correctly handle VA assignments and usage.
* Neither kernel driver nor libdrm_amdpgu are able to prevent and
* detect wrong va assignemnt.
* detect wrong va assignment.
*
* It is client responsibility to correctly handle multi-GPU cases and to pass
* the corresponding arrays of all devices handles where corresponding VA will
@ -1227,6 +1427,11 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev,
*/
int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
/**
* Return the starting address of the allocated virtual address range.
*/
uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle);
/**
* Query virtual address range
*
@ -1248,6 +1453,37 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
uint64_t *start,
uint64_t *end);
/**
* Allocate a amdgpu_va_manager object.
* The returned object has be initialized with the amdgpu_va_manager_init
* before use.
* On release, amdgpu_va_manager_deinit needs to be called, then the memory
* can be released using free().
*/
amdgpu_va_manager_handle amdgpu_va_manager_alloc(void);
void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr,
uint64_t low_va_offset, uint64_t low_va_max,
uint64_t high_va_offset, uint64_t high_va_max,
uint32_t virtual_address_alignment);
void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr);
/**
* Similar to #amdgpu_va_range_alloc() but allocates VA
* directly from an amdgpu_va_manager_handle instead of using
* the manager from an amdgpu_device.
*/
int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
enum amdgpu_gpu_va_range va_range_type,
uint64_t size,
uint64_t va_base_alignment,
uint64_t va_base_required,
uint64_t *va_base_allocated,
amdgpu_va_handle *va_range_handle,
uint64_t flags);
/**
* VA mapping/unmapping for the buffer object
*
@ -1298,6 +1534,42 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
uint64_t flags,
uint32_t ops);
/**
* VA mapping/unmapping of buffer object for usermode queue.
*
* This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
* parameters are treated "raw2", i.e. size is not automatically aligned, and
* all flags must be specified explicitly.
*
* \param dev - \c [in] device handle
* \param bo - \c [in] BO handle (may be NULL)
* \param offset - \c [in] Start offset to map
* \param size - \c [in] Size to map
* \param addr - \c [in] Start virtual address.
* \param flags - \c [in] Supported flags for mapping/unmapping
* \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
* \param vm_timeline_syncobj_out - \c [out] syncobj handle for PT update fence
* \param vm_timeline_point - \c [in] input timeline point
* \param input_fence_syncobj_handles - \c [in] Array of syncobj handles for bo unmap,
* clear and replace
* \param num_syncobj_handles - \c [in] Number of syncobj handles
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev,
amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops,
uint32_t vm_timeline_syncobj_out,
uint64_t vm_timeline_point,
uint64_t input_fence_syncobj_array_in,
uint32_t num_syncobj_handles_in);
/**
* create semaphore
*
@ -1436,6 +1708,23 @@ int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
const uint32_t *syncobjs, uint32_t syncobj_count);
/**
* Signal kernel timeline sync objects.
*
* \param dev - \c [in] device handle
* \param syncobjs - \c [in] array of sync object handles
* \param points - \c [in] array of timeline points
* \param syncobj_count - \c [in] number of handles in syncobjs
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
const uint32_t *syncobjs,
uint64_t *points,
uint32_t syncobj_count);
/**
* Wait for one or all sync objects to signal.
*
@ -1456,6 +1745,63 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled);
/**
* Wait for one or all sync objects on their points to signal.
*
* \param dev - \c [in] self-explanatory
* \param handles - \c [in] array of sync object handles
* \param points - \c [in] array of sync points to wait
* \param num_handles - \c [in] self-explanatory
* \param timeout_nsec - \c [in] self-explanatory
* \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
* \param first_signaled - \c [in] self-explanatory
*
* \return 0 on success\n
* -ETIME - Timeout
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled);
/**
* Query sync objects payloads.
*
* \param dev - \c [in] self-explanatory
* \param handles - \c [in] array of sync object handles
* \param points - \c [out] array of sync points returned, which presents
* syncobj payload.
* \param num_handles - \c [in] self-explanatory
*
* \return 0 on success\n
* -ETIME - Timeout
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles);
/**
* Query sync objects last signaled or submitted point.
*
* \param dev - \c [in] self-explanatory
* \param handles - \c [in] array of sync object handles
* \param points - \c [out] array of sync points returned, which presents
* syncobj payload.
* \param num_handles - \c [in] self-explanatory
* \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_*
*
* \return 0 on success\n
* -ETIME - Timeout
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles, uint32_t flags);
/**
* Export kernel sync object to shareable fd.
*
@ -1514,6 +1860,62 @@ int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int sync_file_fd);
/**
* Export kernel timeline sync object to a sync_file.
*
* \param dev - \c [in] device handle
* \param syncobj - \c [in] sync object handle
* \param point - \c [in] timeline point
* \param flags - \c [in] flags
* \param sync_file_fd - \c [out] sync_file file descriptor.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
uint32_t syncobj,
uint64_t point,
uint32_t flags,
int *sync_file_fd);
/**
* Import kernel timeline sync object from a sync_file.
*
* \param dev - \c [in] device handle
* \param syncobj - \c [in] sync object handle
* \param point - \c [in] timeline point
* \param sync_file_fd - \c [in] sync_file file descriptor.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
uint32_t syncobj,
uint64_t point,
int sync_file_fd);
/**
* transfer between syncbojs.
*
* \param dev - \c [in] device handle
* \param dst_handle - \c [in] sync object handle
* \param dst_point - \c [in] timeline point, 0 presents dst is binary
* \param src_handle - \c [in] sync object handle
* \param src_point - \c [in] timeline point, 0 presents src is binary
* \param flags - \c [in] flags
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
*/
int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev,
uint32_t dst_handle,
uint64_t dst_point,
uint32_t src_handle,
uint64_t src_point,
uint32_t flags);
/**
* Export an amdgpu fence as a handle (syncobj or fd).
@ -1554,6 +1956,28 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no);
/**
* Submit raw command submission to the kernel with a raw BO list handle.
*
* \param dev - \c [in] device handle
* \param context - \c [in] context handle for context id
* \param bo_list_handle - \c [in] raw bo list handle (0 for none)
* \param num_chunks - \c [in] number of CS chunks to submit
* \param chunks - \c [in] array of CS chunks
* \param seq_no - \c [out] output sequence number for submission.
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
*
* \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()
*/
int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
amdgpu_context_handle context,
uint32_t bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no);
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep);
void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
@ -1577,6 +2001,65 @@ int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags);
*/
int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags);
/**
* Create USERQUEUE
* \param dev - \c [in] device handle
* \param ip_type - \c [in] ip type
* \param doorbell_handle - \c [in] doorbell handle
* \param doorbell_offset - \c [in] doorbell index
* \param mqd_in - \c [in] MQD data
* \param queue_va - \c [in] Virtual address of queue
* \param queue_size - \c [in] userqueue size
* \param wptr_va - \c [in] Virtual address of wptr
* \param rptr_va - \c [in] Virtual address of rptr
* \param queue_id - \c [out] queue id
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_create_userqueue(amdgpu_device_handle dev,
uint32_t ip_type,
uint32_t doorbell_handle,
uint32_t doorbell_offset,
uint64_t queue_va,
uint64_t queue_size,
uint64_t wptr_va,
uint64_t rptr_va,
void *mqd_in,
uint32_t flags,
uint32_t *queue_id);
/**
* Free USERQUEUE
* \param dev - \c [in] device handle
* \param queue_id - \c [in] queue id
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id);
/**
* Signal USERQUEUE
* \param dev - \c [in] device handle
* \param signal_data - \c [in] pointer to struct drm_amdgpu_userq_signal
* to be filled by the caller
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_userq_signal(amdgpu_device_handle dev,
struct drm_amdgpu_userq_signal *signal_data);
/**
* Wait USERQUEUE
* \param dev - \c [in] device handle
* \param wait_data - \c [in/out] pointer to struct drm_amdgpu_userq_wait
* to be filled by the caller
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_userq_wait(amdgpu_device_handle dev,
struct drm_amdgpu_userq_wait *wait_data);
#ifdef __cplusplus
}
#endif

View file

@ -22,6 +22,11 @@
*
*/
// secure_getenv requires _GNU_SOURCE
#ifndef _GNU_SOURCE
#define _GNU_SOURCE
#endif
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
@ -104,6 +109,168 @@ out:
return r;
}
static void amdgpu_parse_proc_cpuinfo(struct amdgpu_device *dev)
{
const char *search_key = "model name";
const char *radeon_key = "Radeon";
char *line = NULL;
size_t len = 0;
FILE *fp;
fp = fopen("/proc/cpuinfo", "r");
if (fp == NULL) {
fprintf(stderr, "%s\n", strerror(errno));
return;
}
while (getline(&line, &len, fp) != -1) {
char *saveptr;
char *value;
if (strncmp(line, search_key, strlen(search_key)))
continue;
/* check for parts that have both CPU and GPU information */
value = strstr(line, radeon_key);
/* get content after the first colon */
if (value == NULL) {
value = strstr(line, ":");
if (value == NULL)
continue;
value++;
}
/* strip whitespace */
while (*value == ' ' || *value == '\t')
value++;
saveptr = strchr(value, '\n');
if (saveptr)
*saveptr = '\0';
/* Add AMD to the new string if it's missing from slicing/dicing */
if (strncmp(value, "AMD", 3) != 0) {
char *tmp = malloc(strlen(value) + 5);
if (!tmp)
break;
sprintf(tmp, "AMD %s", value);
dev->marketing_name = tmp;
} else
dev->marketing_name = strdup(value);
break;
}
free(line);
fclose(fp);
}
#if HAVE_SECURE_GETENV
static char *join_path(const char *dir, const char *file) {
size_t dir_len = strlen(dir);
size_t file_len = strlen(file);
char *full_path = NULL;
int need_slash = ((dir_len > 0) && (dir[dir_len - 1] != '/'));
size_t total_len = dir_len + (need_slash ? 1 : 0) + file_len + 1; // +1 for null terminator
if (dir_len == 0) {
return strdup(file);
}
full_path = malloc(total_len);
if (!full_path) {
return NULL; // Memory allocation failed
}
strcpy(full_path, dir);
if (need_slash) {
full_path[dir_len] = '/';
dir_len++;
}
strcpy(full_path + dir_len, file);
return full_path;
}
static char **split_env_var(const char *env_var_content)
{
char **ret = NULL;
char *dup_env_val;
int elements = 1;
int index = 1;
if (!env_var_content || env_var_content[0] == '\0')
return NULL;
for(char *p = (char *)env_var_content; *p; p++) {
if (*p == ':')
elements++;
}
dup_env_val = strdup(env_var_content);
if (!dup_env_val) {
return NULL;
}
ret = malloc(sizeof(char *) * (elements + 1));
ret[0] = dup_env_val;
for(char *p = (char *)dup_env_val; *p; p++) {
if (*p == ':') {
*p = 0;
ret[index++] = p + 1;
}
}
ret[index] = NULL; // ensure that the last element in the array is NULL
return ret;
}
static void split_env_var_free(char **split_var)
{
if (split_var) {
// remember that the first element also points to the whole duplicated string,
// which was modified in place by replacing ':' with '\0' characters
free(split_var[0]);
free(split_var);
}
}
static char *find_asic_id_table(void)
{
// first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable
const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS");
char *file_name = NULL;
char *found_path = NULL;
char **paths = NULL;
if (!amdgpu_asic_id_table_paths)
return NULL;
// extract the file name from AMDGPU_ASIC_ID_TABLE
file_name = strrchr(AMDGPU_ASIC_ID_TABLE, '/');
if (!file_name)
return NULL;
file_name++; // skip the '/'
paths = split_env_var(amdgpu_asic_id_table_paths);
if (!paths)
return NULL;
// for each path, join with file_name and check if it exists
for (int i = 0; paths[i] != NULL; i++) {
char *full_path = join_path(paths[i], file_name);
if (!full_path) {
continue;
}
if (access(full_path, R_OK) == 0) {
found_path = full_path;
break;
}
}
split_env_var_free(paths);
return found_path;
}
#endif
void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
{
FILE *fp;
@ -113,11 +280,21 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
int line_num = 1;
int r = 0;
fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
char *amdgpu_asic_id_table_path = NULL;
#if HAVE_SECURE_GETENV
// if this system lacks secure_getenv(), don't allow extra paths
// for security reasons.
amdgpu_asic_id_table_path = find_asic_id_table();
#endif
// if not found, use the default AMDGPU_ASIC_ID_TABLE path
if (!amdgpu_asic_id_table_path)
amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE);
fp = fopen(amdgpu_asic_id_table_path, "r");
if (!fp) {
fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
fprintf(stderr, "%s: %s\n", amdgpu_asic_id_table_path,
strerror(errno));
return;
goto get_cpu;
}
/* 1st valid line is file version */
@ -132,7 +309,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
continue;
}
drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
drmMsg("%s version: %s\n", amdgpu_asic_id_table_path, line);
break;
}
@ -150,7 +327,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
if (r == -EINVAL) {
fprintf(stderr, "Invalid format: %s: line %d: %s\n",
AMDGPU_ASIC_ID_TABLE, line_num, line);
amdgpu_asic_id_table_path, line_num, line);
} else if (r && r != -EAGAIN) {
fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n",
__func__, strerror(-r));
@ -158,4 +335,11 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
free(line);
fclose(fp);
get_cpu:
free(amdgpu_asic_id_table_path);
if (dev->info.ids_flags & AMDGPU_IDS_FLAGS_FUSION &&
dev->marketing_name == NULL) {
amdgpu_parse_proc_cpuinfo(dev);
}
}

View file

@ -37,68 +37,80 @@
#include "xf86drm.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
#include "util_hash_table.h"
#include "util_math.h"
static void amdgpu_close_kms_handle(amdgpu_device_handle dev,
uint32_t handle)
{
struct drm_gem_close args = {};
args.handle = handle;
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args);
}
int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
static int amdgpu_bo_create(amdgpu_device_handle dev,
uint64_t size,
uint32_t handle,
amdgpu_bo_handle *buf_handle)
{
struct amdgpu_bo *bo;
union drm_amdgpu_gem_create args;
unsigned heap = alloc_buffer->preferred_heap;
int r = 0;
/* It's an error if the heap is not specified */
if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
return -EINVAL;
int r;
bo = calloc(1, sizeof(struct amdgpu_bo));
if (!bo)
return -ENOMEM;
atomic_set(&bo->refcount, 1);
bo->dev = dev;
bo->alloc_size = alloc_buffer->alloc_size;
memset(&args, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
/* Set the placement. */
args.in.domains = heap;
args.in.domain_flags = alloc_buffer->flags;
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
&args, sizeof(args));
r = handle_table_insert(&dev->bo_handles, handle, bo);
if (r) {
free(bo);
return r;
}
bo->handle = args.out.handle;
atomic_set(&bo->refcount, 1);
bo->dev = dev;
bo->alloc_size = size;
bo->handle = handle;
pthread_mutex_init(&bo->cpu_access_mutex, NULL);
*buf_handle = bo;
return 0;
}
int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
struct amdgpu_bo_metadata *info)
drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev,
struct amdgpu_bo_alloc_request *alloc_buffer,
amdgpu_bo_handle *buf_handle)
{
union drm_amdgpu_gem_create args;
int r;
if (!alloc_buffer || !buf_handle)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
/* Set the placement. */
args.in.domains = alloc_buffer->preferred_heap;
args.in.domain_flags = alloc_buffer->flags;
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
&args, sizeof(args));
if (r)
goto out;
pthread_mutex_lock(&dev->bo_table_mutex);
r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
buf_handle);
pthread_mutex_unlock(&dev->bo_table_mutex);
if (r) {
drmCloseBufferHandle(dev->fd, args.out.handle);
}
out:
return r;
}
drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
struct amdgpu_bo_metadata *info)
{
struct drm_amdgpu_gem_metadata args = {};
if (!info)
return -EINVAL;
args.handle = bo->handle;
args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
args.data.flags = info->flags;
@ -117,8 +129,8 @@ int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
&args, sizeof(args));
}
int amdgpu_bo_query_info(amdgpu_bo_handle bo,
struct amdgpu_bo_info *info)
drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo,
struct amdgpu_bo_info *info)
{
struct drm_amdgpu_gem_metadata metadata = {};
struct drm_amdgpu_gem_create_in bo_info = {};
@ -126,7 +138,7 @@ int amdgpu_bo_query_info(amdgpu_bo_handle bo,
int r;
/* Validate the BO passed in */
if (!bo->handle)
if (!bo->handle || !info)
return -EINVAL;
/* Query metadata. */
@ -168,14 +180,6 @@ int amdgpu_bo_query_info(amdgpu_bo_handle bo,
return 0;
}
static void amdgpu_add_handle_to_table(amdgpu_bo_handle bo)
{
pthread_mutex_lock(&bo->dev->bo_table_mutex);
util_hash_table_set(bo->dev->bo_handles,
(void*)(uintptr_t)bo->handle, bo);
pthread_mutex_unlock(&bo->dev->bo_table_mutex);
}
static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
{
struct drm_gem_flink flink;
@ -209,24 +213,19 @@ static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
bo->flink_name = flink.name;
if (bo->dev->flink_fd != bo->dev->fd) {
struct drm_gem_close args = {};
args.handle = handle;
drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, &args);
}
if (bo->dev->flink_fd != bo->dev->fd)
drmCloseBufferHandle(bo->dev->flink_fd, handle);
pthread_mutex_lock(&bo->dev->bo_table_mutex);
util_hash_table_set(bo->dev->bo_flink_names,
(void*)(uintptr_t)bo->flink_name,
bo);
r = handle_table_insert(&bo->dev->bo_flink_names, bo->flink_name, bo);
pthread_mutex_unlock(&bo->dev->bo_table_mutex);
return 0;
return r;
}
int amdgpu_bo_export(amdgpu_bo_handle bo,
enum amdgpu_bo_handle_type type,
uint32_t *shared_handle)
drm_public int amdgpu_bo_export(amdgpu_bo_handle bo,
enum amdgpu_bo_handle_type type,
uint32_t *shared_handle)
{
int r;
@ -240,14 +239,11 @@ int amdgpu_bo_export(amdgpu_bo_handle bo,
return 0;
case amdgpu_bo_handle_type_kms:
amdgpu_add_handle_to_table(bo);
/* fall through */
case amdgpu_bo_handle_type_kms_noimport:
*shared_handle = bo->handle;
return 0;
case amdgpu_bo_handle_type_dma_buf_fd:
amdgpu_add_handle_to_table(bo);
return drmPrimeHandleToFD(bo->dev->fd, bo->handle,
DRM_CLOEXEC | DRM_RDWR,
(int*)shared_handle);
@ -255,14 +251,16 @@ int amdgpu_bo_export(amdgpu_bo_handle bo,
return -EINVAL;
}
int amdgpu_bo_import(amdgpu_device_handle dev,
enum amdgpu_bo_handle_type type,
uint32_t shared_handle,
drm_public int amdgpu_bo_import(amdgpu_device_handle dev,
enum amdgpu_bo_handle_type type,
uint32_t shared_handle,
struct amdgpu_bo_import_result *output)
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
int r;
uint32_t handle = 0, flink_name = 0;
uint64_t alloc_size = 0;
int r = 0;
int dma_fd;
uint64_t dma_buf_size = 0;
@ -272,22 +270,18 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle);
if (r) {
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
if (r)
goto unlock;
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
pthread_mutex_unlock(&dev->bo_table_mutex);
amdgpu_close_kms_handle(dev, handle);
return -errno;
r = -errno;
goto free_bo_handle;
}
lseek(shared_handle, 0, SEEK_SET);
@ -298,24 +292,22 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
/* If we have already created a buffer with this handle, find it. */
switch (type) {
case amdgpu_bo_handle_type_gem_flink_name:
bo = util_hash_table_get(dev->bo_flink_names,
(void*)(uintptr_t)shared_handle);
bo = handle_table_lookup(&dev->bo_flink_names, shared_handle);
break;
case amdgpu_bo_handle_type_dma_buf_fd:
bo = util_hash_table_get(dev->bo_handles,
(void*)(uintptr_t)shared_handle);
bo = handle_table_lookup(&dev->bo_handles, shared_handle);
break;
case amdgpu_bo_handle_type_kms:
case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
pthread_mutex_unlock(&dev->bo_table_mutex);
return -EPERM;
r = -EPERM;
goto unlock;
default:
pthread_mutex_unlock(&dev->bo_table_mutex);
return -EINVAL;
r = -EINVAL;
goto unlock;
}
if (bo) {
@ -328,53 +320,37 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
return 0;
}
bo = calloc(1, sizeof(struct amdgpu_bo));
if (!bo) {
pthread_mutex_unlock(&dev->bo_table_mutex);
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
amdgpu_close_kms_handle(dev, shared_handle);
}
return -ENOMEM;
}
/* Open the handle. */
switch (type) {
case amdgpu_bo_handle_type_gem_flink_name:
open_arg.name = shared_handle;
r = drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_OPEN, &open_arg);
if (r) {
free(bo);
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
if (r)
goto unlock;
bo->handle = open_arg.handle;
flink_name = shared_handle;
handle = open_arg.handle;
alloc_size = open_arg.size;
if (dev->flink_fd != dev->fd) {
r = drmPrimeHandleToFD(dev->flink_fd, bo->handle, DRM_CLOEXEC, &dma_fd);
if (r) {
free(bo);
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
r = drmPrimeFDToHandle(dev->fd, dma_fd, &bo->handle );
r = drmPrimeHandleToFD(dev->flink_fd, handle,
DRM_CLOEXEC, &dma_fd);
if (r)
goto free_bo_handle;
r = drmPrimeFDToHandle(dev->fd, dma_fd, &handle);
close(dma_fd);
if (r) {
free(bo);
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
if (r)
goto free_bo_handle;
r = drmCloseBufferHandle(dev->flink_fd,
open_arg.handle);
if (r)
goto free_bo_handle;
}
bo->flink_name = shared_handle;
bo->alloc_size = open_arg.size;
util_hash_table_set(dev->bo_flink_names,
(void*)(uintptr_t)bo->flink_name, bo);
open_arg.handle = 0;
break;
case amdgpu_bo_handle_type_dma_buf_fd:
bo->handle = shared_handle;
bo->alloc_size = dma_buf_size;
handle = shared_handle;
alloc_size = dma_buf_size;
break;
case amdgpu_bo_handle_type_kms:
@ -383,19 +359,38 @@ int amdgpu_bo_import(amdgpu_device_handle dev,
}
/* Initialize it. */
atomic_set(&bo->refcount, 1);
bo->dev = dev;
pthread_mutex_init(&bo->cpu_access_mutex, NULL);
r = amdgpu_bo_create(dev, alloc_size, handle, &bo);
if (r)
goto free_bo_handle;
util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo);
pthread_mutex_unlock(&dev->bo_table_mutex);
if (flink_name) {
bo->flink_name = flink_name;
r = handle_table_insert(&dev->bo_flink_names, flink_name,
bo);
if (r)
goto free_bo_handle;
}
output->buf_handle = bo;
output->alloc_size = bo->alloc_size;
pthread_mutex_unlock(&dev->bo_table_mutex);
return 0;
free_bo_handle:
if (flink_name && open_arg.handle)
drmCloseBufferHandle(dev->flink_fd, open_arg.handle);
if (bo)
amdgpu_bo_free(bo);
else
drmCloseBufferHandle(dev->fd, handle);
unlock:
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
drm_public int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
{
struct amdgpu_device *dev;
struct amdgpu_bo *bo = buf_handle;
@ -406,13 +401,11 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
if (update_references(&bo->refcount, NULL)) {
/* Remove the buffer from the hash tables. */
util_hash_table_remove(dev->bo_handles,
(void*)(uintptr_t)bo->handle);
handle_table_remove(&dev->bo_handles, bo->handle);
if (bo->flink_name) {
util_hash_table_remove(dev->bo_flink_names,
(void*)(uintptr_t)bo->flink_name);
}
if (bo->flink_name)
handle_table_remove(&dev->bo_flink_names,
bo->flink_name);
/* Release CPU access. */
if (bo->cpu_map_count > 0) {
@ -420,16 +413,22 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
amdgpu_bo_cpu_unmap(bo);
}
amdgpu_close_kms_handle(dev, bo->handle);
drmCloseBufferHandle(dev->fd, bo->handle);
pthread_mutex_destroy(&bo->cpu_access_mutex);
free(bo);
}
pthread_mutex_unlock(&dev->bo_table_mutex);
return 0;
}
int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
drm_public void amdgpu_bo_inc_ref(amdgpu_bo_handle bo)
{
atomic_inc(&bo->refcount);
}
drm_public int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
{
union drm_amdgpu_gem_mmap args;
void *ptr;
@ -477,7 +476,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
return 0;
}
int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
drm_public int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
{
int r;
@ -503,7 +502,7 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
return r;
}
int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
drm_public int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments *info)
{
info->size_local = dev->dev_info.pte_fragment_size;
@ -511,8 +510,8 @@ int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
return 0;
}
int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
uint64_t timeout_ns,
drm_public int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
uint64_t timeout_ns,
bool *busy)
{
union drm_amdgpu_gem_wait_idle args;
@ -534,13 +533,54 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
}
}
int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
amdgpu_bo_handle *buf_handle)
drm_public int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
amdgpu_bo_handle *buf_handle,
uint64_t *offset_in_bo)
{
struct amdgpu_bo *bo = NULL;
uint32_t i;
int r = 0;
if (cpu == NULL || size == 0)
return -EINVAL;
/*
* Workaround for a buggy application which tries to import previously
* exposed CPU pointers. If we find a real world use case we should
* improve that by asking the kernel for the right handle.
*/
pthread_mutex_lock(&dev->bo_table_mutex);
for (i = 0; i < dev->bo_handles.max_key; i++) {
bo = handle_table_lookup(&dev->bo_handles, i);
if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
continue;
if (cpu >= bo->cpu_ptr &&
cpu < (void*)((uintptr_t)bo->cpu_ptr + (size_t)bo->alloc_size))
break;
}
if (i < dev->bo_handles.max_key) {
atomic_inc(&bo->refcount);
*buf_handle = bo;
*offset_in_bo = (uintptr_t)cpu - (uintptr_t)bo->cpu_ptr;
} else {
*buf_handle = NULL;
*offset_in_bo = 0;
r = -ENXIO;
}
pthread_mutex_unlock(&dev->bo_table_mutex);
return r;
}
drm_public int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
void *cpu,
uint64_t size,
amdgpu_bo_handle *buf_handle)
{
int r;
struct amdgpu_bo *bo;
struct drm_amdgpu_gem_userptr args;
args.addr = (uintptr_t)cpu;
@ -550,34 +590,65 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
&args, sizeof(args));
if (r)
return r;
goto out;
bo = calloc(1, sizeof(struct amdgpu_bo));
if (!bo)
return -ENOMEM;
atomic_set(&bo->refcount, 1);
bo->dev = dev;
bo->alloc_size = size;
bo->handle = args.handle;
*buf_handle = bo;
pthread_mutex_lock(&dev->bo_table_mutex);
r = amdgpu_bo_create(dev, size, args.handle, buf_handle);
pthread_mutex_unlock(&dev->bo_table_mutex);
if (r) {
drmCloseBufferHandle(dev->fd, args.handle);
}
out:
return r;
}
int amdgpu_bo_list_create(amdgpu_device_handle dev,
uint32_t number_of_resources,
amdgpu_bo_handle *resources,
uint8_t *resource_prios,
amdgpu_bo_list_handle *result)
drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
uint32_t number_of_buffers,
struct drm_amdgpu_bo_list_entry *buffers,
uint32_t *result)
{
union drm_amdgpu_bo_list args;
int r;
memset(&args, 0, sizeof(args));
args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
args.in.bo_number = number_of_buffers;
args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
&args, sizeof(args));
if (!r)
*result = args.out.list_handle;
return r;
}
drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev,
uint32_t bo_list)
{
union drm_amdgpu_bo_list args;
memset(&args, 0, sizeof(args));
args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
args.in.list_handle = bo_list;
return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
&args, sizeof(args));
}
drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
uint32_t number_of_resources,
amdgpu_bo_handle *resources,
uint8_t *resource_prios,
amdgpu_bo_list_handle *result)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
unsigned i;
int r;
if (!number_of_resources)
if (!number_of_resources || !resources)
return -EINVAL;
/* overflow check for multiplication */
@ -621,7 +692,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev,
return 0;
}
int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
drm_public int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
{
union drm_amdgpu_bo_list args;
int r;
@ -639,10 +710,10 @@ int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
return r;
}
int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
uint32_t number_of_resources,
amdgpu_bo_handle *resources,
uint8_t *resource_prios)
drm_public int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
uint32_t number_of_resources,
amdgpu_bo_handle *resources,
uint8_t *resource_prios)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
@ -680,12 +751,12 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
return r;
}
int amdgpu_bo_va_op(amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops)
drm_public int amdgpu_bo_va_op(amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops)
{
amdgpu_device_handle dev = bo->dev;
@ -697,13 +768,13 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo,
AMDGPU_VM_PAGE_EXECUTABLE, ops);
}
int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops)
drm_public int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops)
{
struct drm_amdgpu_gem_va va;
int r;
@ -724,3 +795,39 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
return r;
}
drm_public int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev,
amdgpu_bo_handle bo,
uint64_t offset,
uint64_t size,
uint64_t addr,
uint64_t flags,
uint32_t ops,
uint32_t vm_timeline_syncobj_out,
uint64_t vm_timeline_point,
uint64_t input_fence_syncobj_handles,
uint32_t num_syncobj_handles)
{
struct drm_amdgpu_gem_va va;
int r;
if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP &&
ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR)
return -EINVAL;
memset(&va, 0, sizeof(va));
va.handle = bo ? bo->handle : 0;
va.operation = ops;
va.flags = flags;
va.va_address = addr;
va.offset_in_bo = offset;
va.map_size = size;
va.vm_timeline_syncobj_out = vm_timeline_syncobj_out;
va.vm_timeline_point = vm_timeline_point;
va.input_fence_syncobj_handles = input_fence_syncobj_handles;
va.num_syncobj_handles = num_syncobj_handles;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
return r;
}

View file

@ -28,7 +28,7 @@
#include <pthread.h>
#include <sched.h>
#include <sys/ioctl.h>
#ifdef HAVE_ALLOCA_H
#if HAVE_ALLOCA_H
# include <alloca.h>
#endif
@ -48,17 +48,30 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority,
amdgpu_context_handle *context)
drm_public int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
uint32_t priority,
amdgpu_context_handle *context)
{
struct amdgpu_context *gpu_context;
union drm_amdgpu_ctx args;
int i, j, k;
int r;
char *override_priority;
if (!dev || !context)
return -EINVAL;
override_priority = getenv("AMD_PRIORITY");
if (override_priority) {
/* The priority is a signed integer. The variable type is
* wrong. If parsing fails, priority is unchanged.
*/
if (sscanf(override_priority, "%i", &priority) == 1) {
printf("amdgpu: context priority changed to %i\n",
priority);
}
}
gpu_context = calloc(1, sizeof(struct amdgpu_context));
if (!gpu_context)
return -ENOMEM;
@ -93,8 +106,8 @@ error:
return r;
}
int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
amdgpu_context_handle *context)
drm_public int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
amdgpu_context_handle *context)
{
return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context);
}
@ -107,7 +120,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
*
* \return 0 on success otherwise POSIX Error code
*/
int amdgpu_cs_ctx_free(amdgpu_context_handle context)
drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle context)
{
union drm_amdgpu_ctx args;
int i, j, k;
@ -127,8 +140,8 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) {
for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) {
amdgpu_semaphore_handle sem;
LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) {
amdgpu_semaphore_handle sem, tmp;
LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, &context->sem_list[i][j][k], list) {
list_del(&sem->list);
amdgpu_cs_reset_sem(sem);
amdgpu_cs_unreference_sem(sem);
@ -141,8 +154,55 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context)
return r;
}
int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs)
drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
amdgpu_context_handle context,
int master_fd,
unsigned priority)
{
union drm_amdgpu_sched args;
int r;
if (!dev || !context || master_fd < 0)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
args.in.fd = dev->fd;
args.in.priority = priority;
args.in.ctx_id = context->id;
r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
if (r)
return r;
return 0;
}
drm_public int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context,
uint32_t op,
uint32_t flags,
uint32_t *out_flags)
{
union drm_amdgpu_ctx args;
int r;
if (!context)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.op = op;
args.in.ctx_id = context->id;
args.in.flags = flags;
r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
&args, sizeof(args));
if (!r && out_flags)
*out_flags = args.out.pstate.flags;
return r;
}
drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs)
{
union drm_amdgpu_ctx args;
int r;
@ -162,6 +222,25 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
return r;
}
drm_public int amdgpu_cs_query_reset_state2(amdgpu_context_handle context,
uint64_t *flags)
{
union drm_amdgpu_ctx args;
int r;
if (!context)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_QUERY_STATE2;
args.in.ctx_id = context->id;
r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
&args, sizeof(args));
if (!r)
*flags = args.out.state.flags;
return r;
}
/**
* Submit command to kernel DRM
* \param dev - \c [in] Device handle
@ -175,15 +254,15 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
static int amdgpu_cs_submit_one(amdgpu_context_handle context,
struct amdgpu_cs_request *ibs_request)
{
union drm_amdgpu_cs cs;
uint64_t *chunk_array;
struct drm_amdgpu_cs_chunk *chunks;
struct drm_amdgpu_cs_chunk_data *chunk_data;
struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
amdgpu_device_handle dev = context->dev;
struct list_head *sem_list;
amdgpu_semaphore_handle sem, tmp;
uint32_t i, size, sem_count = 0;
uint32_t i, size, num_chunks, bo_list_handle = 0, sem_count = 0;
uint64_t seq_no;
bool user_fence;
int r = 0;
@ -199,23 +278,18 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
chunk_array = alloca(sizeof(uint64_t) * size);
chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
size = ibs_request->number_of_ibs + (user_fence ? 1 : 0);
chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
memset(&cs, 0, sizeof(cs));
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
cs.in.ctx_id = context->id;
if (ibs_request->resources)
cs.in.bo_list_handle = ibs_request->resources->handle;
cs.in.num_chunks = ibs_request->number_of_ibs;
bo_list_handle = ibs_request->resources->handle;
num_chunks = ibs_request->number_of_ibs;
/* IB chunks */
for (i = 0; i < ibs_request->number_of_ibs; i++) {
struct amdgpu_cs_ib_info *ib;
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
@ -234,10 +308,9 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
pthread_mutex_lock(&context->sequence_mutex);
if (user_fence) {
i = cs.in.num_chunks++;
i = num_chunks++;
/* fence chunk */
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
@ -250,7 +323,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
}
if (ibs_request->number_of_dependencies) {
dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) *
dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) *
ibs_request->number_of_dependencies);
if (!dependencies) {
r = -ENOMEM;
@ -267,10 +340,9 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
dep->handle = info->fence;
}
i = cs.in.num_chunks++;
i = num_chunks++;
/* dependencies chunk */
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
* ibs_request->number_of_dependencies;
@ -281,7 +353,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
LIST_FOR_EACH_ENTRY(sem, sem_list, list)
sem_count++;
if (sem_count) {
sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count);
sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count);
if (!sem_dependencies) {
r = -ENOMEM;
goto error_unlock;
@ -300,33 +372,30 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
amdgpu_cs_reset_sem(sem);
amdgpu_cs_unreference_sem(sem);
}
i = cs.in.num_chunks++;
i = num_chunks++;
/* dependencies chunk */
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
}
r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
&cs, sizeof(cs));
r = amdgpu_cs_submit_raw2(dev, context, bo_list_handle, num_chunks,
chunks, &seq_no);
if (r)
goto error_unlock;
ibs_request->seq_no = cs.out.handle;
ibs_request->seq_no = seq_no;
context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no;
error_unlock:
pthread_mutex_unlock(&context->sequence_mutex);
free(dependencies);
free(sem_dependencies);
return r;
}
int amdgpu_cs_submit(amdgpu_context_handle context,
uint64_t flags,
struct amdgpu_cs_request *ibs_request,
uint32_t number_of_requests)
drm_public int amdgpu_cs_submit(amdgpu_context_handle context,
uint64_t flags,
struct amdgpu_cs_request *ibs_request,
uint32_t number_of_requests)
{
uint32_t i;
int r;
@ -407,10 +476,10 @@ static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
return 0;
}
int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
uint64_t timeout_ns,
uint64_t flags,
uint32_t *expired)
drm_public int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
uint64_t timeout_ns,
uint64_t flags,
uint32_t *expired)
{
bool busy = true;
int r;
@ -478,12 +547,12 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
return 0;
}
int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
uint32_t fence_count,
bool wait_all,
uint64_t timeout_ns,
uint32_t *status,
uint32_t *first)
drm_public int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
uint32_t fence_count,
bool wait_all,
uint64_t timeout_ns,
uint32_t *status,
uint32_t *first)
{
uint32_t i;
@ -506,7 +575,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
timeout_ns, status, first);
}
int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
drm_public int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
{
struct amdgpu_semaphore *gpu_semaphore;
@ -523,34 +592,41 @@ int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
return 0;
}
int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
uint32_t ip_type,
drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
uint32_t ip_type,
uint32_t ip_instance,
uint32_t ring,
amdgpu_semaphore_handle sem)
{
int ret;
if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
/* sem has been signaled */
if (sem->signal_fence.context)
return -EINVAL;
pthread_mutex_lock(&ctx->sequence_mutex);
/* sem has been signaled */
if (sem->signal_fence.context) {
ret = -EINVAL;
goto unlock;
}
sem->signal_fence.context = ctx;
sem->signal_fence.ip_type = ip_type;
sem->signal_fence.ip_instance = ip_instance;
sem->signal_fence.ring = ring;
sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
update_references(NULL, &sem->refcount);
ret = 0;
unlock:
pthread_mutex_unlock(&ctx->sequence_mutex);
return 0;
return ret;
}
int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
uint32_t ip_type,
drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
uint32_t ip_type,
uint32_t ip_instance,
uint32_t ring,
amdgpu_semaphore_handle sem)
@ -595,14 +671,14 @@ static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
return 0;
}
int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
drm_public int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
{
return amdgpu_cs_unreference_sem(sem);
}
int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
uint32_t flags,
uint32_t *handle)
drm_public int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
uint32_t flags,
uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@ -610,8 +686,8 @@ int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
return drmSyncobjCreate(dev->fd, flags, handle);
}
int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
uint32_t *handle)
drm_public int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@ -619,8 +695,8 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
return drmSyncobjCreate(dev->fd, 0, handle);
}
int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t handle)
drm_public int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t handle)
{
if (NULL == dev)
return -EINVAL;
@ -628,8 +704,9 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
return drmSyncobjDestroy(dev->fd, handle);
}
int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
const uint32_t *syncobjs, uint32_t syncobj_count)
drm_public int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
const uint32_t *syncobjs,
uint32_t syncobj_count)
{
if (NULL == dev)
return -EINVAL;
@ -637,8 +714,9 @@ int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
return drmSyncobjReset(dev->fd, syncobjs, syncobj_count);
}
int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
const uint32_t *syncobjs, uint32_t syncobj_count)
drm_public int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
const uint32_t *syncobjs,
uint32_t syncobj_count)
{
if (NULL == dev)
return -EINVAL;
@ -646,10 +724,22 @@ int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count);
}
int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled)
drm_public int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
const uint32_t *syncobjs,
uint64_t *points,
uint32_t syncobj_count)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjTimelineSignal(dev->fd, syncobjs,
points, syncobj_count);
}
drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled)
{
if (NULL == dev)
return -EINVAL;
@ -658,9 +748,42 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
flags, first_signaled);
}
int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
uint32_t handle,
int *shared_fd)
drm_public int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjTimelineWait(dev->fd, handles, points, num_handles,
timeout_nsec, flags, first_signaled);
}
drm_public int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjQuery(dev->fd, handles, points, num_handles);
}
drm_public int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev,
uint32_t *handles, uint64_t *points,
unsigned num_handles, uint32_t flags)
{
if (!dev)
return -EINVAL;
return drmSyncobjQuery2(dev->fd, handles, points, num_handles, flags);
}
drm_public int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
uint32_t handle,
int *shared_fd)
{
if (NULL == dev)
return -EINVAL;
@ -668,9 +791,9 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
}
int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
int shared_fd,
uint32_t *handle)
drm_public int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
int shared_fd,
uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@ -678,9 +801,9 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int *sync_file_fd)
drm_public int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int *sync_file_fd)
{
if (NULL == dev)
return -EINVAL;
@ -688,9 +811,9 @@ int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
}
int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int sync_file_fd)
drm_public int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int sync_file_fd)
{
if (NULL == dev)
return -EINVAL;
@ -698,19 +821,92 @@ int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
}
int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
amdgpu_context_handle context,
amdgpu_bo_list_handle bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no)
drm_public int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
uint32_t syncobj,
uint64_t point,
uint32_t flags,
int *sync_file_fd)
{
union drm_amdgpu_cs cs = {0};
uint32_t binary_handle;
int ret;
if (NULL == dev)
return -EINVAL;
if (!point)
return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
if (ret)
return ret;
ret = drmSyncobjTransfer(dev->fd, binary_handle, 0,
syncobj, point, flags);
if (ret)
goto out;
ret = drmSyncobjExportSyncFile(dev->fd, binary_handle, sync_file_fd);
out:
drmSyncobjDestroy(dev->fd, binary_handle);
return ret;
}
drm_public int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
uint32_t syncobj,
uint64_t point,
int sync_file_fd)
{
uint32_t binary_handle;
int ret;
if (NULL == dev)
return -EINVAL;
if (!point)
return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
if (ret)
return ret;
ret = drmSyncobjImportSyncFile(dev->fd, binary_handle, sync_file_fd);
if (ret)
goto out;
ret = drmSyncobjTransfer(dev->fd, syncobj, point,
binary_handle, 0, 0);
out:
drmSyncobjDestroy(dev->fd, binary_handle);
return ret;
}
drm_public int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev,
uint32_t dst_handle,
uint64_t dst_point,
uint32_t src_handle,
uint64_t src_point,
uint32_t flags)
{
if (NULL == dev)
return -EINVAL;
return drmSyncobjTransfer(dev->fd,
dst_handle, dst_point,
src_handle, src_point,
flags);
}
drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
amdgpu_context_handle context,
amdgpu_bo_list_handle bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no)
{
union drm_amdgpu_cs cs;
uint64_t *chunk_array;
int i, r;
if (num_chunks == 0)
return -EINVAL;
memset(&cs, 0, sizeof(cs));
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
for (i = 0; i < num_chunks; i++)
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
@ -728,15 +924,41 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
return 0;
}
void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
amdgpu_context_handle context,
uint32_t bo_list_handle,
int num_chunks,
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no)
{
union drm_amdgpu_cs cs;
uint64_t *chunk_array;
int i, r;
memset(&cs, 0, sizeof(cs));
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
for (i = 0; i < num_chunks; i++)
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
cs.in.ctx_id = context->id;
cs.in.bo_list_handle = bo_list_handle;
cs.in.num_chunks = num_chunks;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
&cs, sizeof(cs));
if (!r && seq_no)
*seq_no = cs.out.handle;
return r;
}
drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
struct drm_amdgpu_cs_chunk_data *data)
{
data->fence_data.handle = fence_info->handle->handle;
data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
}
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep)
drm_public void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep)
{
dep->ip_type = fence->ip_type;
dep->ip_instance = fence->ip_instance;
@ -745,14 +967,15 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
dep->handle = fence->fence;
}
int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
struct amdgpu_cs_fence *fence,
uint32_t what,
uint32_t *out_handle)
drm_public int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
struct amdgpu_cs_fence *fence,
uint32_t what,
uint32_t *out_handle)
{
union drm_amdgpu_fence_to_handle fth = {0};
union drm_amdgpu_fence_to_handle fth;
int r;
memset(&fth, 0, sizeof(fth));
fth.in.fence.ctx_id = fence->context->id;
fth.in.fence.ip_type = fence->ip_type;
fth.in.fence.ip_instance = fence->ip_instance;

View file

@ -39,47 +39,15 @@
#include "xf86drm.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
#include "util_hash_table.h"
#include "util_math.h"
#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
static pthread_mutex_t fd_mutex = PTHREAD_MUTEX_INITIALIZER;
static struct util_hash_table *fd_tab;
static pthread_mutex_t dev_mutex = PTHREAD_MUTEX_INITIALIZER;
static amdgpu_device_handle dev_list;
static unsigned handle_hash(void *key)
static int fd_compare(int fd1, int fd2)
{
return PTR_TO_UINT(key);
}
static int handle_compare(void *key1, void *key2)
{
return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
}
static unsigned fd_hash(void *key)
{
int fd = PTR_TO_UINT(key);
char *name = drmGetPrimaryDeviceNameFromFd(fd);
unsigned result = 0;
char *c;
if (name == NULL)
return 0;
for (c = name; *c; ++c)
result += *c;
free(name);
return result;
}
static int fd_compare(void *key1, void *key2)
{
int fd1 = PTR_TO_UINT(key1);
int fd2 = PTR_TO_UINT(key2);
char *name1 = drmGetPrimaryDeviceNameFromFd(fd1);
char *name2 = drmGetPrimaryDeviceNameFromFd(fd2);
int result;
@ -127,23 +95,28 @@ static int amdgpu_get_auth(int fd, int *auth)
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
{
pthread_mutex_lock(&fd_mutex);
util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
if (util_hash_table_count(fd_tab) == 0) {
util_hash_table_destroy(fd_tab);
fd_tab = NULL;
/* Remove dev from dev_list, if it was added there. */
if (dev == dev_list) {
dev_list = dev->next;
} else {
for (amdgpu_device_handle node = dev_list; node; node = node->next) {
if (node->next == dev) {
node->next = dev->next;
break;
}
}
}
close(dev->fd);
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
close(dev->flink_fd);
pthread_mutex_unlock(&fd_mutex);
amdgpu_vamgr_deinit(&dev->vamgr_32);
amdgpu_vamgr_deinit(&dev->vamgr);
amdgpu_vamgr_deinit(&dev->vamgr_high_32);
amdgpu_vamgr_deinit(&dev->vamgr_high);
util_hash_table_destroy(dev->bo_flink_names);
util_hash_table_destroy(dev->bo_handles);
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_32);
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_low);
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high_32);
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high);
handle_table_fini(&dev->bo_handles);
handle_table_fini(&dev->bo_flink_names);
pthread_mutex_destroy(&dev->bo_table_mutex);
free(dev->marketing_name);
free(dev);
@ -164,45 +137,49 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev)
* // incremented. dst is freed if its reference counter is 0.
*/
static void amdgpu_device_reference(struct amdgpu_device **dst,
struct amdgpu_device *src)
struct amdgpu_device *src)
{
if (update_references(&(*dst)->refcount, &src->refcount))
amdgpu_device_free_internal(*dst);
*dst = src;
}
int amdgpu_device_initialize(int fd,
uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle)
static int _amdgpu_device_initialize(int fd,
uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle,
bool deduplicate_device)
{
struct amdgpu_device *dev;
struct amdgpu_device *dev = NULL;
drmVersionPtr version;
int r;
int flag_auth = 0;
int flag_authexist=0;
uint32_t accel_working = 0;
uint64_t start, max;
*device_handle = NULL;
pthread_mutex_lock(&fd_mutex);
if (!fd_tab)
fd_tab = util_hash_table_create(fd_hash, fd_compare);
pthread_mutex_lock(&dev_mutex);
r = amdgpu_get_auth(fd, &flag_auth);
if (r) {
fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
__func__, r);
pthread_mutex_unlock(&fd_mutex);
pthread_mutex_unlock(&dev_mutex);
return r;
}
dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
if (deduplicate_device)
for (dev = dev_list; dev; dev = dev->next)
if (fd_compare(dev->fd, fd) == 0)
break;
if (dev) {
r = amdgpu_get_auth(dev->fd, &flag_authexist);
if (r) {
fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n",
__func__, r);
pthread_mutex_unlock(&fd_mutex);
pthread_mutex_unlock(&dev_mutex);
return r;
}
if ((flag_auth) && (!flag_authexist)) {
@ -211,14 +188,14 @@ int amdgpu_device_initialize(int fd,
*major_version = dev->major_version;
*minor_version = dev->minor_version;
amdgpu_device_reference(device_handle, dev);
pthread_mutex_unlock(&fd_mutex);
pthread_mutex_unlock(&dev_mutex);
return 0;
}
dev = calloc(1, sizeof(struct amdgpu_device));
if (!dev) {
fprintf(stderr, "%s: calloc failed\n", __func__);
pthread_mutex_unlock(&fd_mutex);
pthread_mutex_unlock(&dev_mutex);
return -ENOMEM;
}
@ -246,9 +223,6 @@ int amdgpu_device_initialize(int fd,
dev->minor_version = version->version_minor;
drmFreeVersion(version);
dev->bo_flink_names = util_hash_table_create(handle_hash,
handle_compare);
dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
pthread_mutex_init(&dev->bo_table_mutex, NULL);
/* Check if acceleration is working. */
@ -270,35 +244,23 @@ int amdgpu_device_initialize(int fd,
goto cleanup;
}
start = dev->dev_info.virtual_address_offset;
max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
start = max;
max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr, start, max,
dev->dev_info.virtual_address_alignment);
start = dev->dev_info.high_va_offset;
max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr_high_32, start, max,
dev->dev_info.virtual_address_alignment);
start = max;
max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr_high, start, max,
dev->dev_info.virtual_address_alignment);
amdgpu_va_manager_init(&dev->va_mgr,
dev->dev_info.virtual_address_offset,
dev->dev_info.virtual_address_max,
dev->dev_info.high_va_offset,
dev->dev_info.high_va_max,
dev->dev_info.virtual_address_alignment);
amdgpu_parse_asic_ids(dev);
*major_version = dev->major_version;
*minor_version = dev->minor_version;
*device_handle = dev;
util_hash_table_set(fd_tab, UINT_TO_PTR(dev->fd), dev);
pthread_mutex_unlock(&fd_mutex);
if (deduplicate_device) {
dev->next = dev_list;
dev_list = dev;
}
pthread_mutex_unlock(&dev_mutex);
return 0;
@ -306,32 +268,59 @@ cleanup:
if (dev->fd >= 0)
close(dev->fd);
free(dev);
pthread_mutex_unlock(&fd_mutex);
pthread_mutex_unlock(&dev_mutex);
return r;
}
int amdgpu_device_deinitialize(amdgpu_device_handle dev)
drm_public int amdgpu_device_initialize(int fd,
uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle)
{
return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, true);
}
drm_public int amdgpu_device_initialize2(int fd, bool deduplicate_device,
uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle)
{
return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, deduplicate_device);
}
drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev)
{
pthread_mutex_lock(&dev_mutex);
amdgpu_device_reference(&dev, NULL);
pthread_mutex_unlock(&dev_mutex);
return 0;
}
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
drm_public int amdgpu_device_get_fd(amdgpu_device_handle device_handle)
{
return dev->marketing_name;
return device_handle->fd;
}
int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
void *value)
drm_public const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
if (dev->marketing_name)
return dev->marketing_name;
else
return "AMD Radeon Graphics";
}
drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
enum amdgpu_sw_info info,
void *value)
{
uint32_t *val32 = (uint32_t*)value;
switch (info) {
case amdgpu_sw_info_address32_hi:
if (dev->vamgr_high_32.va_max)
*val32 = (dev->vamgr_high_32.va_max - 1) >> 32;
if (dev->va_mgr.vamgr_high_32.va_max)
*val32 = (dev->va_mgr.vamgr_high_32.va_max - 1) >> 32;
else
*val32 = (dev->vamgr_32.va_max - 1) >> 32;
*val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32;
return 0;
}
return -EINVAL;

View file

@ -30,8 +30,8 @@
#include "amdgpu_internal.h"
#include "xf86drm.h"
int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
unsigned size, void *value)
drm_public int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
unsigned size, void *value)
{
struct drm_amdgpu_info request;
@ -44,8 +44,8 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
sizeof(struct drm_amdgpu_info));
}
int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
int32_t *result)
drm_public int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
int32_t *result)
{
struct drm_amdgpu_info request;
@ -59,9 +59,9 @@ int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
sizeof(struct drm_amdgpu_info));
}
int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
unsigned count, uint32_t instance, uint32_t flags,
uint32_t *values)
drm_public int amdgpu_read_mm_registers(amdgpu_device_handle dev,
unsigned dword_offset, unsigned count, uint32_t instance,
uint32_t flags, uint32_t *values)
{
struct drm_amdgpu_info request;
@ -78,8 +78,9 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
sizeof(struct drm_amdgpu_info));
}
int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
uint32_t *count)
drm_public int amdgpu_query_hw_ip_count(amdgpu_device_handle dev,
unsigned type,
uint32_t *count)
{
struct drm_amdgpu_info request;
@ -93,9 +94,9 @@ int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
sizeof(struct drm_amdgpu_info));
}
int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info)
drm_public int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info)
{
struct drm_amdgpu_info request;
@ -110,9 +111,9 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
sizeof(struct drm_amdgpu_info));
}
int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
unsigned ip_instance, unsigned index,
uint32_t *version, uint32_t *feature)
drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev,
unsigned fw_type, unsigned ip_instance, unsigned index,
uint32_t *version, uint32_t *feature)
{
struct drm_amdgpu_info request;
struct drm_amdgpu_info_firmware firmware = {};
@ -136,6 +137,24 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
return 0;
}
drm_public int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev,
unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_uq_fw_areas *info)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)info;
request.return_size = sizeof(*info);
request.query = AMDGPU_INFO_UQ_FW_AREAS;
request.query_hw_ip.type = type;
request.query_hw_ip.ip_instance = ip_instance;
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
{
int r, i;
@ -227,8 +246,8 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
return 0;
}
int amdgpu_query_gpu_info(amdgpu_device_handle dev,
struct amdgpu_gpu_info *info)
drm_public int amdgpu_query_gpu_info(amdgpu_device_handle dev,
struct amdgpu_gpu_info *info)
{
if (!dev || !info)
return -EINVAL;
@ -239,10 +258,10 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev,
return 0;
}
int amdgpu_query_heap_info(amdgpu_device_handle dev,
uint32_t heap,
uint32_t flags,
struct amdgpu_heap_info *info)
drm_public int amdgpu_query_heap_info(amdgpu_device_handle dev,
uint32_t heap,
uint32_t flags,
struct amdgpu_heap_info *info)
{
struct drm_amdgpu_info_vram_gtt vram_gtt_info = {};
int r;
@ -291,8 +310,8 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev,
return 0;
}
int amdgpu_query_gds_info(amdgpu_device_handle dev,
struct amdgpu_gds_resource_info *gds_info)
drm_public int amdgpu_query_gds_info(amdgpu_device_handle dev,
struct amdgpu_gds_resource_info *gds_info)
{
struct drm_amdgpu_info_gds gds_config = {};
int r;
@ -316,8 +335,8 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev,
return 0;
}
int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
unsigned size, void *value)
drm_public int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
unsigned size, void *value)
{
struct drm_amdgpu_info request;
@ -330,3 +349,32 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}
drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = AMDGPU_INFO_VIDEO_CAPS;
request.sensor_info.type = cap_type;
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}
drm_public int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev,
unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = AMDGPU_INFO_GPUVM_FAULT;
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}

View file

@ -32,6 +32,7 @@
#include "xf86atomic.h"
#include "amdgpu.h"
#include "util_double_list.h"
#include "handle_table.h"
#define AMDGPU_CS_MAX_RINGS 8
/* do not use below macro if b is not power of 2 aligned value */
@ -56,15 +57,26 @@ struct amdgpu_bo_va_mgr {
};
struct amdgpu_va {
amdgpu_device_handle dev;
uint64_t address;
uint64_t size;
enum amdgpu_gpu_va_range range;
struct amdgpu_bo_va_mgr *vamgr;
};
struct amdgpu_va_manager {
/** The VA manager for the lower virtual address space */
struct amdgpu_bo_va_mgr vamgr_low;
/** The VA manager for the 32bit address space */
struct amdgpu_bo_va_mgr vamgr_32;
/** The VA manager for the high virtual address space */
struct amdgpu_bo_va_mgr vamgr_high;
/** The VA manager for the 32bit high address space */
struct amdgpu_bo_va_mgr vamgr_high_32;
};
struct amdgpu_device {
atomic_t refcount;
struct amdgpu_device *next;
int fd;
int flink_fd;
unsigned major_version;
@ -72,21 +84,15 @@ struct amdgpu_device {
char *marketing_name;
/** List of buffer handles. Protected by bo_table_mutex. */
struct util_hash_table *bo_handles;
struct handle_table bo_handles;
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
struct util_hash_table *bo_flink_names;
struct handle_table bo_flink_names;
/** This protects all hash tables. */
pthread_mutex_t bo_table_mutex;
struct drm_amdgpu_info_device dev_info;
struct amdgpu_gpu_info info;
/** The VA manager for the lower virtual address space */
struct amdgpu_bo_va_mgr vamgr;
/** The VA manager for the 32bit address space */
struct amdgpu_bo_va_mgr vamgr_32;
/** The VA manager for the high virtual address space */
struct amdgpu_bo_va_mgr vamgr_high;
/** The VA manager for the 32bit high address space */
struct amdgpu_bo_va_mgr vamgr_high_32;
struct amdgpu_va_manager va_mgr;
};
struct amdgpu_bo {
@ -100,7 +106,7 @@ struct amdgpu_bo {
pthread_mutex_t cpu_access_mutex;
void *cpu_ptr;
int cpu_map_count;
int64_t cpu_map_count;
};
struct amdgpu_bo_list {

123
amdgpu/amdgpu_userq.c Normal file
View file

@ -0,0 +1,123 @@
/*
* Copyright 2024 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <string.h>
#include <errno.h>
#include "xf86drm.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
drm_public int
amdgpu_create_userqueue(amdgpu_device_handle dev,
uint32_t ip_type,
uint32_t doorbell_handle,
uint32_t doorbell_offset,
uint64_t queue_va,
uint64_t queue_size,
uint64_t wptr_va,
uint64_t rptr_va,
void *mqd_in,
uint32_t flags,
uint32_t *queue_id)
{
int ret;
union drm_amdgpu_userq userq;
uint64_t mqd_size;
if (!dev)
return -EINVAL;
switch (ip_type) {
case AMDGPU_HW_IP_GFX:
mqd_size = sizeof(struct drm_amdgpu_userq_mqd_gfx11);
break;
case AMDGPU_HW_IP_DMA:
mqd_size = sizeof(struct drm_amdgpu_userq_mqd_sdma_gfx11);
break;
case AMDGPU_HW_IP_COMPUTE:
mqd_size = sizeof(struct drm_amdgpu_userq_mqd_compute_gfx11);
break;
default:
return -EINVAL;
}
memset(&userq, 0, sizeof(userq));
userq.in.op = AMDGPU_USERQ_OP_CREATE;
userq.in.ip_type = ip_type;
userq.in.doorbell_handle = doorbell_handle;
userq.in.doorbell_offset = doorbell_offset;
userq.in.queue_va = queue_va;
userq.in.queue_size = queue_size;
userq.in.wptr_va = wptr_va;
userq.in.rptr_va = rptr_va;
userq.in.mqd = (uint64_t)mqd_in;
userq.in.mqd_size = mqd_size;
userq.in.flags = flags;
ret = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ,
&userq, sizeof(userq));
*queue_id = userq.out.queue_id;
return ret;
}
drm_public int
amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id)
{
union drm_amdgpu_userq userq;
memset(&userq, 0, sizeof(userq));
userq.in.op = AMDGPU_USERQ_OP_FREE;
userq.in.queue_id = queue_id;
return drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ,
&userq, sizeof(userq));
}
drm_public int
amdgpu_userq_signal(amdgpu_device_handle dev,
struct drm_amdgpu_userq_signal *signal_data)
{
int r;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_SIGNAL,
signal_data, sizeof(struct drm_amdgpu_userq_signal));
return r;
}
drm_public int
amdgpu_userq_wait(amdgpu_device_handle dev,
struct drm_amdgpu_userq_wait *wait_data)
{
int r;
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_WAIT,
wait_data, sizeof(struct drm_amdgpu_userq_wait));
return r;
}

View file

@ -29,9 +29,9 @@
#include "amdgpu_internal.h"
#include "util_math.h"
int amdgpu_va_range_query(amdgpu_device_handle dev,
enum amdgpu_gpu_va_range type,
uint64_t *start, uint64_t *end)
drm_public int amdgpu_va_range_query(amdgpu_device_handle dev,
enum amdgpu_gpu_va_range type,
uint64_t *start, uint64_t *end)
{
if (type != amdgpu_gpu_va_range_general)
return -EINVAL;
@ -69,65 +69,99 @@ drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr)
pthread_mutex_destroy(&mgr->bo_va_mutex);
}
static drm_private uint64_t
static drm_private int
amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va,
uint64_t end_va)
{
if (start_va > hole->offset && end_va - hole->offset < hole->size) {
struct amdgpu_bo_va_hole *n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
if (!n)
return -ENOMEM;
n->size = start_va - hole->offset;
n->offset = hole->offset;
list_add(&n->list, &hole->list);
hole->size -= (end_va - hole->offset);
hole->offset = end_va;
} else if (start_va > hole->offset) {
hole->size = start_va - hole->offset;
} else if (end_va - hole->offset < hole->size) {
hole->size -= (end_va - hole->offset);
hole->offset = end_va;
} else {
list_del(&hole->list);
free(hole);
}
return 0;
}
static drm_private int
amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
uint64_t alignment, uint64_t base_required)
uint64_t alignment, uint64_t base_required,
bool search_from_top, uint64_t *va_out)
{
struct amdgpu_bo_va_hole *hole, *n;
uint64_t offset = 0, waste = 0;
uint64_t offset = 0;
int ret;
alignment = MAX2(alignment, mgr->va_alignment);
size = ALIGN(size, mgr->va_alignment);
if (base_required % alignment)
return AMDGPU_INVALID_VA_ADDRESS;
return -EINVAL;
pthread_mutex_lock(&mgr->bo_va_mutex);
LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
if (base_required) {
if (hole->offset > base_required ||
(hole->offset + hole->size) < (base_required + size))
continue;
waste = base_required - hole->offset;
offset = base_required;
} else {
offset = hole->offset;
waste = offset % alignment;
waste = waste ? alignment - waste : 0;
offset += waste;
if (offset >= (hole->offset + hole->size)) {
continue;
if (!search_from_top) {
LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
if (base_required) {
if (hole->offset > base_required ||
(hole->offset + hole->size) < (base_required + size))
continue;
offset = base_required;
} else {
uint64_t waste = hole->offset % alignment;
waste = waste ? alignment - waste : 0;
offset = hole->offset + waste;
if (offset >= (hole->offset + hole->size) ||
size > (hole->offset + hole->size) - offset) {
continue;
}
}
}
if (!waste && hole->size == size) {
offset = hole->offset;
list_del(&hole->list);
free(hole);
ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
pthread_mutex_unlock(&mgr->bo_va_mutex);
return offset;
*va_out = offset;
return ret;
}
if ((hole->size - waste) > size) {
if (waste) {
n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
n->size = waste;
n->offset = hole->offset;
list_add(&n->list, &hole->list);
} else {
LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
if (base_required) {
if (hole->offset > base_required ||
(hole->offset + hole->size) < (base_required + size))
continue;
offset = base_required;
} else {
if (size > hole->size)
continue;
offset = hole->offset + hole->size - size;
offset -= offset % alignment;
if (offset < hole->offset) {
continue;
}
}
hole->size -= (size + waste);
hole->offset += size + waste;
ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
pthread_mutex_unlock(&mgr->bo_va_mutex);
return offset;
}
if ((hole->size - waste) == size) {
hole->size = waste;
pthread_mutex_unlock(&mgr->bo_va_mutex);
return offset;
*va_out = offset;
return ret;
}
}
pthread_mutex_unlock(&mgr->bo_va_mutex);
return AMDGPU_INVALID_VA_ADDRESS;
return -ENOMEM;
}
static drm_private void
@ -186,71 +220,86 @@ out:
pthread_mutex_unlock(&mgr->bo_va_mutex);
}
int amdgpu_va_range_alloc(amdgpu_device_handle dev,
enum amdgpu_gpu_va_range va_range_type,
uint64_t size,
uint64_t va_base_alignment,
uint64_t va_base_required,
uint64_t *va_base_allocated,
amdgpu_va_handle *va_range_handle,
uint64_t flags)
drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev,
enum amdgpu_gpu_va_range va_range_type,
uint64_t size,
uint64_t va_base_alignment,
uint64_t va_base_required,
uint64_t *va_base_allocated,
amdgpu_va_handle *va_range_handle,
uint64_t flags)
{
return amdgpu_va_range_alloc2(&dev->va_mgr, va_range_type, size,
va_base_alignment, va_base_required,
va_base_allocated, va_range_handle,
flags);
}
drm_public int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
enum amdgpu_gpu_va_range va_range_type,
uint64_t size,
uint64_t va_base_alignment,
uint64_t va_base_required,
uint64_t *va_base_allocated,
amdgpu_va_handle *va_range_handle,
uint64_t flags)
{
struct amdgpu_bo_va_mgr *vamgr;
bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE);
int ret;
/* Clear the flag when the high VA manager is not initialized */
if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max)
if (flags & AMDGPU_VA_RANGE_HIGH && !va_mgr->vamgr_high_32.va_max)
flags &= ~AMDGPU_VA_RANGE_HIGH;
if (flags & AMDGPU_VA_RANGE_HIGH) {
if (flags & AMDGPU_VA_RANGE_32_BIT)
vamgr = &dev->vamgr_high_32;
vamgr = &va_mgr->vamgr_high_32;
else
vamgr = &dev->vamgr_high;
vamgr = &va_mgr->vamgr_high;
} else {
if (flags & AMDGPU_VA_RANGE_32_BIT)
vamgr = &dev->vamgr_32;
vamgr = &va_mgr->vamgr_32;
else
vamgr = &dev->vamgr;
vamgr = &va_mgr->vamgr_low;
}
va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment);
size = ALIGN(size, vamgr->va_alignment);
*va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
va_base_alignment, va_base_required);
ret = amdgpu_vamgr_find_va(vamgr, size,
va_base_alignment, va_base_required,
search_from_top, va_base_allocated);
if (!(flags & AMDGPU_VA_RANGE_32_BIT) &&
(*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) {
if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) {
/* fallback to 32bit address */
if (flags & AMDGPU_VA_RANGE_HIGH)
vamgr = &dev->vamgr_high_32;
vamgr = &va_mgr->vamgr_high_32;
else
vamgr = &dev->vamgr_32;
*va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
va_base_alignment, va_base_required);
vamgr = &va_mgr->vamgr_32;
ret = amdgpu_vamgr_find_va(vamgr, size,
va_base_alignment, va_base_required,
search_from_top, va_base_allocated);
}
if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) {
if (!ret) {
struct amdgpu_va* va;
va = calloc(1, sizeof(struct amdgpu_va));
if(!va){
amdgpu_vamgr_free_va(vamgr, *va_base_allocated, size);
return -ENOMEM;
}
va->dev = dev;
va->address = *va_base_allocated;
va->size = size;
va->range = va_range_type;
va->vamgr = vamgr;
*va_range_handle = va;
} else {
return -EINVAL;
}
return 0;
return ret;
}
int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
{
if(!va_range_handle || !va_range_handle->address)
return 0;
@ -261,3 +310,50 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
free(va_range_handle);
return 0;
}
drm_public uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle)
{
return va_handle->address;
}
drm_public amdgpu_va_manager_handle amdgpu_va_manager_alloc(void)
{
amdgpu_va_manager_handle r = calloc(1, sizeof(struct amdgpu_va_manager));
return r;
}
drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
uint64_t low_va_offset, uint64_t low_va_max,
uint64_t high_va_offset, uint64_t high_va_max,
uint32_t virtual_address_alignment)
{
uint64_t start, max;
start = low_va_offset;
max = MIN2(low_va_max, 0x100000000ULL);
amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max,
virtual_address_alignment);
start = max;
max = MAX2(low_va_max, 0x100000000ULL);
amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max,
virtual_address_alignment);
start = high_va_offset;
max = MIN2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
amdgpu_vamgr_init(&va_mgr->vamgr_high_32, start, max,
virtual_address_alignment);
start = max;
max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max,
virtual_address_alignment);
}
drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr)
{
amdgpu_vamgr_deinit(&va_mgr->vamgr_32);
amdgpu_vamgr_deinit(&va_mgr->vamgr_low);
amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32);
amdgpu_vamgr_deinit(&va_mgr->vamgr_high);
}

View file

@ -26,7 +26,7 @@
#include "xf86drm.h"
#include "amdgpu_internal.h"
int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags)
drm_public int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags)
{
union drm_amdgpu_vm vm;
@ -37,7 +37,8 @@ int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags)
&vm, sizeof(vm));
}
int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags)
drm_public int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev,
uint32_t flags)
{
union drm_amdgpu_vm vm;

72
amdgpu/handle_table.c Normal file
View file

@ -0,0 +1,72 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
#include "handle_table.h"
#include "util_math.h"
drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
void *value)
{
if (key >= table->max_key) {
uint32_t alignment = sysconf(_SC_PAGESIZE) / sizeof(void*);
uint32_t max_key = ALIGN(key + 1, alignment);
void **values;
values = realloc(table->values, max_key * sizeof(void *));
if (!values)
return -ENOMEM;
memset(values + table->max_key, 0, (max_key - table->max_key) *
sizeof(void *));
table->max_key = max_key;
table->values = values;
}
table->values[key] = value;
return 0;
}
drm_private void handle_table_remove(struct handle_table *table, uint32_t key)
{
if (key < table->max_key)
table->values[key] = NULL;
}
drm_private void *handle_table_lookup(struct handle_table *table, uint32_t key)
{
if (key < table->max_key)
return table->values[key];
else
return NULL;
}
drm_private void handle_table_fini(struct handle_table *table)
{
free(table->values);
table->max_key = 0;
table->values = NULL;
}

41
amdgpu/handle_table.h Normal file
View file

@ -0,0 +1,41 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _HANDLE_TABLE_H_
#define _HANDLE_TABLE_H_
#include <stdint.h>
#include "libdrm_macros.h"
struct handle_table {
uint32_t max_key;
void **values;
};
drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
void *value);
drm_private void handle_table_remove(struct handle_table *table, uint32_t key);
drm_private void *handle_table_lookup(struct handle_table *table, uint32_t key);
drm_private void handle_table_fini(struct handle_table *table);
#endif /* _HANDLE_TABLE_H_ */

View file

@ -21,35 +21,33 @@
datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm')
libdrm_amdgpu = shared_library(
libdrm_amdgpu = library(
'drm_amdgpu',
[
files(
'amdgpu_asic_id.c', 'amdgpu_bo.c', 'amdgpu_cs.c', 'amdgpu_device.c',
'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'util_hash.c',
'util_hash_table.c',
'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'handle_table.c',
'amdgpu_userq.c',
),
config_file,
],
c_args : [
warn_c_args,
libdrm_c_args,
'-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(join_paths(datadir_amdgpu, 'amdgpu.ids')),
],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs, dep_atomic_ops],
version : '1.0.0',
dependencies : [dep_threads, dep_atomic_ops, dep_rt],
version : '1.@0@.0'.format(patch_ver),
install : true,
)
install_headers('amdgpu.h', subdir : 'libdrm')
pkg.generate(
libdrm_amdgpu,
name : 'libdrm_amdgpu',
libraries : libdrm_amdgpu,
subdirs : ['.', 'libdrm'],
version : meson.project_version(),
requires_private : 'libdrm',
description : 'Userspace interface to kernel DRM services for amdgpu',
)
@ -58,9 +56,14 @@ ext_libdrm_amdgpu = declare_dependency(
include_directories : [inc_drm, include_directories('.')],
)
meson.override_dependency('libdrm_amdgpu', ext_libdrm_amdgpu)
test(
'amdgpu-symbol-check',
prog_bash,
env : env_test,
args : [files('amdgpu-symbol-check'), libdrm_amdgpu]
'amdgpu-symbols-check',
symbols_check,
args : [
'--lib', libdrm_amdgpu,
'--symbols-file', files('amdgpu-symbols.txt'),
'--nm', prog_nm.full_path(),
],
)

View file

@ -1,383 +0,0 @@
/**************************************************************************
*
* Copyright 2007 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/*
* Authors:
* Zack Rusin <zackr@vmware.com>
*/
#include "util_hash.h"
#include <stdlib.h>
#include <assert.h>
#define MAX(a, b) ((a > b) ? (a) : (b))
static const int MinNumBits = 4;
static const unsigned char prime_deltas[] = {
0, 0, 1, 3, 1, 5, 3, 3, 1, 9, 7, 5, 3, 9, 25, 3,
1, 21, 3, 21, 7, 15, 9, 5, 3, 29, 15, 0, 0, 0, 0, 0
};
static int primeForNumBits(int numBits)
{
return (1 << numBits) + prime_deltas[numBits];
}
/* Returns the smallest integer n such that
primeForNumBits(n) >= hint.
*/
static int countBits(int hint)
{
int numBits = 0;
int bits = hint;
while (bits > 1) {
bits >>= 1;
numBits++;
}
if (numBits >= (int)sizeof(prime_deltas)) {
numBits = sizeof(prime_deltas) - 1;
} else if (primeForNumBits(numBits) < hint) {
++numBits;
}
return numBits;
}
struct util_node {
struct util_node *next;
unsigned key;
void *value;
};
struct util_hash_data {
struct util_node *fakeNext;
struct util_node **buckets;
int size;
int nodeSize;
short userNumBits;
short numBits;
int numBuckets;
};
struct util_hash {
union {
struct util_hash_data *d;
struct util_node *e;
} data;
};
static void *util_data_allocate_node(struct util_hash_data *hash)
{
return malloc(hash->nodeSize);
}
static void util_free_node(struct util_node *node)
{
free(node);
}
static struct util_node *
util_hash_create_node(struct util_hash *hash,
unsigned akey, void *avalue,
struct util_node **anextNode)
{
struct util_node *node = util_data_allocate_node(hash->data.d);
if (!node)
return NULL;
node->key = akey;
node->value = avalue;
node->next = (struct util_node*)(*anextNode);
*anextNode = node;
++hash->data.d->size;
return node;
}
static void util_data_rehash(struct util_hash_data *hash, int hint)
{
if (hint < 0) {
hint = countBits(-hint);
if (hint < MinNumBits)
hint = MinNumBits;
hash->userNumBits = (short)hint;
while (primeForNumBits(hint) < (hash->size >> 1))
++hint;
} else if (hint < MinNumBits) {
hint = MinNumBits;
}
if (hash->numBits != hint) {
struct util_node *e = (struct util_node *)(hash);
struct util_node **oldBuckets = hash->buckets;
int oldNumBuckets = hash->numBuckets;
int i = 0;
hash->numBits = (short)hint;
hash->numBuckets = primeForNumBits(hint);
hash->buckets = malloc(sizeof(struct util_node*) * hash->numBuckets);
for (i = 0; i < hash->numBuckets; ++i)
hash->buckets[i] = e;
for (i = 0; i < oldNumBuckets; ++i) {
struct util_node *firstNode = oldBuckets[i];
while (firstNode != e) {
unsigned h = firstNode->key;
struct util_node *lastNode = firstNode;
struct util_node *afterLastNode;
struct util_node **beforeFirstNode;
while (lastNode->next != e && lastNode->next->key == h)
lastNode = lastNode->next;
afterLastNode = lastNode->next;
beforeFirstNode = &hash->buckets[h % hash->numBuckets];
while (*beforeFirstNode != e)
beforeFirstNode = &(*beforeFirstNode)->next;
lastNode->next = *beforeFirstNode;
*beforeFirstNode = firstNode;
firstNode = afterLastNode;
}
}
free(oldBuckets);
}
}
static void util_data_might_grow(struct util_hash_data *hash)
{
if (hash->size >= hash->numBuckets)
util_data_rehash(hash, hash->numBits + 1);
}
static void util_data_has_shrunk(struct util_hash_data *hash)
{
if (hash->size <= (hash->numBuckets >> 3) &&
hash->numBits > hash->userNumBits) {
int max = MAX(hash->numBits-2, hash->userNumBits);
util_data_rehash(hash, max);
}
}
static struct util_node *util_data_first_node(struct util_hash_data *hash)
{
struct util_node *e = (struct util_node *)(hash);
struct util_node **bucket = hash->buckets;
int n = hash->numBuckets;
while (n--) {
if (*bucket != e)
return *bucket;
++bucket;
}
return e;
}
static struct util_node **util_hash_find_node(struct util_hash *hash, unsigned akey)
{
struct util_node **node;
if (hash->data.d->numBuckets) {
node = (struct util_node **)(&hash->data.d->buckets[akey % hash->data.d->numBuckets]);
assert(*node == hash->data.e || (*node)->next);
while (*node != hash->data.e && (*node)->key != akey)
node = &(*node)->next;
} else {
node = (struct util_node **)((const struct util_node * const *)(&hash->data.e));
}
return node;
}
drm_private struct util_hash_iter
util_hash_insert(struct util_hash *hash, unsigned key, void *data)
{
util_data_might_grow(hash->data.d);
{
struct util_node **nextNode = util_hash_find_node(hash, key);
struct util_node *node = util_hash_create_node(hash, key, data, nextNode);
if (!node) {
struct util_hash_iter null_iter = {hash, 0};
return null_iter;
}
{
struct util_hash_iter iter = {hash, node};
return iter;
}
}
}
drm_private struct util_hash *util_hash_create(void)
{
struct util_hash *hash = malloc(sizeof(struct util_hash));
if (!hash)
return NULL;
hash->data.d = malloc(sizeof(struct util_hash_data));
if (!hash->data.d) {
free(hash);
return NULL;
}
hash->data.d->fakeNext = 0;
hash->data.d->buckets = 0;
hash->data.d->size = 0;
hash->data.d->nodeSize = sizeof(struct util_node);
hash->data.d->userNumBits = (short)MinNumBits;
hash->data.d->numBits = 0;
hash->data.d->numBuckets = 0;
return hash;
}
drm_private void util_hash_delete(struct util_hash *hash)
{
struct util_node *e_for_x = (struct util_node *)(hash->data.d);
struct util_node **bucket = (struct util_node **)(hash->data.d->buckets);
int n = hash->data.d->numBuckets;
while (n--) {
struct util_node *cur = *bucket++;
while (cur != e_for_x) {
struct util_node *next = cur->next;
util_free_node(cur);
cur = next;
}
}
free(hash->data.d->buckets);
free(hash->data.d);
free(hash);
}
drm_private struct util_hash_iter
util_hash_find(struct util_hash *hash, unsigned key)
{
struct util_node **nextNode = util_hash_find_node(hash, key);
struct util_hash_iter iter = {hash, *nextNode};
return iter;
}
drm_private unsigned util_hash_iter_key(struct util_hash_iter iter)
{
if (!iter.node || iter.hash->data.e == iter.node)
return 0;
return iter.node->key;
}
drm_private void *util_hash_iter_data(struct util_hash_iter iter)
{
if (!iter.node || iter.hash->data.e == iter.node)
return 0;
return iter.node->value;
}
static struct util_node *util_hash_data_next(struct util_node *node)
{
union {
struct util_node *next;
struct util_node *e;
struct util_hash_data *d;
} a;
int start;
struct util_node **bucket;
int n;
a.next = node->next;
if (!a.next) {
/* iterating beyond the last element */
return 0;
}
if (a.next->next)
return a.next;
start = (node->key % a.d->numBuckets) + 1;
bucket = a.d->buckets + start;
n = a.d->numBuckets - start;
while (n--) {
if (*bucket != a.e)
return *bucket;
++bucket;
}
return a.e;
}
drm_private struct util_hash_iter
util_hash_iter_next(struct util_hash_iter iter)
{
struct util_hash_iter next = {iter.hash, util_hash_data_next(iter.node)};
return next;
}
drm_private int util_hash_iter_is_null(struct util_hash_iter iter)
{
if (!iter.node || iter.node == iter.hash->data.e)
return 1;
return 0;
}
drm_private void *util_hash_take(struct util_hash *hash, unsigned akey)
{
struct util_node **node = util_hash_find_node(hash, akey);
if (*node != hash->data.e) {
void *t = (*node)->value;
struct util_node *next = (*node)->next;
util_free_node(*node);
*node = next;
--hash->data.d->size;
util_data_has_shrunk(hash->data.d);
return t;
}
return 0;
}
drm_private struct util_hash_iter util_hash_first_node(struct util_hash *hash)
{
struct util_hash_iter iter = {hash, util_data_first_node(hash->data.d)};
return iter;
}
drm_private struct util_hash_iter
util_hash_erase(struct util_hash *hash, struct util_hash_iter iter)
{
struct util_hash_iter ret = iter;
struct util_node *node = iter.node;
struct util_node **node_ptr;
if (node == hash->data.e)
return iter;
ret = util_hash_iter_next(ret);
node_ptr = (struct util_node**)(&hash->data.d->buckets[node->key % hash->data.d->numBuckets]);
while (*node_ptr != node)
node_ptr = &(*node_ptr)->next;
*node_ptr = node->next;
util_free_node(node);
--hash->data.d->size;
return ret;
}

View file

@ -1,103 +0,0 @@
/**************************************************************************
*
* Copyright 2007 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* @file
* Hash implementation.
*
* This file provides a hash implementation that is capable of dealing
* with collisions. It stores colliding entries in linked list. All
* functions operating on the hash return an iterator. The iterator
* itself points to the collision list. If there wasn't any collision
* the list will have just one entry, otherwise client code should
* iterate over the entries to find the exact entry among ones that
* had the same key (e.g. memcmp could be used on the data to check
* that)
*
* @author Zack Rusin <zackr@vmware.com>
*/
#ifndef UTIL_HASH_H
#define UTIL_HASH_H
#include <stdbool.h>
#include "libdrm_macros.h"
struct util_hash;
struct util_node;
struct util_hash_iter {
struct util_hash *hash;
struct util_node *node;
};
drm_private struct util_hash *util_hash_create(void);
drm_private void util_hash_delete(struct util_hash *hash);
/**
* Adds a data with the given key to the hash. If entry with the given
* key is already in the hash, this current entry is instered before it
* in the collision list.
* Function returns iterator pointing to the inserted item in the hash.
*/
drm_private struct util_hash_iter
util_hash_insert(struct util_hash *hash, unsigned key, void *data);
/**
* Removes the item pointed to by the current iterator from the hash.
* Note that the data itself is not erased and if it was a malloc'ed pointer
* it will have to be freed after calling this function by the callee.
* Function returns iterator pointing to the item after the removed one in
* the hash.
*/
drm_private struct util_hash_iter
util_hash_erase(struct util_hash *hash, struct util_hash_iter iter);
drm_private void *util_hash_take(struct util_hash *hash, unsigned key);
drm_private struct util_hash_iter util_hash_first_node(struct util_hash *hash);
/**
* Return an iterator pointing to the first entry in the collision list.
*/
drm_private struct util_hash_iter
util_hash_find(struct util_hash *hash, unsigned key);
drm_private int util_hash_iter_is_null(struct util_hash_iter iter);
drm_private unsigned util_hash_iter_key(struct util_hash_iter iter);
drm_private void *util_hash_iter_data(struct util_hash_iter iter);
drm_private struct util_hash_iter
util_hash_iter_next(struct util_hash_iter iter);
#endif

View file

@ -1,270 +0,0 @@
/**************************************************************************
*
* Copyright 2008 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* @file
* General purpose hash table implementation.
*
* Just uses the util_hash for now, but it might be better switch to a linear
* probing hash table implementation at some point -- as it is said they have
* better lookup and cache performance and it appears to be possible to write
* a lock-free implementation of such hash tables .
*
* @author José Fonseca <jfonseca@vmware.com>
*/
#include "util_hash_table.h"
#include "util_hash.h"
#include <stdlib.h>
#include <assert.h>
struct util_hash_table
{
struct util_hash *head;
/** Hash function */
unsigned (*make_hash)(void *key);
/** Compare two keys */
int (*compare)(void *key1, void *key2);
};
struct util_hash_table_item
{
void *key;
void *value;
};
static struct util_hash_table_item *
util_hash_table_item(struct util_hash_iter iter)
{
return (struct util_hash_table_item *)util_hash_iter_data(iter);
}
drm_private struct util_hash_table *
util_hash_table_create(unsigned (*hash)(void *key),
int (*compare)(void *key1, void *key2))
{
struct util_hash_table *ht;
ht = malloc(sizeof(struct util_hash_table));
if(!ht)
return NULL;
ht->head = util_hash_create();
if(!ht->head) {
free(ht);
return NULL;
}
ht->make_hash = hash;
ht->compare = compare;
return ht;
}
static struct util_hash_iter
util_hash_table_find_iter(struct util_hash_table *ht,
void *key, unsigned key_hash)
{
struct util_hash_iter iter;
struct util_hash_table_item *item;
iter = util_hash_find(ht->head, key_hash);
while (!util_hash_iter_is_null(iter)) {
item = (struct util_hash_table_item *)util_hash_iter_data(iter);
if (!ht->compare(item->key, key))
break;
iter = util_hash_iter_next(iter);
}
return iter;
}
static struct util_hash_table_item *
util_hash_table_find_item(struct util_hash_table *ht,
void *key, unsigned key_hash)
{
struct util_hash_iter iter;
struct util_hash_table_item *item;
iter = util_hash_find(ht->head, key_hash);
while (!util_hash_iter_is_null(iter)) {
item = (struct util_hash_table_item *)util_hash_iter_data(iter);
if (!ht->compare(item->key, key))
return item;
iter = util_hash_iter_next(iter);
}
return NULL;
}
drm_private void
util_hash_table_set(struct util_hash_table *ht, void *key, void *value)
{
unsigned key_hash;
struct util_hash_table_item *item;
struct util_hash_iter iter;
assert(ht);
if (!ht)
return;
key_hash = ht->make_hash(key);
item = util_hash_table_find_item(ht, key, key_hash);
if(item) {
/* TODO: key/value destruction? */
item->value = value;
return;
}
item = malloc(sizeof(struct util_hash_table_item));
if(!item)
return;
item->key = key;
item->value = value;
iter = util_hash_insert(ht->head, key_hash, item);
if(util_hash_iter_is_null(iter)) {
free(item);
return;
}
}
drm_private void *util_hash_table_get(struct util_hash_table *ht, void *key)
{
unsigned key_hash;
struct util_hash_table_item *item;
assert(ht);
if (!ht)
return NULL;
key_hash = ht->make_hash(key);
item = util_hash_table_find_item(ht, key, key_hash);
if(!item)
return NULL;
return item->value;
}
drm_private void util_hash_table_remove(struct util_hash_table *ht, void *key)
{
unsigned key_hash;
struct util_hash_iter iter;
struct util_hash_table_item *item;
assert(ht);
if (!ht)
return;
key_hash = ht->make_hash(key);
iter = util_hash_table_find_iter(ht, key, key_hash);
if(util_hash_iter_is_null(iter))
return;
item = util_hash_table_item(iter);
assert(item);
free(item);
util_hash_erase(ht->head, iter);
}
drm_private void util_hash_table_clear(struct util_hash_table *ht)
{
struct util_hash_iter iter;
struct util_hash_table_item *item;
assert(ht);
if (!ht)
return;
iter = util_hash_first_node(ht->head);
while (!util_hash_iter_is_null(iter)) {
item = (struct util_hash_table_item *)util_hash_take(ht->head, util_hash_iter_key(iter));
free(item);
iter = util_hash_first_node(ht->head);
}
}
drm_private void util_hash_table_foreach(struct util_hash_table *ht,
void (*callback)(void *key, void *value, void *data),
void *data)
{
struct util_hash_iter iter;
struct util_hash_table_item *item;
assert(ht);
if (!ht)
return;
iter = util_hash_first_node(ht->head);
while (!util_hash_iter_is_null(iter)) {
item = (struct util_hash_table_item *)util_hash_iter_data(iter);
callback(item->key, item->value, data);
iter = util_hash_iter_next(iter);
}
}
static void util_hash_table_inc(void *k, void *v, void *d)
{
++*(size_t *)d;
}
drm_private size_t util_hash_table_count(struct util_hash_table *ht)
{
size_t count = 0;
util_hash_table_foreach(ht, util_hash_table_inc, &count);
return count;
}
drm_private void util_hash_table_destroy(struct util_hash_table *ht)
{
struct util_hash_iter iter;
struct util_hash_table_item *item;
assert(ht);
if (!ht)
return;
iter = util_hash_first_node(ht->head);
while (!util_hash_iter_is_null(iter)) {
item = (struct util_hash_table_item *)util_hash_iter_data(iter);
free(item);
iter = util_hash_iter_next(iter);
}
util_hash_delete(ht->head);
free(ht);
}

View file

@ -1,71 +0,0 @@
/**************************************************************************
*
* Copyright 2008 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* General purpose hash table.
*
* @author José Fonseca <jfonseca@vmware.com>
*/
#ifndef U_HASH_TABLE_H_
#define U_HASH_TABLE_H_
#include "libdrm_macros.h"
/**
* Generic purpose hash table.
*/
struct util_hash_table;
/**
* Create an hash table.
*
* @param hash hash function
* @param compare should return 0 for two equal keys.
*/
drm_private struct util_hash_table *
util_hash_table_create(unsigned (*hash)(void *key),
int (*compare)(void *key1, void *key2));
drm_private void
util_hash_table_set(struct util_hash_table *ht, void *key, void *value);
drm_private void *util_hash_table_get(struct util_hash_table *ht, void *key);
drm_private void util_hash_table_remove(struct util_hash_table *ht, void *key);
drm_private void util_hash_table_clear(struct util_hash_table *ht);
drm_private void util_hash_table_foreach(struct util_hash_table *ht,
void (*callback)(void *key, void *value, void *data),
void *data);
drm_private size_t util_hash_table_count(struct util_hash_table *ht);
drm_private void util_hash_table_destroy(struct util_hash_table *ht);
#endif /* U_HASH_TABLE_H_ */

View file

@ -60,16 +60,16 @@ struct gralloc_handle_t {
uint32_t usage; /* android libhardware usage flags */
uint32_t stride; /* the stride in bytes */
uint64_t modifier; /* buffer modifiers */
int data_owner; /* owner of data (for validation) */
uint64_t modifier __attribute__((aligned(8))); /* buffer modifiers */
union {
void *data; /* pointer to struct gralloc_gbm_bo_t */
uint64_t reserved;
} __attribute__((aligned(8)));
};
#define GRALLOC_HANDLE_VERSION 3
#define GRALLOC_HANDLE_VERSION 4
#define GRALLOC_HANDLE_MAGIC 0x60585350
#define GRALLOC_HANDLE_NUM_FDS 1
#define GRALLOC_HANDLE_NUM_INTS ( \

View file

@ -1,20 +0,0 @@
#! /bin/sh
srcdir=`dirname "$0"`
test -z "$srcdir" && srcdir=.
ORIGDIR=`pwd`
cd "$srcdir"
git config --local --get format.subjectPrefix >/dev/null ||
git config --local format.subjectPrefix "PATCH libdrm" 2>/dev/null
git config --local --get sendemail.to >/dev/null ||
git config --local sendemail.to "dri-devel@lists.freedesktop.org" 2>/dev/null
autoreconf --force --verbose --install || exit 1
cd "$ORIGDIR" || exit $?
if test -z "$NOCONFIGURE"; then
"$srcdir"/configure "$@"
fi

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@ -1,605 +0,0 @@
# Copyright 2005 Adam Jackson.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# on the rights to use, copy, modify, merge, publish, distribute, sub
# license, and/or sell copies of the Software, and to permit persons to whom
# the Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
AC_PREREQ([2.63])
AC_INIT([libdrm],
[2.4.93],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
AC_CONFIG_HEADERS([config.h])
AC_CONFIG_SRCDIR([Makefile.am])
AC_CONFIG_MACRO_DIR([m4])
AC_CONFIG_AUX_DIR([build-aux])
PKG_PROG_PKG_CONFIG
# Require xorg-macros minimum of 1.12 for XORG_WITH_XSLTPROC
m4_ifndef([XORG_MACROS_VERSION],
[m4_fatal([must install xorg-macros 1.12 or later before running autoconf/autogen])])
XORG_MACROS_VERSION(1.12)
XORG_WITH_XSLTPROC
XORG_MANPAGE_SECTIONS
AM_INIT_AUTOMAKE([1.10 foreign dist-bzip2])
# Enable quiet compiles on automake 1.11.
m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
# Check for programs
AC_PROG_CC
AC_PROG_CC_C99
AC_PROG_NM
if test "x$ac_cv_prog_cc_c99" = xno; then
AC_MSG_ERROR([Building libdrm requires C99 enabled compiler])
fi
AC_USE_SYSTEM_EXTENSIONS
AC_SYS_LARGEFILE
AC_FUNC_ALLOCA
save_CFLAGS="$CFLAGS"
export CFLAGS="$CFLAGS -Werror"
AC_HEADER_MAJOR
CFLAGS="$save_CFLAGS"
AC_CHECK_HEADERS([sys/sysctl.h sys/select.h])
# Initialize libtool
LT_PREREQ([2.2])
LT_INIT([disable-static])
dnl pthread-stubs is mandatory on some BSD platforms, due to the nature of the
dnl project. Even then there's a notable issue as described in the project README
case "$host_os" in
linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu* | openbsd*)
pthread_stubs_possible="no"
;;
* )
pthread_stubs_possible="yes"
;;
esac
if test "x$pthread_stubs_possible" = xyes; then
PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs >= 0.4)
AC_SUBST(PTHREADSTUBS_CFLAGS)
AC_SUBST(PTHREADSTUBS_LIBS)
fi
pkgconfigdir=${libdir}/pkgconfig
AC_SUBST(pkgconfigdir)
libdrmdatadir=${datadir}/libdrm
AC_SUBST(libdrmdatadir)
AC_ARG_ENABLE([udev],
[AS_HELP_STRING([--enable-udev],
[Enable support for using udev instead of mknod (default: disabled)])],
[UDEV=$enableval], [UDEV=no])
AC_ARG_ENABLE(libkms,
AS_HELP_STRING([--disable-libkms],
[Disable KMS mm abstraction library (default: auto, enabled on supported platforms)]),
[LIBKMS=$enableval], [LIBKMS=auto])
AC_ARG_ENABLE(intel,
AS_HELP_STRING([--disable-intel],
[Enable support for intel's KMS API (default: auto, enabled on x86)]),
[INTEL=$enableval], [INTEL=auto])
AC_ARG_ENABLE(radeon,
AS_HELP_STRING([--disable-radeon],
[Enable support for radeon's KMS API (default: auto)]),
[RADEON=$enableval], [RADEON=auto])
AC_ARG_ENABLE(amdgpu,
AS_HELP_STRING([--disable-amdgpu],
[Enable support for amdgpu's KMS API (default: auto)]),
[AMDGPU=$enableval], [AMDGPU=auto])
AC_ARG_ENABLE(nouveau,
AS_HELP_STRING([--disable-nouveau],
[Enable support for nouveau's KMS API (default: auto)]),
[NOUVEAU=$enableval], [NOUVEAU=auto])
AC_ARG_ENABLE(vmwgfx,
AS_HELP_STRING([--disable-vmwgfx],
[Enable support for vmwgfx's KMS API (default: yes)]),
[VMWGFX=$enableval], [VMWGFX=yes])
AC_ARG_ENABLE(omap-experimental-api,
AS_HELP_STRING([--enable-omap-experimental-api],
[Enable support for OMAP's experimental API (default: disabled)]),
[OMAP=$enableval], [OMAP=no])
AC_ARG_ENABLE(exynos-experimental-api,
AS_HELP_STRING([--enable-exynos-experimental-api],
[Enable support for EXYNOS's experimental API (default: disabled)]),
[EXYNOS=$enableval], [EXYNOS=no])
AC_ARG_ENABLE(freedreno,
AS_HELP_STRING([--disable-freedreno],
[Enable support for freedreno's KMS API (default: auto, enabled on arm)]),
[FREEDRENO=$enableval], [FREEDRENO=auto])
AC_ARG_ENABLE(freedreno-kgsl,
AS_HELP_STRING([--enable-freedreno-kgsl],
[Enable support for freedreno's to use downstream android kernel API (default: disabled)]),
[FREEDRENO_KGSL=$enableval], [FREEDRENO_KGSL=no])
AC_ARG_ENABLE(tegra-experimental-api,
AS_HELP_STRING([--enable-tegra-experimental-api],
[Enable support for Tegra's experimental API (default: disabled)]),
[TEGRA=$enableval], [TEGRA=no])
AC_ARG_ENABLE(vc4,
AS_HELP_STRING([--disable-vc4],
[Enable support for vc4's API (default: auto, enabled on arm)]),
[VC4=$enableval], [VC4=auto])
AC_ARG_ENABLE(etnaviv-experimental-api,
AS_HELP_STRING([--enable-etnaviv-experimental-api],
[Enable support for etnaviv's experimental API (default: disabled)]),
[ETNAVIV=$enableval], [ETNAVIV=no])
AC_ARG_ENABLE(install-test-programs,
AS_HELP_STRING([--enable-install-test-programs],
[Install test programs (default: no)]),
[INSTALL_TESTS=$enableval], [INSTALL_TESTS=no])
dnl ===========================================================================
dnl check compiler flags
AC_DEFUN([LIBDRM_CC_TRY_FLAG], [
AC_MSG_CHECKING([whether $CC supports $1])
libdrm_save_CFLAGS="$CFLAGS"
CFLAGS="$CFLAGS $1"
AC_COMPILE_IFELSE([AC_LANG_SOURCE([ ])], [libdrm_cc_flag=yes], [libdrm_cc_flag=no])
CFLAGS="$libdrm_save_CFLAGS"
if test "x$libdrm_cc_flag" = "xyes"; then
ifelse([$2], , :, [$2])
else
ifelse([$3], , :, [$3])
fi
AC_MSG_RESULT([$libdrm_cc_flag])
])
dnl We use clock_gettime to check for timeouts in drmWaitVBlank
AC_CHECK_FUNCS([clock_gettime], [CLOCK_LIB=],
[AC_CHECK_LIB([rt], [clock_gettime], [CLOCK_LIB=-lrt],
[AC_MSG_ERROR([Couldn't find clock_gettime])])])
AC_SUBST([CLOCK_LIB])
AC_CHECK_FUNCS([open_memstream],
[AC_DEFINE([HAVE_OPEN_MEMSTREAM], 1, [Have open_memstream()])],
[AC_DEFINE([HAVE_OPEN_MEMSTREAM], 0)])
dnl Use lots of warning flags with with gcc and compatible compilers
dnl Note: if you change the following variable, the cache is automatically
dnl skipped and all flags rechecked. So there's no need to do anything
dnl else. If for any reason you need to force a recheck, just change
dnl MAYBE_WARN in an ignorable way (like adding whitespace)
MAYBE_WARN="-Wall -Wextra -Werror=undef \
-Wsign-compare -Werror-implicit-function-declaration \
-Wpointer-arith -Wwrite-strings -Wstrict-prototypes \
-Wmissing-prototypes -Wmissing-declarations -Wnested-externs \
-Wpacked -Wswitch-enum -Wmissing-format-attribute \
-Wstrict-aliasing=2 -Winit-self \
-Wdeclaration-after-statement -Wold-style-definition \
-Wno-unused-parameter \
-Wno-attributes -Wno-long-long -Winline -Wshadow \
-Wno-missing-field-initializers"
# invalidate cached value if MAYBE_WARN has changed
if test "x$libdrm_cv_warn_maybe" != "x$MAYBE_WARN"; then
unset libdrm_cv_warn_cflags
fi
AC_CACHE_CHECK([for supported warning flags], libdrm_cv_warn_cflags, [
echo
WARN_CFLAGS=""
# Some warning options are not supported by all versions of
# gcc, so test all desired options against the current
# compiler.
#
# Note that there are some order dependencies
# here. Specifically, an option that disables a warning will
# have no net effect if a later option then enables that
# warnings, (perhaps implicitly). So we put some grouped
# options (-Wall and -Wextra) up front and the -Wno options
# last.
for W in $MAYBE_WARN; do
LIBDRM_CC_TRY_FLAG([$W], [WARN_CFLAGS="$WARN_CFLAGS $W"])
done
libdrm_cv_warn_cflags=$WARN_CFLAGS
libdrm_cv_warn_maybe=$MAYBE_WARN
AC_MSG_CHECKING([which warning flags were supported])])
WARN_CFLAGS="$libdrm_cv_warn_cflags"
# Check for atomic intrinsics
AC_CACHE_CHECK([for native atomic primitives], drm_cv_atomic_primitives, [
drm_cv_atomic_primitives="none"
AC_LINK_IFELSE([AC_LANG_PROGRAM([[
int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); }
int atomic_cmpxchg(int *i, int j, int k) { return __sync_val_compare_and_swap (i, j, k); }
]],[[]])], [drm_cv_atomic_primitives="Intel"],[])
if test "x$drm_cv_atomic_primitives" = "xnone"; then
AC_CHECK_HEADER([atomic_ops.h], drm_cv_atomic_primitives="libatomic-ops")
fi
# atomic functions defined in <atomic.h> & libc on Solaris
if test "x$drm_cv_atomic_primitives" = "xnone"; then
AC_CHECK_FUNC([atomic_cas_uint], drm_cv_atomic_primitives="Solaris")
fi
])
if test "x$drm_cv_atomic_primitives" = xIntel; then
AC_DEFINE(HAVE_LIBDRM_ATOMIC_PRIMITIVES, 1,
[Enable if your compiler supports the Intel __sync_* atomic primitives])
else
AC_DEFINE(HAVE_LIBDRM_ATOMIC_PRIMITIVES, 0)
fi
if test "x$drm_cv_atomic_primitives" = "xlibatomic-ops"; then
AC_DEFINE(HAVE_LIB_ATOMIC_OPS, 1, [Enable if you have libatomic-ops-dev installed])
else
AC_DEFINE(HAVE_LIB_ATOMIC_OPS, 0)
fi
dnl Print out the approapriate message considering the value set be the
dnl respective in $1.
dnl $1 - value to be evaluated. Eg. $INTEL, $NOUVEAU, ...
dnl $2 - libdrm shortname. Eg. intel, freedreno, ...
dnl $3 - GPU name/brand. Eg. Intel, NVIDIA Tegra, ...
dnl $4 - Configure switch. Eg. intel, omap-experimental-api, ...
AC_DEFUN([LIBDRM_ATOMICS_NOT_FOUND_MSG], [
case "x$1" in
xyes) AC_MSG_ERROR([libdrm_$2 depends upon atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package, or, failing both of those, disable support for $3 GPUs by passing --disable-$4 to ./configure]) ;;
xauto) AC_MSG_WARN([Disabling $2. It depends on atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package.]) ;;
*) ;;
esac
])
if test "x$drm_cv_atomic_primitives" = "xnone"; then
LIBDRM_ATOMICS_NOT_FOUND_MSG($INTEL, intel, Intel, intel)
INTEL=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($RADEON, radeon, Radeon, radeon)
RADEON=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($AMDGPU, amdgpu, AMD, amdgpu)
AMDGPU=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($NOUVEAU, nouveau, NVIDIA, nouveau)
NOUVEAU=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($OMAP, omap, OMAP, omap-experimental-api)
OMAP=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($FREEDRENO, freedreno, Qualcomm Adreno, freedreno)
FREEDRENO=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($TEGRA, tegra, NVIDIA Tegra, tegra-experimental-api)
TEGRA=no
LIBDRM_ATOMICS_NOT_FOUND_MSG($ETNAVIV, etnaviv, Vivante, etnaviv-experimental-api)
ETNAVIV=no
else
if test "x$INTEL" = xauto; then
case $host_cpu in
i?86|x86_64) INTEL=yes ;;
*) INTEL=no ;;
esac
fi
if test "x$RADEON" = xauto; then
RADEON=yes
fi
if test "x$AMDGPU" = xauto; then
AMDGPU=yes
fi
if test "x$NOUVEAU" = xauto; then
NOUVEAU=yes
fi
if test "x$FREEDRENO" = xauto; then
case $host_cpu in
arm*|aarch64) FREEDRENO=yes ;;
*) FREEDRENO=no ;;
esac
fi
if test "x$VC4" = xauto; then
case $host_cpu in
arm*|aarch64) VC4=yes ;;
*) VC4=no ;;
esac
fi
fi
if test "x$INTEL" != "xno"; then
PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
fi
AC_SUBST(PCIACCESS_CFLAGS)
AC_SUBST(PCIACCESS_LIBS)
if test "x$UDEV" = xyes; then
AC_DEFINE(UDEV, 1, [Have UDEV support])
else
AC_DEFINE(UDEV, 0)
fi
AC_CANONICAL_HOST
if test "x$LIBKMS" = xauto ; then
case $host_os in
linux*) LIBKMS="yes" ;;
freebsd* | kfreebsd*-gnu)
LIBKMS="yes" ;;
dragonfly*) LIBKMS="yes" ;;
*) LIBKMS="no" ;;
esac
fi
AM_CONDITIONAL(HAVE_LIBKMS, [test "x$LIBKMS" = xyes])
AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
if test "x$INTEL" = xyes; then
AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
else
AC_DEFINE(HAVE_INTEL, 0)
fi
AM_CONDITIONAL(HAVE_VMWGFX, [test "x$VMWGFX" = xyes])
if test "x$VMWGFX" = xyes; then
AC_DEFINE(HAVE_VMWGFX, 1, [Have vmwgfx kernel headers])
else
AC_DEFINE(HAVE_VMWGFX, 0)
fi
AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" = xyes])
if test "x$NOUVEAU" = xyes; then
AC_DEFINE(HAVE_NOUVEAU, 1, [Have nouveau (nvidia) support])
else
AC_DEFINE(HAVE_NOUVEAU, 0)
fi
AM_CONDITIONAL(HAVE_OMAP, [test "x$OMAP" = xyes])
AM_CONDITIONAL(HAVE_EXYNOS, [test "x$EXYNOS" = xyes])
if test "x$EXYNOS" = xyes; then
AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support])
else
AC_DEFINE(HAVE_EXYNOS, 0)
fi
AM_CONDITIONAL(HAVE_FREEDRENO, [test "x$FREEDRENO" = xyes])
if test "x$FREEDRENO_KGSL" = xyes; then
if test "x$FREEDRENO" != xyes; then
AC_MSG_ERROR([Cannot enable freedreno KGSL interface if freedreno is disabled])
fi
fi
AM_CONDITIONAL(HAVE_FREEDRENO_KGSL, [test "x$FREEDRENO_KGSL" = xyes])
if test "x$FREEDRENO_KGSL" = xyes; then
AC_DEFINE(HAVE_FREEDRENO_KGSL, 1, [Have freedreno support for KGSL kernel interface])
else
AC_DEFINE(HAVE_FREEDRENO_KGSL, 0)
fi
AM_CONDITIONAL(HAVE_RADEON, [test "x$RADEON" = xyes])
if test "x$RADEON" = xyes; then
AC_DEFINE(HAVE_RADEON, 1, [Have radeon support])
else
AC_DEFINE(HAVE_RADEON, 0)
fi
if test "x$AMDGPU" != xno; then
# Detect cunit library
PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no])
# If pkg-config does not find cunit, check it using AC_CHECK_LIB. We
# do this because Debian (Ubuntu) lacks pkg-config file for cunit.
# fixed in 2.1-2.dfsg-3: http://anonscm.debian.org/cgit/collab-maint/cunit.git/commit/?h=debian
if test "x${have_cunit}" = "xno"; then
AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no])
if test "x${have_cunit}" = "xyes"; then
CUNIT_LIBS="-lcunit"
CUNIT_CFLAGS=""
AC_SUBST([CUNIT_LIBS])
AC_SUBST([CUNIT_CFLAGS])
fi
fi
else
have_cunit=no
fi
AM_CONDITIONAL(HAVE_CUNIT, [test "x$have_cunit" != "xno"])
AM_CONDITIONAL(HAVE_AMDGPU, [test "x$AMDGPU" = xyes])
if test "x$AMDGPU" = xyes; then
AC_DEFINE(HAVE_AMDGPU, 1, [Have amdgpu support])
if test "x$have_cunit" = "xno"; then
AC_MSG_WARN([Could not find cunit library. Disabling amdgpu tests])
fi
else
AC_DEFINE(HAVE_AMDGPU, 0)
fi
AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes])
AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes])
if test "x$VC4" = xyes; then
AC_DEFINE(HAVE_VC4, 1, [Have VC4 support])
else
AC_DEFINE(HAVE_VC4, 0)
fi
AM_CONDITIONAL(HAVE_ETNAVIV, [test "x$ETNAVIV" = xyes])
AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes])
AC_ARG_ENABLE([cairo-tests],
[AS_HELP_STRING([--enable-cairo-tests],
[Enable support for Cairo rendering in tests (default: auto)])],
[CAIRO=$enableval], [CAIRO=auto])
if test "x$CAIRO" != xno; then
PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no])
fi
AC_MSG_CHECKING([whether to enable Cairo tests])
if test "x$CAIRO" = xauto; then
CAIRO="$HAVE_CAIRO"
fi
if test "x$CAIRO" = xyes; then
if ! test "x$HAVE_CAIRO" = xyes; then
AC_MSG_ERROR([Cairo support required but not present])
fi
AC_DEFINE(HAVE_CAIRO, 1, [Have Cairo support])
else
AC_DEFINE(HAVE_CAIRO, 0)
fi
AC_MSG_RESULT([$CAIRO])
AM_CONDITIONAL(HAVE_CAIRO, [test "x$CAIRO" = xyes])
# xsltproc for docbook manpages
AC_ARG_ENABLE([manpages],
AS_HELP_STRING([--enable-manpages], [enable manpages @<:@default=auto@:>@]),
[MANS=$enableval], [MANS=auto])
AM_CONDITIONAL([BUILD_MANPAGES], [test "x$XSLTPROC" != "x" -a "x$MANS" != "xno"])
# check for offline man-pages stylesheet
AC_MSG_CHECKING([for docbook manpages stylesheet])
MANPAGES_STYLESHEET="http://docbook.sourceforge.net/release/xsl/current/manpages/docbook.xsl"
AC_PATH_PROGS_FEATURE_CHECK([XSLTPROC_TMP], [xsltproc],
AS_IF([`"$ac_path_XSLTPROC_TMP" --nonet "$MANPAGES_STYLESHEET" > /dev/null 2>&1`],
[HAVE_MANPAGES_STYLESHEET=yes]))
if test "x$HAVE_MANPAGES_STYLESHEET" = "xyes"; then
AC_SUBST(MANPAGES_STYLESHEET)
AC_MSG_RESULT([yes])
else
AC_MSG_RESULT([no])
fi
AM_CONDITIONAL([HAVE_MANPAGES_STYLESHEET], [test "x$HAVE_MANPAGES_STYLESHEET" = "xyes"])
AC_ARG_ENABLE(valgrind,
[AS_HELP_STRING([--enable-valgrind],
[Build libdrm with valgrind support (default: auto)])],
[VALGRIND=$enableval], [VALGRIND=auto])
if test "x$VALGRIND" != xno; then
PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no])
fi
AC_MSG_CHECKING([whether to enable Valgrind support])
if test "x$VALGRIND" = xauto; then
VALGRIND="$have_valgrind"
fi
if test "x$VALGRIND" = "xyes"; then
if ! test "x$have_valgrind" = xyes; then
AC_MSG_ERROR([Valgrind support required but not present])
fi
AC_DEFINE([HAVE_VALGRIND], 1, [Use valgrind intrinsics to suppress false warnings])
else
AC_DEFINE([HAVE_VALGRIND], 0)
fi
AC_MSG_RESULT([$VALGRIND])
AC_ARG_WITH([kernel-source],
[AS_HELP_STRING([--with-kernel-source],
[specify path to linux kernel source])],
[kernel_source="$with_kernel_source"])
AC_SUBST(kernel_source)
AC_MSG_CHECKING([whether $CC supports __attribute__(("hidden"))])
AC_LINK_IFELSE([AC_LANG_PROGRAM([
int foo_hidden( void ) __attribute__((visibility("hidden")));
])], HAVE_ATTRIBUTE_VISIBILITY="yes"; AC_MSG_RESULT([yes]), AC_MSG_RESULT([no]));
if test "x$HAVE_ATTRIBUTE_VISIBILITY" = xyes; then
AC_DEFINE(HAVE_VISIBILITY, 1, [Compiler supports __attribute__(("hidden"))])
else
AC_DEFINE(HAVE_VISIBILITY, 0)
fi
CFLAGS="$CFLAGS -include config.h"
AC_SUBST(WARN_CFLAGS)
AC_CONFIG_FILES([
Makefile
data/Makefile
libkms/Makefile
libkms/libkms.pc
intel/Makefile
intel/libdrm_intel.pc
radeon/Makefile
radeon/libdrm_radeon.pc
amdgpu/Makefile
amdgpu/libdrm_amdgpu.pc
nouveau/Makefile
nouveau/libdrm_nouveau.pc
omap/Makefile
omap/libdrm_omap.pc
exynos/Makefile
exynos/libdrm_exynos.pc
freedreno/Makefile
freedreno/libdrm_freedreno.pc
tegra/Makefile
tegra/libdrm_tegra.pc
vc4/Makefile
vc4/libdrm_vc4.pc
etnaviv/Makefile
etnaviv/libdrm_etnaviv.pc
tests/Makefile
tests/modeprint/Makefile
tests/modetest/Makefile
tests/kms/Makefile
tests/kmstest/Makefile
tests/proptest/Makefile
tests/radeon/Makefile
tests/amdgpu/Makefile
tests/vbltest/Makefile
tests/exynos/Makefile
tests/tegra/Makefile
tests/nouveau/Makefile
tests/etnaviv/Makefile
tests/util/Makefile
man/Makefile
libdrm.pc])
AC_OUTPUT
echo ""
echo "$PACKAGE_STRING will be compiled with:"
echo ""
echo " libkms $LIBKMS"
echo " Intel API $INTEL"
echo " vmwgfx API $VMWGFX"
echo " Radeon API $RADEON"
echo " AMDGPU API $AMDGPU"
echo " Nouveau API $NOUVEAU"
echo " OMAP API $OMAP"
echo " EXYNOS API $EXYNOS"
echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)"
echo " Tegra API $TEGRA"
echo " VC4 API $VC4"
echo " Etnaviv API $ETNAVIV"
echo ""

212
core-symbols.txt Normal file
View file

@ -0,0 +1,212 @@
drmAddBufs
drmAddContextPrivateMapping
drmAddContextTag
drmAddMap
drmAgpAcquire
drmAgpAlloc
drmAgpBase
drmAgpBind
drmAgpDeviceId
drmAgpEnable
drmAgpFree
drmAgpGetMode
drmAgpMemoryAvail
drmAgpMemoryUsed
drmAgpRelease
drmAgpSize
drmAgpUnbind
drmAgpVendorId
drmAgpVersionMajor
drmAgpVersionMinor
drmAuthMagic
drmAvailable
drmCheckModesettingSupported
drmClose
drmCloseBufferHandle
drmCloseOnce
drmCommandNone
drmCommandRead
drmCommandWrite
drmCommandWriteRead
drmCreateContext
drmCreateDrawable
drmCrtcGetSequence
drmCrtcQueueSequence
drmCtlInstHandler
drmCtlUninstHandler
drmDelContextTag
drmDestroyContext
drmDestroyDrawable
drmDevicesEqual
drmDMA
drmDropMaster
drmError
drmFinish
drmFree
drmFreeBufs
drmFreeBusid
drmFreeDevice
drmFreeDevices
drmFreeReservedContextList
drmFreeVersion
drmGetBufInfo
drmGetBusid
drmGetCap
drmGetClient
drmGetContextFlags
drmGetContextPrivateMapping
drmGetContextTag
drmGetDevice
drmGetDevice2
drmGetDeviceFromDevId
drmGetDeviceNameFromFd
drmGetDeviceNameFromFd2
drmGetDevices
drmGetDevices2
drmGetEntry
drmGetHashTable
drmGetInterruptFromBusID
drmGetLibVersion
drmGetLock
drmGetMagic
drmGetMap
drmGetNodeTypeFromDevId
drmGetNodeTypeFromFd
drmGetPrimaryDeviceNameFromFd
drmGetRenderDeviceNameFromFd
drmGetReservedContextList
drmGetStats
drmGetVersion
drmHandleEvent
drmHashCreate
drmHashDelete
drmHashDestroy
drmHashFirst
drmHashInsert
drmHashLookup
drmHashNext
drmIoctl
drmIsKMS
drmIsMaster
drmMalloc
drmMap
drmMapBufs
drmMarkBufs
drmModeAddFB
drmModeAddFB2
drmModeAddFB2WithModifiers
drmModeAtomicAddProperty
drmModeAtomicAlloc
drmModeAtomicCommit
drmModeAtomicDuplicate
drmModeAtomicFree
drmModeAtomicGetCursor
drmModeAtomicMerge
drmModeAtomicSetCursor
drmModeAttachMode
drmModeCloseFB
drmModeConnectorGetPossibleCrtcs
drmModeConnectorSetProperty
drmModeCreateDumbBuffer
drmModeCreateLease
drmModeCreatePropertyBlob
drmModeCrtcGetGamma
drmModeCrtcSetGamma
drmModeDestroyDumbBuffer
drmModeDestroyPropertyBlob
drmModeDetachMode
drmModeDirtyFB
drmModeFormatModifierBlobIterNext
drmModeFreeConnector
drmModeFreeCrtc
drmModeFreeEncoder
drmModeFreeFB
drmModeFreeFB2
drmModeFreeModeInfo
drmModeFreeObjectProperties
drmModeFreePlane
drmModeFreePlaneResources
drmModeFreeProperty
drmModeFreePropertyBlob
drmModeFreeResources
drmModeGetConnector
drmModeGetConnectorCurrent
drmModeGetConnectorTypeName
drmModeGetCrtc
drmModeGetEncoder
drmModeGetFB
drmModeGetFB2
drmModeGetLease
drmModeGetPlane
drmModeGetPlaneResources
drmModeGetProperty
drmModeGetPropertyBlob
drmModeGetResources
drmModeListLessees
drmModeMapDumbBuffer
drmModeMoveCursor
drmModeObjectGetProperties
drmModeObjectSetProperty
drmModePageFlip
drmModePageFlipTarget
drmModeRevokeLease
drmModeRmFB
drmModeSetCrtc
drmModeSetCursor
drmModeSetCursor2
drmModeSetPlane
drmMsg
drmOpen
drmOpenControl
drmOpenOnce
drmOpenOnceWithType
drmOpenRender
drmOpenWithType
drmPrimeFDToHandle
drmPrimeHandleToFD
drmRandom
drmRandomCreate
drmRandomDestroy
drmRandomDouble
drmRmMap
drmScatterGatherAlloc
drmScatterGatherFree
drmSetBusid
drmSetClientCap
drmSetContextFlags
drmSetInterfaceVersion
drmSetMaster
drmSetServerInfo
drmSLCreate
drmSLDelete
drmSLDestroy
drmSLDump
drmSLFirst
drmSLInsert
drmSLLookup
drmSLLookupNeighbors
drmSLNext
drmSwitchToContext
drmSyncobjCreate
drmSyncobjDestroy
drmSyncobjEventfd
drmSyncobjExportSyncFile
drmSyncobjFDToHandle
drmSyncobjHandleToFD
drmSyncobjImportSyncFile
drmSyncobjQuery
drmSyncobjQuery2
drmSyncobjReset
drmSyncobjSignal
drmSyncobjTimelineSignal
drmSyncobjTimelineWait
drmSyncobjTransfer
drmSyncobjWait
drmUnlock
drmUnmap
drmUnmapBufs
drmUpdateDrawableInfo
drmWaitVBlank
drmGetFormatModifierName
drmGetFormatModifierVendor
drmGetFormatName

6
data/Android.bp Normal file
View file

@ -0,0 +1,6 @@
prebuilt_etc {
name: "amdgpu.ids",
proprietary: true,
sub_dir: "hwdata",
src: "amdgpu.ids",
}

View file

@ -1,10 +0,0 @@
LOCAL_PATH := $(call my-dir)
include $(CLEAR_VARS)
LOCAL_MODULE := amdgpu.ids
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_CLASS := ETC
LOCAL_PROPRIETARY_MODULE := true
LOCAL_MODULE_RELATIVE_PATH := hwdata
LOCAL_SRC_FILES := $(LOCAL_MODULE)
include $(BUILD_PREBUILT)

View file

@ -1,25 +0,0 @@
# Copyright © 2017 Advanced Micro Devices, Inc.
# All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# on the rights to use, copy, modify, merge, publish, distribute, sub
# license, and/or sell copies of the Software, and to permit persons to whom
# the Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
libdrmdatadir = @libdrmdatadir@
if HAVE_AMDGPU
dist_libdrmdata_DATA = amdgpu.ids
endif

View file

@ -4,184 +4,697 @@
# device_id, revision_id, product_name <-- single tab after comma
1.0.0
6600, 0, AMD Radeon HD 8600/8700M
6600, 81, AMD Radeon (TM) R7 M370
6601, 0, AMD Radeon (TM) HD 8500M/8700M
6604, 0, AMD Radeon R7 M265 Series
6604, 81, AMD Radeon (TM) R7 M350
6605, 0, AMD Radeon R7 M260 Series
6605, 81, AMD Radeon (TM) R7 M340
6606, 0, AMD Radeon HD 8790M
6607, 0, AMD Radeon (TM) HD8530M
6608, 0, AMD FirePro W2100
6610, 0, AMD Radeon HD 8600 Series
6610, 81, AMD Radeon (TM) R7 350
6610, 83, AMD Radeon (TM) R5 340
6611, 0, AMD Radeon HD 8500 Series
6613, 0, AMD Radeon HD 8500 series
1114, C2, AMD Radeon 860M Graphics
1114, C3, AMD Radeon 840M Graphics
1114, D2, AMD Radeon 860M Graphics
1114, D3, AMD Radeon 840M Graphics
1309, 00, AMD Radeon R7 Graphics
130A, 00, AMD Radeon R6 Graphics
130B, 00, AMD Radeon R4 Graphics
130C, 00, AMD Radeon R7 Graphics
130D, 00, AMD Radeon R6 Graphics
130E, 00, AMD Radeon R5 Graphics
130F, 00, AMD Radeon R7 Graphics
130F, D4, AMD Radeon R7 Graphics
130F, D5, AMD Radeon R7 Graphics
130F, D6, AMD Radeon R7 Graphics
130F, D7, AMD Radeon R7 Graphics
1313, 00, AMD Radeon R7 Graphics
1313, D4, AMD Radeon R7 Graphics
1313, D5, AMD Radeon R7 Graphics
1313, D6, AMD Radeon R7 Graphics
1315, 00, AMD Radeon R5 Graphics
1315, D4, AMD Radeon R5 Graphics
1315, D5, AMD Radeon R5 Graphics
1315, D6, AMD Radeon R5 Graphics
1315, D7, AMD Radeon R5 Graphics
1316, 00, AMD Radeon R5 Graphics
1318, 00, AMD Radeon R5 Graphics
131B, 00, AMD Radeon R4 Graphics
131C, 00, AMD Radeon R7 Graphics
131D, 00, AMD Radeon R6 Graphics
1435, AE, AMD Custom GPU 0932
1506, C1, AMD Radeon 610M
1506, C2, AMD Radeon 610M
1506, C3, AMD Radeon 610M
1506, C4, AMD Radeon 610M
150E, C1, AMD Radeon 890M Graphics
150E, C4, AMD Radeon 880M Graphics
150E, C5, AMD Radeon 890M Graphics
150E, C6, AMD Radeon 890M Graphics
150E, D1, AMD Radeon 890M Graphics
150E, D2, AMD Radeon 880M Graphics
150E, D3, AMD Radeon 890M Graphics
1586, C1, Radeon 8060S Graphics
1586, C2, Radeon 8050S Graphics
1586, C4, Radeon 8050S Graphics
1586, D1, Radeon 8060S Graphics
1586, D2, Radeon 8050S Graphics
1586, D4, Radeon 8050S Graphics
1586, D5, Radeon 8040S Graphics
15BF, 00, AMD Radeon 780M Graphics
15BF, 01, AMD Radeon 760M Graphics
15BF, 02, AMD Radeon 780M Graphics
15BF, 03, AMD Radeon 760M Graphics
15BF, C1, AMD Radeon 780M Graphics
15BF, C2, AMD Radeon 780M Graphics
15BF, C3, AMD Radeon 760M Graphics
15BF, C4, AMD Radeon 780M Graphics
15BF, C5, AMD Radeon 740M Graphics
15BF, C6, AMD Radeon 780M Graphics
15BF, C7, AMD Radeon 780M Graphics
15BF, C8, AMD Radeon 760M Graphics
15BF, C9, AMD Radeon 780M Graphics
15BF, CA, AMD Radeon 740M Graphics
15BF, CB, AMD Radeon 760M Graphics
15BF, CC, AMD Radeon 740M Graphics
15BF, CD, AMD Radeon 760M Graphics
15BF, CF, AMD Radeon 780M Graphics
15BF, D0, AMD Radeon 780M Graphics
15BF, D1, AMD Radeon 780M Graphics
15BF, D2, AMD Radeon 780M Graphics
15BF, D3, AMD Radeon 780M Graphics
15BF, D4, AMD Radeon 780M Graphics
15BF, D5, AMD Radeon 760M Graphics
15BF, D6, AMD Radeon 760M Graphics
15BF, D7, AMD Radeon 780M Graphics
15BF, D8, AMD Radeon 740M Graphics
15BF, D9, AMD Radeon 780M Graphics
15BF, DA, AMD Radeon 780M Graphics
15BF, DB, AMD Radeon 760M Graphics
15BF, DC, AMD Radeon 760M Graphics
15BF, DD, AMD Radeon 780M Graphics
15BF, DE, AMD Radeon 740M Graphics
15BF, DF, AMD Radeon 760M Graphics
15BF, F0, AMD Radeon 760M Graphics
15C8, C1, AMD Radeon 740M Graphics
15C8, C2, AMD Radeon 740M Graphics
15C8, C3, AMD Radeon 740M Graphics
15C8, C4, AMD Radeon 740M Graphics
15C8, D1, AMD Radeon 740M Graphics
15C8, D2, AMD Radeon 740M Graphics
15C8, D3, AMD Radeon 740M Graphics
15C8, D4, AMD Radeon 740M Graphics
15D8, 00, AMD Radeon RX Vega 8 Graphics WS
15D8, 91, AMD Radeon Vega 3 Graphics
15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
15D8, 92, AMD Radeon Vega 3 Graphics
15D8, 92, AMD Ryzen Embedded R1505G with Radeon Vega Gfx
15D8, 93, AMD Radeon Vega 1 Graphics
15D8, A1, AMD Radeon Vega 10 Graphics
15D8, A2, AMD Radeon Vega 8 Graphics
15D8, A3, AMD Radeon Vega 6 Graphics
15D8, A4, AMD Radeon Vega 3 Graphics
15D8, B1, AMD Radeon Vega 10 Graphics
15D8, B2, AMD Radeon Vega 8 Graphics
15D8, B3, AMD Radeon Vega 6 Graphics
15D8, B4, AMD Radeon Vega 3 Graphics
15D8, C1, AMD Radeon Vega 10 Graphics
15D8, C2, AMD Radeon Vega 8 Graphics
15D8, C3, AMD Radeon Vega 6 Graphics
15D8, C4, AMD Radeon Vega 3 Graphics
15D8, C5, AMD Radeon Vega 3 Graphics
15D8, C8, AMD Radeon Vega 11 Graphics
15D8, C9, AMD Radeon Vega 8 Graphics
15D8, CA, AMD Radeon Vega 11 Graphics
15D8, CB, AMD Radeon Vega 8 Graphics
15D8, CC, AMD Radeon Vega 3 Graphics
15D8, CE, AMD Radeon Vega 3 Graphics
15D8, CF, AMD Ryzen Embedded R1305G with Radeon Vega Gfx
15D8, D1, AMD Radeon Vega 10 Graphics
15D8, D2, AMD Radeon Vega 8 Graphics
15D8, D3, AMD Radeon Vega 6 Graphics
15D8, D4, AMD Radeon Vega 3 Graphics
15D8, D8, AMD Radeon Vega 11 Graphics
15D8, D9, AMD Radeon Vega 8 Graphics
15D8, DA, AMD Radeon Vega 11 Graphics
15D8, DB, AMD Radeon Vega 3 Graphics
15D8, DB, AMD Radeon Vega 8 Graphics
15D8, DC, AMD Radeon Vega 3 Graphics
15D8, DD, AMD Radeon Vega 3 Graphics
15D8, DE, AMD Radeon Vega 3 Graphics
15D8, DF, AMD Radeon Vega 3 Graphics
15D8, E3, AMD Radeon Vega 3 Graphics
15D8, E4, AMD Ryzen Embedded R1102G with Radeon Vega Gfx
15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
15DD, 84, AMD Radeon Vega 6 Graphics
15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
15DD, 86, AMD Radeon Vega 11 Graphics
15DD, 88, AMD Radeon Vega 8 Graphics
15DD, C1, AMD Radeon Vega 11 Graphics
15DD, C2, AMD Radeon Vega 8 Graphics
15DD, C3, AMD Radeon Vega 3 / 10 Graphics
15DD, C4, AMD Radeon Vega 8 Graphics
15DD, C5, AMD Radeon Vega 3 Graphics
15DD, C6, AMD Radeon Vega 11 Graphics
15DD, C8, AMD Radeon Vega 8 Graphics
15DD, C9, AMD Radeon Vega 11 Graphics
15DD, CA, AMD Radeon Vega 8 Graphics
15DD, CB, AMD Radeon Vega 3 Graphics
15DD, CC, AMD Radeon Vega 6 Graphics
15DD, CE, AMD Radeon Vega 3 Graphics
15DD, CF, AMD Radeon Vega 3 Graphics
15DD, D0, AMD Radeon Vega 10 Graphics
15DD, D1, AMD Radeon Vega 8 Graphics
15DD, D3, AMD Radeon Vega 11 Graphics
15DD, D5, AMD Radeon Vega 8 Graphics
15DD, D6, AMD Radeon Vega 11 Graphics
15DD, D7, AMD Radeon Vega 8 Graphics
15DD, D8, AMD Radeon Vega 3 Graphics
15DD, D9, AMD Radeon Vega 6 Graphics
15DD, E1, AMD Radeon Vega 3 Graphics
15DD, E2, AMD Radeon Vega 3 Graphics
163F, AE, AMD Custom GPU 0405
163F, E1, AMD Custom GPU 0405
164E, D8, AMD Radeon 610M
164E, D9, AMD Radeon 610M
164E, DA, AMD Radeon 610M
164E, DB, AMD Radeon 610M
164E, DC, AMD Radeon 610M
1681, 06, AMD Radeon 680M
1681, 07, AMD Radeon 660M
1681, 0A, AMD Radeon 680M
1681, 0B, AMD Radeon 660M
1681, C7, AMD Radeon 680M
1681, C8, AMD Radeon 680M
1681, C9, AMD Radeon 660M
1900, 01, AMD Radeon 780M Graphics
1900, 02, AMD Radeon 760M Graphics
1900, 03, AMD Radeon 780M Graphics
1900, 04, AMD Radeon 760M Graphics
1900, 05, AMD Radeon 780M Graphics
1900, 06, AMD Radeon 780M Graphics
1900, 07, AMD Radeon 760M Graphics
1900, B0, AMD Radeon 780M Graphics
1900, B1, AMD Radeon 780M Graphics
1900, B2, AMD Radeon 780M Graphics
1900, B3, AMD Radeon 780M Graphics
1900, B4, AMD Radeon 780M Graphics
1900, B5, AMD Radeon 780M Graphics
1900, B6, AMD Radeon 780M Graphics
1900, B7, AMD Radeon 760M Graphics
1900, B8, AMD Radeon 760M Graphics
1900, B9, AMD Radeon 780M Graphics
1900, BA, AMD Radeon 780M Graphics
1900, BB, AMD Radeon 780M Graphics
1900, C0, AMD Radeon 780M Graphics
1900, C1, AMD Radeon 760M Graphics
1900, C2, AMD Radeon 780M Graphics
1900, C3, AMD Radeon 760M Graphics
1900, C4, AMD Radeon 780M Graphics
1900, C5, AMD Radeon 780M Graphics
1900, C6, AMD Radeon 760M Graphics
1900, C7, AMD Radeon 780M Graphics
1900, C8, AMD Radeon 760M Graphics
1900, C9, AMD Radeon 780M Graphics
1900, CA, AMD Radeon 760M Graphics
1900, CB, AMD Radeon 780M Graphics
1900, CC, AMD Radeon 780M Graphics
1900, CD, AMD Radeon 760M Graphics
1900, CE, AMD Radeon 780M Graphics
1900, CF, AMD Radeon 760M Graphics
1900, D0, AMD Radeon 780M Graphics
1900, D1, AMD Radeon 760M Graphics
1900, D2, AMD Radeon 780M Graphics
1900, D3, AMD Radeon 760M Graphics
1900, D4, AMD Radeon 780M Graphics
1900, D5, AMD Radeon 780M Graphics
1900, D6, AMD Radeon 760M Graphics
1900, D7, AMD Radeon 780M Graphics
1900, D8, AMD Radeon 760M Graphics
1900, D9, AMD Radeon 780M Graphics
1900, DA, AMD Radeon 760M Graphics
1900, DB, AMD Radeon 780M Graphics
1900, DC, AMD Radeon 780M Graphics
1900, DD, AMD Radeon 760M Graphics
1900, DE, AMD Radeon 780M Graphics
1900, DF, AMD Radeon 760M Graphics
1900, F0, AMD Radeon 780M Graphics
1900, F1, AMD Radeon 780M Graphics
1900, F2, AMD Radeon 780M Graphics
1901, C1, AMD Radeon 740M Graphics
1901, C2, AMD Radeon 740M Graphics
1901, C3, AMD Radeon 740M Graphics
1901, C6, AMD Radeon 740M Graphics
1901, C7, AMD Radeon 740M Graphics
1901, C8, AMD Radeon 740M Graphics
1901, C9, AMD Radeon 740M Graphics
1901, CA, AMD Radeon 740M Graphics
1901, D1, AMD Radeon 740M Graphics
1901, D2, AMD Radeon 740M Graphics
1901, D3, AMD Radeon 740M Graphics
1901, D4, AMD Radeon 740M Graphics
1901, D5, AMD Radeon 740M Graphics
1901, D6, AMD Radeon 740M Graphics
1901, D7, AMD Radeon 740M Graphics
1901, D8, AMD Radeon 740M Graphics
6600, 00, AMD Radeon HD 8600 / 8700M
6600, 81, AMD Radeon R7 M370
6601, 00, AMD Radeon HD 8500M / 8700M
6604, 00, AMD Radeon R7 M265 Series
6604, 81, AMD Radeon R7 M350
6605, 00, AMD Radeon R7 M260 Series
6605, 81, AMD Radeon R7 M340
6606, 00, AMD Radeon HD 8790M
6607, 00, AMD Radeon R5 M240
6608, 00, AMD FirePro W2100
6610, 00, AMD Radeon R7 200 Series
6610, 81, AMD Radeon R7 350
6610, 83, AMD Radeon R5 340
6610, 87, AMD Radeon R7 200 Series
6611, 00, AMD Radeon R7 200 Series
6611, 87, AMD Radeon R7 200 Series
6613, 00, AMD Radeon R7 200 Series
6617, 00, AMD Radeon R7 240 Series
6617, 87, AMD Radeon R7 200 Series
6617, C7, AMD Radeon R7 240 Series
6640, 0, AMD Radeon HD 8950
6640, 80, AMD Radeon (TM) R9 M380
6646, 0, AMD Radeon R9 M280X
6646, 80, AMD Radeon (TM) R9 M470X
6647, 0, AMD Radeon R9 M270X
6647, 80, AMD Radeon (TM) R9 M380
6649, 0, AMD FirePro W5100
6658, 0, AMD Radeon R7 200 Series
665C, 0, AMD Radeon HD 7700 Series
665D, 0, AMD Radeon R7 200 Series
665F, 81, AMD Radeon (TM) R7 300 Series
6660, 0, AMD Radeon HD 8600M Series
6660, 81, AMD Radeon (TM) R5 M335
6660, 83, AMD Radeon (TM) R5 M330
6663, 0, AMD Radeon HD 8500M Series
6663, 83, AMD Radeon (TM) R5 M320
6664, 0, AMD Radeon R5 M200 Series
6665, 0, AMD Radeon R5 M200 Series
6665, 83, AMD Radeon (TM) R5 M320
6667, 0, AMD Radeon R5 M200 Series
666F, 0, AMD Radeon HD 8500M
6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
6798, 0, AMD Radeon HD 7900 Series
679A, 0, AMD Radeon HD 7900 Series
679B, 0, AMD Radeon HD 7900 Series
679E, 0, AMD Radeon HD 7800 Series
67A0, 0, AMD Radeon FirePro W9100
67A1, 0, AMD Radeon FirePro W8100
67B0, 0, AMD Radeon R9 200 Series
67B0, 80, AMD Radeon (TM) R9 390 Series
67B1, 0, AMD Radeon R9 200 Series
67B1, 80, AMD Radeon (TM) R9 390 Series
67B9, 0, AMD Radeon R9 200 Series
67DF, C1, Radeon RX 580 Series
67DF, C2, Radeon RX 570 Series
67DF, C3, Radeon RX 580 Series
67DF, C4, AMD Radeon (TM) RX 480 Graphics
67DF, C5, AMD Radeon (TM) RX 470 Graphics
67DF, C6, Radeon RX 570 Series
67DF, C7, AMD Radeon (TM) RX 480 Graphics
67DF, CF, AMD Radeon (TM) RX 470 Graphics
67DF, D7, Radeon(TM) RX 470 Graphics
67DF, E3, Radeon RX Series
67DF, E7, Radeon RX 580 Series
67DF, EF, Radeon RX 570 Series
67C2, 01, AMD Radeon (TM) Pro V7350x2
67C2, 02, AMD Radeon (TM) Pro V7300X
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics
67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics
67D0, 01, AMD Radeon (TM) Pro V7350x2
67D0, 02, AMD Radeon (TM) Pro V7300X
67E0, 00, AMD Radeon (TM) Pro WX Series
67E3, 00, AMD Radeon (TM) Pro WX 4100
67E8, 00, AMD Radeon (TM) Pro WX Series
67E8, 01, AMD Radeon (TM) Pro WX Series
67E8, 80, AMD Radeon (TM) E9260 Graphics
67EB, 00, AMD Radeon (TM) Pro V5300X
67EF, C0, AMD Radeon (TM) RX Graphics
67EF, C1, AMD Radeon (TM) RX 460 Graphics
67EF, C3, Radeon RX Series
67EF, C5, AMD Radeon (TM) RX 460 Graphics
67EF, C7, AMD Radeon (TM) RX Graphics
67EF, CF, AMD Radeon (TM) RX 460 Graphics
67EF, E0, Radeon RX 560 Series
67EF, E1, Radeon RX Series
67EF, E3, Radeon RX Series
67EF, E5, Radeon RX 560 Series
67EF, EF, AMD Radeon (TM) RX Graphics
67EF, FF, Radeon(TM) RX 460 Graphics
67FF, C0, AMD Radeon (TM) RX Graphics
67FF, C1, AMD Radeon (TM) RX Graphics
67FF, CF, Radeon RX 560 Series
67FF, EF, Radeon RX 560 Series
67FF, FF, Radeon RX 550 Series
6800, 0, AMD Radeon HD 7970M
6801, 0, AMD Radeon(TM) HD8970M
6808, 0, ATI FirePro V(FireGL V) Graphics Adapter
6809, 0, ATI FirePro V(FireGL V) Graphics Adapter
6810, 0, AMD Radeon(TM) HD 8800 Series
6810, 81, AMD Radeon (TM) R7 370 Series
6811, 0, AMD Radeon(TM) HD8800 Series
6811, 81, AMD Radeon (TM) R7 300 Series
6818, 0, AMD Radeon HD 7800 Series
6819, 0, AMD Radeon HD 7800 Series
6820, 0, AMD Radeon HD 8800M Series
6820, 81, AMD Radeon (TM) R9 M375
6820, 83, AMD Radeon (TM) R9 M375X
6821, 0, AMD Radeon HD 8800M Series
6821, 87, AMD Radeon (TM) R7 M380
6821, 83, AMD Radeon R9 (TM) M370X
6822, 0, AMD Radeon E8860
6823, 0, AMD Radeon HD 8800M Series
6825, 0, AMD Radeon HD 7800M Series
6827, 0, AMD Radeon HD 7800M Series
6828, 0, ATI FirePro V(FireGL V) Graphics Adapter
682B, 0, AMD Radeon HD 8800M Series
682B, 87, AMD Radeon (TM) R9 M360
682C, 0, AMD FirePro W4100
682D, 0, AMD Radeon HD 7700M Series
682F, 0, AMD Radeon HD 7700M Series
6835, 0, AMD Radeon R7 Series / HD 9000 Series
6837, 0, AMD Radeon HD7700 Series
683D, 0, AMD Radeon HD 7700 Series
683F, 0, AMD Radeon HD 7700 Series
6860, 00, Radeon Instinct MI25
6860, 01, Radeon Pro V320
6860, 02, Radeon Instinct MI25
6860, 03, Radeon Pro V340
6860, 04, Radeon Instinct MI25x2
6861, 00, Radeon(TM) Pro WX9100
6862, 00, Radeon Pro SSG
6863, 00, Radeon Vega Frontier Edition
6864, 03, Radeon Pro V340
6864, 04, Instinct MI25x2
6868, 00, Radeon(TM) Pro WX8100
686C, 00, GLXT (Radeon Instinct MI25) MxGPU VFID
686C, 01, GLXT (Radeon Pro V320) MxGPU
686C, 02, GLXT (Radeon Instinct MI25) MxGPU
686C, 03, GLXT (Radeon Pro V340) MxGPU
686C, 04, GLXT (Radeon Instinct MI25x2) MxGPU
687F, C0, Radeon RX Vega
687F, C1, Radeon RX Vega
687F, C3, Radeon RX Vega
6900, 0, AMD Radeon R7 M260
6900, 81, AMD Radeon (TM) R7 M360
6900, 83, AMD Radeon (TM) R7 M340
6901, 0, AMD Radeon R5 M255
6907, 0, AMD Radeon R5 M255
6907, 87, AMD Radeon (TM) R5 M315
6920, 0, AMD RADEON R9 M395X
6920, 1, AMD RADEON R9 M390X
6921, 0, AMD Radeon R9 M295X
6929, 0, AMD FirePro S7150
692B, 0, AMD FirePro W7100
6938, 0, AMD Radeon R9 200 Series
6640, 00, AMD Radeon HD 8950
6640, 80, AMD Radeon R9 M380
6646, 00, AMD Radeon R9 M280X
6646, 80, AMD Radeon R9 M385
6646, 80, AMD Radeon R9 M470X
6647, 00, AMD Radeon R9 M200X Series
6647, 80, AMD Radeon R9 M380
6649, 00, AMD FirePro W5100
6658, 00, AMD Radeon R7 200 Series
665C, 00, AMD Radeon HD 7700 Series
665D, 00, AMD Radeon R7 200 Series
665F, 81, AMD Radeon R7 360 Series
6660, 00, AMD Radeon HD 8600M Series
6660, 81, AMD Radeon R5 M335
6660, 83, AMD Radeon R5 M330
6663, 00, AMD Radeon HD 8500M Series
6663, 83, AMD Radeon R5 M320
6664, 00, AMD Radeon R5 M200 Series
6665, 00, AMD Radeon R5 M230 Series
6665, 83, AMD Radeon R5 M320
6665, C3, AMD Radeon R5 M435
6666, 00, AMD Radeon R5 M200 Series
6667, 00, AMD Radeon R5 M200 Series
666F, 00, AMD Radeon HD 8500M
66A1, 02, AMD Instinct MI60 / MI50
66A1, 06, AMD Radeon Pro VII
66AF, C1, AMD Radeon VII
6780, 00, AMD FirePro W9000
6784, 00, ATI FirePro V (FireGL V) Graphics Adapter
6788, 00, ATI FirePro V (FireGL V) Graphics Adapter
678A, 00, AMD FirePro W8000
6798, 00, AMD Radeon R9 200 / HD 7900 Series
6799, 00, AMD Radeon HD 7900 Series
679A, 00, AMD Radeon HD 7900 Series
679B, 00, AMD Radeon HD 7900 Series
679E, 00, AMD Radeon HD 7800 Series
67A0, 00, AMD Radeon FirePro W9100
67A1, 00, AMD Radeon FirePro W8100
67B0, 00, AMD Radeon R9 200 Series
67B0, 80, AMD Radeon R9 390 Series
67B1, 00, AMD Radeon R9 200 Series
67B1, 80, AMD Radeon R9 390 Series
67B9, 00, AMD Radeon R9 200 Series
67C0, 00, AMD Radeon Pro WX 7100 Graphics
67C0, 80, AMD Radeon E9550
67C2, 01, AMD Radeon Pro V7350x2
67C2, 02, AMD Radeon Pro V7300X
67C4, 00, AMD Radeon Pro WX 7100 Graphics
67C4, 80, AMD Radeon E9560 / E9565 Graphics
67C7, 00, AMD Radeon Pro WX 5100 Graphics
67C7, 80, AMD Radeon E9390 Graphics
67D0, 01, AMD Radeon Pro V7350x2
67D0, 02, AMD Radeon Pro V7300X
67DF, C0, AMD Radeon Pro 580X
67DF, C1, AMD Radeon RX 580 Series
67DF, C2, AMD Radeon RX 570 Series
67DF, C3, AMD Radeon RX 580 Series
67DF, C4, AMD Radeon RX 480 Graphics
67DF, C5, AMD Radeon RX 470 Graphics
67DF, C6, AMD Radeon RX 570 Series
67DF, C7, AMD Radeon RX 480 Graphics
67DF, CF, AMD Radeon RX 470 Graphics
67DF, D7, AMD Radeon RX 470 Graphics
67DF, E0, AMD Radeon RX 470 Series
67DF, E1, AMD Radeon RX 590 Series
67DF, E3, AMD Radeon RX Series
67DF, E7, AMD Radeon RX 580 Series
67DF, EB, AMD Radeon Pro 580X
67DF, EF, AMD Radeon RX 570 Series
67DF, F7, AMD Radeon RX P30PH
67DF, FF, AMD Radeon RX 470 Series
67E0, 00, AMD Radeon Pro WX Series
67E3, 00, AMD Radeon Pro WX 4100
67E8, 00, AMD Radeon Pro WX Series
67E8, 01, AMD Radeon Pro WX Series
67E8, 80, AMD Radeon E9260 Graphics
67EB, 00, AMD Radeon Pro V5300X
67EF, C0, AMD Radeon RX Graphics
67EF, C1, AMD Radeon RX 460 Graphics
67EF, C2, AMD Radeon Pro Series
67EF, C3, AMD Radeon RX Series
67EF, C5, AMD Radeon RX 460 Graphics
67EF, C7, AMD Radeon RX Graphics
67EF, CF, AMD Radeon RX 460 Graphics
67EF, E0, AMD Radeon RX 560 Series
67EF, E1, AMD Radeon RX Series
67EF, E2, AMD Radeon RX 560X
67EF, E3, AMD Radeon RX Series
67EF, E5, AMD Radeon RX 560 Series
67EF, E7, AMD Radeon RX 560 Series
67EF, EF, AMD Radeon 550 Series
67EF, FF, AMD Radeon RX 460 Graphics
67FF, C0, AMD Radeon Pro 465
67FF, C1, AMD Radeon RX 560 Series
67FF, CF, AMD Radeon RX 560 Series
67FF, EF, AMD Radeon RX 560 Series
67FF, FF, AMD Radeon RX 550 Series
6800, 00, AMD Radeon HD 7970M
6801, 00, AMD Radeon HD 8970M
6806, 00, AMD Radeon R9 M290X
6808, 00, AMD FirePro W7000
6808, 00, ATI FirePro V (FireGL V) Graphics Adapter
6809, 00, ATI FirePro W5000
6810, 00, AMD Radeon R9 200 Series
6810, 81, AMD Radeon R9 370 Series
6811, 00, AMD Radeon R9 200 Series
6811, 81, AMD Radeon R7 370 Series
6818, 00, AMD Radeon HD 7800 Series
6819, 00, AMD Radeon HD 7800 Series
6820, 00, AMD Radeon R9 M275X
6820, 81, AMD Radeon R9 M375
6820, 83, AMD Radeon R9 M375X
6821, 00, AMD Radeon R9 M200X Series
6821, 83, AMD Radeon R9 M370X
6821, 87, AMD Radeon R7 M380
6822, 00, AMD Radeon E8860
6823, 00, AMD Radeon R9 M200X Series
6825, 00, AMD Radeon HD 7800M Series
6826, 00, AMD Radeon HD 7700M Series
6827, 00, AMD Radeon HD 7800M Series
6828, 00, AMD FirePro W600
682B, 00, AMD Radeon HD 8800M Series
682B, 87, AMD Radeon R9 M360
682C, 00, AMD FirePro W4100
682D, 00, AMD Radeon HD 7700M Series
682F, 00, AMD Radeon HD 7700M Series
6830, 00, AMD Radeon 7800M Series
6831, 00, AMD Radeon 7700M Series
6835, 00, AMD Radeon R7 Series / HD 9000 Series
6837, 00, AMD Radeon HD 7700 Series
683D, 00, AMD Radeon HD 7700 Series
683F, 00, AMD Radeon HD 7700 Series
684C, 00, ATI FirePro V (FireGL V) Graphics Adapter
6860, 00, AMD Radeon Instinct MI25
6860, 01, AMD Radeon Instinct MI25
6860, 02, AMD Radeon Instinct MI25
6860, 03, AMD Radeon Pro V340
6860, 04, AMD Radeon Instinct MI25x2
6860, 07, AMD Radeon Pro V320
6861, 00, AMD Radeon Pro WX 9100
6862, 00, AMD Radeon Pro SSG
6863, 00, AMD Radeon Vega Frontier Edition
6864, 03, AMD Radeon Pro V340
6864, 04, AMD Radeon Instinct MI25x2
6864, 05, AMD Radeon Pro V340
6868, 00, AMD Radeon Pro WX 8200
686C, 00, AMD Radeon Instinct MI25 MxGPU
686C, 01, AMD Radeon Instinct MI25 MxGPU
686C, 02, AMD Radeon Instinct MI25 MxGPU
686C, 03, AMD Radeon Pro V340 MxGPU
686C, 04, AMD Radeon Instinct MI25x2 MxGPU
686C, 05, AMD Radeon Pro V340L MxGPU
686C, 06, AMD Radeon Instinct MI25 MxGPU
687F, 01, AMD Radeon RX Vega
687F, C0, AMD Radeon RX Vega
687F, C1, AMD Radeon RX Vega
687F, C3, AMD Radeon RX Vega
687F, C7, AMD Radeon RX Vega
6900, 00, AMD Radeon R7 M260
6900, 81, AMD Radeon R7 M360
6900, 83, AMD Radeon R7 M340
6900, C1, AMD Radeon R5 M465 Series
6900, C3, AMD Radeon R5 M445 Series
6900, D1, AMD Radeon 530 Series
6900, D3, AMD Radeon 530 Series
6901, 00, AMD Radeon R5 M255
6902, 00, AMD Radeon Series
6907, 00, AMD Radeon R5 M255
6907, 87, AMD Radeon R5 M315
6920, 00, AMD Radeon R9 M395X
6920, 01, AMD Radeon R9 M390X
6921, 00, AMD Radeon R9 M390X
6929, 00, AMD FirePro S7150
6929, 01, AMD FirePro S7100X
692B, 00, AMD FirePro W7100
6938, 00, AMD Radeon R9 200 Series
6938, F0, AMD Radeon R9 200 Series
6938, F1, AMD Radeon (TM) R9 380 Series
6938, F1, AMD Radeon R9 380 Series
6939, 00, AMD Radeon R9 200 Series
6939, F0, AMD Radeon R9 200 Series
6939, 0, AMD Radeon R9 200 Series
6939, F1, AMD Radeon (TM) R9 380 Series
6980, 00, Radeon Pro WX3100
6985, 00, AMD Radeon Pro WX3100
6939, F1, AMD Radeon R9 380 Series
694C, C0, AMD Radeon RX Vega M GH Graphics
694E, C0, AMD Radeon RX Vega M GL Graphics
6980, 00, AMD Radeon Pro WX 3100
6981, 00, AMD Radeon Pro WX 3200 Series
6981, 01, AMD Radeon Pro WX 3200 Series
6981, 10, AMD Radeon Pro WX 3200 Series
6985, 00, AMD Radeon Pro WX 3100
6986, 00, AMD Radeon Pro WX 2100
6987, 80, AMD Embedded Radeon E9171
6995, 00, AMD Radeon Pro WX2100
6997, 00, Radeon Pro WX2100
6987, C0, AMD Radeon 550X Series
6987, C1, AMD Radeon RX 640
6987, C3, AMD Radeon 540X Series
6987, C7, AMD Radeon 540
6995, 00, AMD Radeon Pro WX 2100
6997, 00, AMD Radeon Pro WX 2100
699F, 81, AMD Embedded Radeon E9170 Series
699F, C0, Radeon 500 Series
699F, C3, Radeon 500 Series
699F, C7, Radeon RX 550 Series
7300, C1, AMD FirePro (TM) S9300 x2
7300, C8, AMD Radeon (TM) R9 Fury Series
7300, C9, Radeon (TM) Pro Duo
7300, CB, AMD Radeon (TM) R9 Fury Series
7300, CA, AMD Radeon (TM) R9 Fury Series
699F, C0, AMD Radeon 500 Series
699F, C1, AMD Radeon 540 Series
699F, C3, AMD Radeon 500 Series
699F, C7, AMD Radeon RX 550 / 550 Series
699F, C9, AMD Radeon 540
6FDF, E7, AMD Radeon RX 590 GME
6FDF, EF, AMD Radeon RX 580 2048SP
7300, C1, AMD FirePro S9300 x2
7300, C8, AMD Radeon R9 Fury Series
7300, C9, AMD Radeon Pro Duo
7300, CA, AMD Radeon R9 Fury Series
7300, CB, AMD Radeon R9 Fury Series
7312, 00, AMD Radeon Pro W5700
731E, C6, AMD Radeon RX 5700XTB
731E, C7, AMD Radeon RX 5700B
731F, C0, AMD Radeon RX 5700 XT 50th Anniversary
731F, C1, AMD Radeon RX 5700 XT
731F, C2, AMD Radeon RX 5600M
731F, C3, AMD Radeon RX 5700M
731F, C4, AMD Radeon RX 5700
731F, C5, AMD Radeon RX 5700 XT
731F, CA, AMD Radeon RX 5600 XT
731F, CB, AMD Radeon RX 5600 OEM
7340, C1, AMD Radeon RX 5500M
7340, C3, AMD Radeon RX 5300M
7340, C5, AMD Radeon RX 5500 XT
7340, C7, AMD Radeon RX 5500
7340, C9, AMD Radeon RX 5500XTB
7340, CF, AMD Radeon RX 5300
7341, 00, AMD Radeon Pro W5500
7347, 00, AMD Radeon Pro W5500M
7360, 41, AMD Radeon Pro 5600M
7360, C3, AMD Radeon Pro V520
7362, C1, AMD Radeon Pro V540
7362, C3, AMD Radeon Pro V520
738C, 01, AMD Instinct MI100
73A1, 00, AMD Radeon Pro V620
73A3, 00, AMD Radeon Pro W6800
73A5, C0, AMD Radeon RX 6950 XT
73AE, 00, AMD Radeon Pro V620 MxGPU
73AF, C0, AMD Radeon RX 6900 XT
73BF, C0, AMD Radeon RX 6900 XT
73BF, C1, AMD Radeon RX 6800 XT
73BF, C3, AMD Radeon RX 6800
73DF, C0, AMD Radeon RX 6750 XT
73DF, C1, AMD Radeon RX 6700 XT
73DF, C2, AMD Radeon RX 6800M
73DF, C3, AMD Radeon RX 6800M
73DF, C5, AMD Radeon RX 6700 XT
73DF, CF, AMD Radeon RX 6700M
73DF, D5, AMD Radeon RX 6750 GRE 12GB
73DF, D7, AMD TDC-235
73DF, DF, AMD Radeon RX 6700
73DF, E5, AMD Radeon RX 6750 GRE 12GB
73DF, FF, AMD Radeon RX 6700
73E0, 00, AMD Radeon RX 6600M
73E1, 00, AMD Radeon Pro W6600M
73E3, 00, AMD Radeon Pro W6600
73EF, C0, AMD Radeon RX 6800S
73EF, C1, AMD Radeon RX 6650 XT
73EF, C2, AMD Radeon RX 6700S
73EF, C3, AMD Radeon RX 6650M
73EF, C4, AMD Radeon RX 6650M XT
73FF, C1, AMD Radeon RX 6600 XT
73FF, C3, AMD Radeon RX 6600M
73FF, C7, AMD Radeon RX 6600
73FF, CB, AMD Radeon RX 6600S
73FF, CF, AMD Radeon RX 6600 LE
73FF, DF, AMD Radeon RX 6750 GRE 10GB
7408, 00, AMD Instinct MI250X
740C, 01, AMD Instinct MI250X / MI250
740F, 02, AMD Instinct MI210
7421, 00, AMD Radeon Pro W6500M
7422, 00, AMD Radeon Pro W6400
7423, 00, AMD Radeon Pro W6300M
7423, 01, AMD Radeon Pro W6300
7424, 00, AMD Radeon RX 6300
743F, C1, AMD Radeon RX 6500 XT
743F, C3, AMD Radeon RX 6500
743F, C3, AMD Radeon RX 6500M
743F, C7, AMD Radeon RX 6400
743F, C8, AMD Radeon RX 6500M
743F, CC, AMD Radeon 6550S
743F, CE, AMD Radeon RX 6450M
743F, CF, AMD Radeon RX 6300M
743F, D3, AMD Radeon RX 6550M
743F, D7, AMD Radeon RX 6400
7448, 00, AMD Radeon Pro W7900
7449, 00, AMD Radeon Pro W7800 48GB
744A, 00, AMD Radeon Pro W7900 Dual Slot
744B, 00, AMD Radeon Pro W7900D
744C, C8, AMD Radeon RX 7900 XTX
744C, CC, AMD Radeon RX 7900 XT
744C, CE, AMD Radeon RX 7900 GRE
744C, CF, AMD Radeon RX 7900M
745E, CC, AMD Radeon Pro W7800
7460, 00, AMD Radeon Pro V710
7461, 00, AMD Radeon Pro V710 MxGPU
7470, 00, AMD Radeon Pro W7700
747E, C8, AMD Radeon RX 7800 XT
747E, D8, AMD Radeon RX 7800M
747E, DB, AMD Radeon RX 7700
747E, FF, AMD Radeon RX 7700 XT
7480, 00, AMD Radeon Pro W7600
7480, C0, AMD Radeon RX 7600 XT
7480, C1, AMD Radeon RX 7700S
7480, C2, AMD Radeon RX 7650 GRE
7480, C3, AMD Radeon RX 7600S
7480, C7, AMD Radeon RX 7600M XT
7480, CF, AMD Radeon RX 7600
7481, C7, AMD Steam Machine
7483, CF, AMD Radeon RX 7600M
7489, 00, AMD Radeon Pro W7500
7499, 00, AMD Radeon Pro W7400
7499, C0, AMD Radeon RX 7400
7499, C1, AMD Radeon RX 7300
74A0, 00, AMD Instinct MI300A
74A1, 00, AMD Instinct MI300X
74A2, 00, AMD Instinct MI308X
74A5, 00, AMD Instinct MI325X
74A8, 00, AMD Instinct MI308X HF
74A9, 00, AMD Instinct MI300X HF
74B5, 00, AMD Instinct MI300X VF
74B6, 00, AMD Instinct MI308X
74BD, 00, AMD Instinct MI300X HF
7550, C0, AMD Radeon RX 9070 XT
7550, C2, AMD Radeon RX 9070 GRE
7550, C3, AMD Radeon RX 9070
7551, C0, AMD Radeon AI PRO R9700
7590, C0, AMD Radeon RX 9060 XT
7590, C7, AMD Radeon RX 9060
75A0, C0, AMD Instinct MI350X
75A3, C0, AMD Instinct MI355X
75B0, C0, AMD Instinct MI350X VF
75B3, C0, AMD Instinct MI355X VF
9830, 00, AMD Radeon HD 8400 / R3 Series
9831, 00, AMD Radeon HD 8400E
9832, 00, AMD Radeon HD 8330
9833, 00, AMD Radeon HD 8330E
9834, 00, AMD Radeon HD 8210
9835, 00, AMD Radeon HD 8210E
9836, 00, AMD Radeon HD 8200 / R3 Series
9837, 00, AMD Radeon HD 8280E
9838, 00, AMD Radeon HD 8200 / R3 series
9839, 00, AMD Radeon HD 8180
983D, 00, AMD Radeon HD 8250
9850, 00, AMD Radeon R3 Graphics
9850, 03, AMD Radeon R3 Graphics
9850, 40, AMD Radeon R2 Graphics
9850, 45, AMD Radeon R3 Graphics
9851, 00, AMD Radeon R4 Graphics
9851, 01, AMD Radeon R5E Graphics
9851, 05, AMD Radeon R5 Graphics
9851, 06, AMD Radeon R5E Graphics
9851, 40, AMD Radeon R4 Graphics
9851, 45, AMD Radeon R5 Graphics
9852, 00, AMD Radeon R2 Graphics
9852, 40, AMD Radeon E1 Graphics
9853, 00, AMD Radeon R2 Graphics
9853, 01, AMD Radeon R4E Graphics
9853, 03, AMD Radeon R2 Graphics
9853, 05, AMD Radeon R1E Graphics
9853, 06, AMD Radeon R1E Graphics
9853, 07, AMD Radeon R1E Graphics
9853, 08, AMD Radeon R1E Graphics
9853, 40, AMD Radeon R2 Graphics
9854, 00, AMD Radeon R3 Graphics
9854, 01, AMD Radeon R3E Graphics
9854, 02, AMD Radeon R3 Graphics
9854, 05, AMD Radeon R2 Graphics
9854, 06, AMD Radeon R4 Graphics
9854, 07, AMD Radeon R3 Graphics
9855, 02, AMD Radeon R6 Graphics
9855, 05, AMD Radeon R4 Graphics
9856, 00, AMD Radeon R2 Graphics
9856, 01, AMD Radeon R2E Graphics
9856, 02, AMD Radeon R2 Graphics
9856, 05, AMD Radeon R1E Graphics
9856, 06, AMD Radeon R2 Graphics
9856, 07, AMD Radeon R1E Graphics
9856, 08, AMD Radeon R1E Graphics
9856, 13, AMD Radeon R1E Graphics
9874, 81, AMD Radeon R6 Graphics
9874, 84, AMD Radeon R7 Graphics
9874, 85, AMD Radeon R6 Graphics
9874, 87, AMD Radeon R5 Graphics
9874, 88, AMD Radeon R7E Graphics
9874, 89, AMD Radeon R6E Graphics
9874, C4, AMD Radeon R7 Graphics
9874, C5, AMD Radeon R6 Graphics
9874, C6, AMD Radeon R6 Graphics
9874, C7, AMD Radeon R5 Graphics
9874, C8, AMD Radeon R7 Graphics
9874, 81, AMD Radeon R6 Graphics
9874, 87, AMD Radeon R5 Graphics
9874, 85, AMD Radeon R6 Graphics
9874, 84, AMD Radeon R7 Graphics
9874, C9, AMD Radeon R7 Graphics
9874, CA, AMD Radeon R5 Graphics
9874, CB, AMD Radeon R5 Graphics
9874, CC, AMD Radeon R7 Graphics
9874, CD, AMD Radeon R7 Graphics
9874, CE, AMD Radeon R5 Graphics
9874, E1, AMD Radeon R7 Graphics
9874, E2, AMD Radeon R7 Graphics
9874, E3, AMD Radeon R7 Graphics
9874, E4, AMD Radeon R7 Graphics
9874, E5, AMD Radeon R5 Graphics
9874, E6, AMD Radeon R5 Graphics
98E4, 80, AMD Radeon R5E Graphics
98E4, 81, AMD Radeon R4E Graphics
98E4, 83, AMD Radeon R2E Graphics
98E4, 84, AMD Radeon R2E Graphics
98E4, 86, AMD Radeon R1E Graphics
98E4, C0, AMD Radeon R4 Graphics
98E4, C1, AMD Radeon R5 Graphics
98E4, C2, AMD Radeon R4 Graphics
98E4, C4, AMD Radeon R5 Graphics
98E4, C6, AMD Radeon R5 Graphics
98E4, C8, AMD Radeon R4 Graphics
98E4, C9, AMD Radeon R4 Graphics
98E4, CA, AMD Radeon R5 Graphics
98E4, D0, AMD Radeon R2 Graphics
98E4, D1, AMD Radeon R2 Graphics
98E4, D2, AMD Radeon R2 Graphics
98E4, D4, AMD Radeon R2 Graphics
98E4, D9, AMD Radeon R5 Graphics
98E4, DA, AMD Radeon R5 Graphics
98E4, DB, AMD Radeon R3 Graphics
98E4, E1, AMD Radeon R3 Graphics
98E4, E2, AMD Radeon R3 Graphics
98E4, E9, AMD Radeon R4 Graphics
98E4, EA, AMD Radeon R4 Graphics
98E4, EB, AMD Radeon R3 Graphics
98E4, EB, AMD Radeon R4 Graphics

11
etnaviv/Android.bp Normal file
View file

@ -0,0 +1,11 @@
build = ["Android.sources.bp"]
cc_library_shared {
name: "libdrm_etnaviv",
defaults: [
"libdrm_defaults",
"libdrm_etnaviv_sources",
],
vendor: true,
shared_libs: ["libdrm"],
}

View file

@ -1,14 +0,0 @@
LOCAL_PATH := $(call my-dir)
include $(CLEAR_VARS)
# Import variables LIBDRM_ETNAVIV_FILES, LIBDRM_ETNAVIV_H_FILES
include $(LOCAL_PATH)/Makefile.sources
LOCAL_MODULE := libdrm_etnaviv
LOCAL_SHARED_LIBRARIES := libdrm
LOCAL_SRC_FILES := $(LIBDRM_ETNAVIV_FILES)
include $(LIBDRM_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)

View file

@ -0,0 +1,13 @@
// Autogenerated with Android.sources.bp.mk
cc_defaults {
name: "libdrm_etnaviv_sources",
srcs: [
"etnaviv_device.c",
"etnaviv_gpu.c",
"etnaviv_bo.c",
"etnaviv_bo_cache.c",
"etnaviv_pipe.c",
"etnaviv_cmd_stream.c",
],
}

View file

@ -1,26 +0,0 @@
include Makefile.sources
AM_CFLAGS = \
$(WARN_CFLAGS) \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
libdrm_etnaviv_ladir = $(libdir)
libdrm_etnaviv_la_LTLIBRARIES = libdrm_etnaviv.la
libdrm_etnaviv_la_LDFLAGS = -version-number 1:0:0 -no-undefined
libdrm_etnaviv_la_LIBADD = \
../libdrm.la \
@PTHREADSTUBS_LIBS@ \
@CLOCK_LIB@
libdrm_etnaviv_la_SOURCES = $(LIBDRM_ETNAVIV_FILES)
libdrm_etnavivincludedir = ${includedir}/libdrm
libdrm_etnavivinclude_HEADERS = $(LIBDRM_ETNAVIV_H_FILES)
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_etnaviv.pc
TESTS = etnaviv-symbol-check
EXTRA_DIST = $(TESTS)

View file

@ -1,13 +0,0 @@
LIBDRM_ETNAVIV_FILES := \
etnaviv_device.c \
etnaviv_gpu.c \
etnaviv_bo.c \
etnaviv_bo_cache.c \
etnaviv_perfmon.c \
etnaviv_pipe.c \
etnaviv_cmd_stream.c \
etnaviv_drm.h \
etnaviv_priv.h
LIBDRM_ETNAVIV_H_FILES := \
etnaviv_drmif.h

View file

@ -1,15 +1,3 @@
#!/bin/bash
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_ETNAVIV_H_FILES
FUNCS=$(nm -D --format=bsd --defined-only ${1-.libs/libdrm_etnaviv.so} | awk '{print $3}'| while read func; do
( grep -q "^$func$" || echo $func ) <<EOF
__bss_start
_edata
_end
_fini
_init
etna_device_new
etna_device_new_dup
etna_device_ref
@ -23,7 +11,6 @@ etna_pipe_del
etna_pipe_wait
etna_pipe_wait_ns
etna_bo_new
etna_bo_from_handle
etna_bo_from_name
etna_bo_from_dmabuf
etna_bo_ref
@ -47,8 +34,3 @@ etna_perfmon_create
etna_perfmon_del
etna_perfmon_get_dom_by_name
etna_perfmon_get_sig_by_name
EOF
done)
test ! -n "$FUNCS" || echo $FUNCS
test ! -n "$FUNCS"

View file

@ -48,12 +48,8 @@ drm_private void bo_del(struct etna_bo *bo)
drmHashDelete(bo->dev->name_table, bo->name);
if (bo->handle) {
struct drm_gem_close req = {
.handle = bo->handle,
};
drmHashDelete(bo->dev->handle_table, bo->handle);
drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
drmCloseBufferHandle(bo->dev->fd, bo->handle);
}
free(bo);
@ -82,12 +78,7 @@ static struct etna_bo *bo_from_handle(struct etna_device *dev,
struct etna_bo *bo = calloc(sizeof(*bo), 1);
if (!bo) {
struct drm_gem_close req = {
.handle = handle,
};
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
drmCloseBufferHandle(dev->fd, handle);
return NULL;
}
@ -104,7 +95,7 @@ static struct etna_bo *bo_from_handle(struct etna_device *dev,
}
/* allocate a new (un-tiled) buffer object */
struct etna_bo *etna_bo_new(struct etna_device *dev, uint32_t size,
drm_public struct etna_bo *etna_bo_new(struct etna_device *dev, uint32_t size,
uint32_t flags)
{
struct etna_bo *bo;
@ -131,7 +122,7 @@ struct etna_bo *etna_bo_new(struct etna_device *dev, uint32_t size,
return bo;
}
struct etna_bo *etna_bo_ref(struct etna_bo *bo)
drm_public struct etna_bo *etna_bo_ref(struct etna_bo *bo)
{
atomic_inc(&bo->refcnt);
@ -159,7 +150,8 @@ static int get_buffer_info(struct etna_bo *bo)
}
/* import a buffer object from DRI2 name */
struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name)
drm_public struct etna_bo *etna_bo_from_name(struct etna_device *dev,
uint32_t name)
{
struct etna_bo *bo;
struct drm_gem_open req = {
@ -196,7 +188,7 @@ out_unlock:
* fd so caller should close() the fd when it is otherwise done
* with it (even if it is still using the 'struct etna_bo *')
*/
struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd)
drm_public struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd)
{
struct etna_bo *bo;
int ret, size;
@ -231,7 +223,7 @@ out_unlock:
}
/* destroy a buffer object */
void etna_bo_del(struct etna_bo *bo)
drm_public void etna_bo_del(struct etna_bo *bo)
{
struct etna_device *dev = bo->dev;
@ -253,7 +245,7 @@ out:
}
/* get the global flink/DRI2 buffer name */
int etna_bo_get_name(struct etna_bo *bo, uint32_t *name)
drm_public int etna_bo_get_name(struct etna_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@ -277,7 +269,7 @@ int etna_bo_get_name(struct etna_bo *bo, uint32_t *name)
return 0;
}
uint32_t etna_bo_handle(struct etna_bo *bo)
drm_public uint32_t etna_bo_handle(struct etna_bo *bo)
{
return bo->handle;
}
@ -285,7 +277,7 @@ uint32_t etna_bo_handle(struct etna_bo *bo)
/* caller owns the dmabuf fd that is returned and is responsible
* to close() it when done
*/
int etna_bo_dmabuf(struct etna_bo *bo)
drm_public int etna_bo_dmabuf(struct etna_bo *bo)
{
int ret, prime_fd;
@ -301,12 +293,12 @@ int etna_bo_dmabuf(struct etna_bo *bo)
return prime_fd;
}
uint32_t etna_bo_size(struct etna_bo *bo)
drm_public uint32_t etna_bo_size(struct etna_bo *bo)
{
return bo->size;
}
void *etna_bo_map(struct etna_bo *bo)
drm_public void *etna_bo_map(struct etna_bo *bo)
{
if (!bo->map) {
if (!bo->offset) {
@ -324,7 +316,7 @@ void *etna_bo_map(struct etna_bo *bo)
return bo->map;
}
int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
drm_public int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
{
struct drm_etnaviv_gem_cpu_prep req = {
.handle = bo->handle,
@ -337,7 +329,7 @@ int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
&req, sizeof(req));
}
void etna_bo_cpu_fini(struct etna_bo *bo)
drm_public void etna_bo_cpu_fini(struct etna_bo *bo)
{
struct drm_etnaviv_gem_cpu_fini req = {
.handle = bo->handle,

View file

@ -55,7 +55,8 @@ etna_cmd_stream_priv(struct etna_cmd_stream *stream)
return (struct etna_cmd_stream_priv *)stream;
}
struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
drm_public struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe,
uint32_t size,
void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
void *priv)
{
@ -95,7 +96,7 @@ fail:
return NULL;
}
void etna_cmd_stream_del(struct etna_cmd_stream *stream)
drm_public void etna_cmd_stream_del(struct etna_cmd_stream *stream)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
@ -119,7 +120,7 @@ static void reset_buffer(struct etna_cmd_stream *stream)
priv->reset_notify(stream, priv->reset_notify_priv);
}
uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream)
drm_public uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream)
{
return etna_cmd_stream_priv(stream)->last_timestamp;
}
@ -149,11 +150,7 @@ static uint32_t bo2idx(struct etna_cmd_stream *stream, struct etna_bo *bo,
pthread_mutex_lock(&idx_lock);
if (!bo->current_stream) {
idx = append_bo(stream, bo);
bo->current_stream = stream;
bo->idx = idx;
} else if (bo->current_stream == stream) {
if (bo->current_stream == stream) {
idx = bo->idx;
} else {
/* slow-path: */
@ -164,6 +161,8 @@ static uint32_t bo2idx(struct etna_cmd_stream *stream, struct etna_bo *bo,
/* not found */
idx = append_bo(stream, bo);
}
bo->current_stream = stream;
bo->idx = idx;
}
pthread_mutex_unlock(&idx_lock);
@ -222,20 +221,21 @@ static void flush(struct etna_cmd_stream *stream, int in_fence_fd,
*out_fence_fd = req.fence_fd;
}
void etna_cmd_stream_flush(struct etna_cmd_stream *stream)
drm_public void etna_cmd_stream_flush(struct etna_cmd_stream *stream)
{
flush(stream, -1, NULL);
reset_buffer(stream);
}
void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd,
int *out_fence_fd)
drm_public void etna_cmd_stream_flush2(struct etna_cmd_stream *stream,
int in_fence_fd,
int *out_fence_fd)
{
flush(stream, in_fence_fd, out_fence_fd);
reset_buffer(stream);
}
void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
drm_public void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
@ -244,7 +244,8 @@ void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
reset_buffer(stream);
}
void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r)
drm_public void etna_cmd_stream_reloc(struct etna_cmd_stream *stream,
const struct etna_reloc *r)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
struct drm_etnaviv_gem_submit_reloc *reloc;
@ -261,7 +262,7 @@ void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_rel
etna_cmd_stream_emit(stream, addr);
}
void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p)
drm_public void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
struct drm_etnaviv_gem_submit_pmr *pmr;

View file

@ -25,8 +25,7 @@
*/
#include <stdlib.h>
#include <linux/stddef.h>
#include <linux/types.h>
#include <sys/types.h>
#include <errno.h>
#include <sys/mman.h>
#include <fcntl.h>
@ -41,7 +40,7 @@
static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER;
struct etna_device *etna_device_new(int fd)
drm_public struct etna_device *etna_device_new(int fd)
{
struct etna_device *dev = calloc(sizeof(*dev), 1);
@ -59,7 +58,7 @@ struct etna_device *etna_device_new(int fd)
/* like etna_device_new() but creates it's own private dup() of the fd
* which is close()d when the device is finalized. */
struct etna_device *etna_device_new_dup(int fd)
drm_public struct etna_device *etna_device_new_dup(int fd)
{
int dup_fd = dup(fd);
struct etna_device *dev = etna_device_new(dup_fd);
@ -72,7 +71,7 @@ struct etna_device *etna_device_new_dup(int fd)
return dev;
}
struct etna_device *etna_device_ref(struct etna_device *dev)
drm_public struct etna_device *etna_device_ref(struct etna_device *dev)
{
atomic_inc(&dev->refcnt);
@ -99,7 +98,7 @@ drm_private void etna_device_del_locked(struct etna_device *dev)
etna_device_del_impl(dev);
}
void etna_device_del(struct etna_device *dev)
drm_public void etna_device_del(struct etna_device *dev)
{
if (!atomic_dec_and_test(&dev->refcnt))
return;
@ -109,7 +108,7 @@ void etna_device_del(struct etna_device *dev)
pthread_mutex_unlock(&table_lock);
}
int etna_device_fd(struct etna_device *dev)
drm_public int etna_device_fd(struct etna_device *dev)
{
return dev->fd;
}

View file

@ -73,6 +73,10 @@ struct drm_etnaviv_timespec {
#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
#define ETNA_MAX_PIPES 4
@ -148,6 +152,11 @@ struct drm_etnaviv_gem_submit_reloc {
* then patching the cmdstream for this entry is skipped. This can
* avoid kernel needing to map/access the cmdstream bo in the common
* case.
* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
* field is interpreted as the fixed location to map the bo into the gpu
* virtual address space. If the kernel is unable to map the buffer at
* this location the submit will fail. This means userspace is responsible
* for the whole gpu virtual address management.
*/
#define ETNA_SUBMIT_BO_READ 0x0001
#define ETNA_SUBMIT_BO_WRITE 0x0002
@ -177,9 +186,11 @@ struct drm_etnaviv_gem_submit_pmr {
#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
#define ETNA_SUBMIT_SOFTPIN 0x0008
#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
ETNA_SUBMIT_FENCE_FD_IN | \
ETNA_SUBMIT_FENCE_FD_OUT)
ETNA_SUBMIT_FENCE_FD_OUT| \
ETNA_SUBMIT_SOFTPIN)
#define ETNA_PIPE_3D 0x00
#define ETNA_PIPE_2D 0x01
#define ETNA_PIPE_VG 0x02

View file

@ -115,8 +115,6 @@ int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns);
struct etna_bo *etna_bo_new(struct etna_device *dev,
uint32_t size, uint32_t flags);
struct etna_bo *etna_bo_from_handle(struct etna_device *dev,
uint32_t handle, uint32_t size);
struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
struct etna_bo *etna_bo_ref(struct etna_bo *bo);

View file

@ -44,7 +44,7 @@ static uint64_t get_param(struct etna_device *dev, uint32_t core, uint32_t param
return req.value;
}
struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core)
drm_public struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core)
{
struct etna_gpu *gpu;
@ -73,12 +73,12 @@ fail:
return NULL;
}
void etna_gpu_del(struct etna_gpu *gpu)
drm_public void etna_gpu_del(struct etna_gpu *gpu)
{
free(gpu);
}
int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
drm_public int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
uint64_t *value)
{
struct etna_device *dev = gpu->dev;

View file

@ -121,7 +121,7 @@ static void etna_perfmon_free_domains(struct etna_perfmon *pm)
}
}
struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe)
drm_public struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe)
{
struct etna_perfmon *pm;
int ret;
@ -147,7 +147,7 @@ fail:
return NULL;
}
void etna_perfmon_del(struct etna_perfmon *pm)
drm_public void etna_perfmon_del(struct etna_perfmon *pm)
{
if (!pm)
return;
@ -156,7 +156,7 @@ void etna_perfmon_del(struct etna_perfmon *pm)
free(pm);
}
struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name)
drm_public struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name)
{
struct etna_perfmon_domain *dom;
@ -170,7 +170,7 @@ struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm
return NULL;
}
struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name)
drm_public struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name)
{
struct etna_perfmon_signal *signal;

View file

@ -26,12 +26,12 @@
#include "etnaviv_priv.h"
int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms)
drm_public int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms)
{
return etna_pipe_wait_ns(pipe, timestamp, ms * 1000000);
}
int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns)
drm_public int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns)
{
struct etna_device *dev = pipe->gpu->dev;
int ret;
@ -55,12 +55,12 @@ int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns)
return 0;
}
void etna_pipe_del(struct etna_pipe *pipe)
drm_public void etna_pipe_del(struct etna_pipe *pipe)
{
free(pipe);
}
struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id)
drm_public struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id)
{
struct etna_pipe *pipe;

View file

@ -150,7 +150,7 @@ struct etna_cmd_stream_priv {
struct etna_bo **bos;
uint32_t nr_bos, max_bos;
/* notify callback if buffer reset happend */
/* notify callback if buffer reset happened */
void (*reset_notify)(struct etna_cmd_stream *stream, void *priv);
void *reset_notify_priv;
};

View file

@ -19,7 +19,7 @@
# SOFTWARE.
libdrm_etnaviv = shared_library(
libdrm_etnaviv = library(
'drm_etnaviv',
[
files(
@ -30,20 +30,19 @@ libdrm_etnaviv = shared_library(
],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
c_args : warn_c_args,
dependencies : [dep_pthread_stubs, dep_rt, dep_atomic_ops],
version : '1.0.0',
c_args : libdrm_c_args,
gnu_symbol_visibility : 'hidden',
dependencies : [dep_threads, dep_rt, dep_atomic_ops],
version : '1.@0@.0'.format(patch_ver),
install : true,
)
install_headers('etnaviv_drmif.h', subdir : 'libdrm')
pkg.generate(
libdrm_etnaviv,
name : 'libdrm_etnaviv',
libraries : libdrm_etnaviv,
subdirs : ['.', 'libdrm'],
version : meson.project_version(),
requires_private : 'libdrm',
description : 'Userspace interface to Tegra kernel DRM services',
)
@ -52,8 +51,14 @@ ext_libdrm_etnaviv = declare_dependency(
include_directories : [inc_drm, include_directories('.')],
)
meson.override_dependency('libdrm_etnaviv', ext_libdrm_etnaviv)
test(
'etnaviv-symbol-check',
prog_bash,
args : [files('etnaviv-symbol-check'), libdrm_etnaviv]
'etnaviv-symbols-check',
symbols_check,
args : [
'--lib', libdrm_etnaviv,
'--symbols-file', files('etnaviv-symbols.txt'),
'--nm', prog_nm.full_path(),
],
)

View file

@ -1,27 +0,0 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
libdrm_exynos_la_LTLIBRARIES = libdrm_exynos.la
libdrm_exynos_ladir = $(libdir)
libdrm_exynos_la_LDFLAGS = -version-number 1:0:0 -no-undefined
libdrm_exynos_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
libdrm_exynos_la_SOURCES = \
exynos_drm.c \
exynos_fimg2d.c \
fimg2d_reg.h
libdrm_exynoscommonincludedir = ${includedir}/exynos
libdrm_exynoscommoninclude_HEADERS = exynos_drm.h exynos_fimg2d.h
libdrm_exynosincludedir = ${includedir}/libdrm
libdrm_exynosinclude_HEADERS = exynos_drmif.h
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_exynos.pc
TESTS = exynos-symbol-check
EXTRA_DIST = $(TESTS)

View file

@ -1,40 +0,0 @@
#!/bin/bash
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.am/libdrm_exynos*_HEADERS
FUNCS=$($NM -D --format=bsd --defined-only ${1-.libs/libdrm_exynos.so} | awk '{print $3}'| while read func; do
( grep -q "^$func$" || echo $func ) <<EOF
__bss_start
_edata
_end
_fini
_init
exynos_bo_create
exynos_bo_destroy
exynos_bo_from_name
exynos_bo_get_info
exynos_bo_get_name
exynos_bo_handle
exynos_bo_map
exynos_device_create
exynos_device_destroy
exynos_prime_fd_to_handle
exynos_prime_handle_to_fd
exynos_vidi_connection
exynos_handle_event
g2d_blend
g2d_copy
g2d_copy_with_scale
g2d_exec
g2d_config_event
g2d_fini
g2d_init
g2d_move
g2d_scale_and_blend
g2d_solid_fill
EOF
done)
test ! -n "$FUNCS" || echo $FUNCS
test ! -n "$FUNCS"

23
exynos/exynos-symbols.txt Normal file
View file

@ -0,0 +1,23 @@
exynos_bo_create
exynos_bo_destroy
exynos_bo_from_name
exynos_bo_get_info
exynos_bo_get_name
exynos_bo_handle
exynos_bo_map
exynos_device_create
exynos_device_destroy
exynos_prime_fd_to_handle
exynos_prime_handle_to_fd
exynos_vidi_connection
exynos_handle_event
g2d_blend
g2d_copy
g2d_copy_with_scale
g2d_exec
g2d_config_event
g2d_fini
g2d_init
g2d_move
g2d_scale_and_blend
g2d_solid_fill

View file

@ -31,7 +31,6 @@
#include <unistd.h>
#include <sys/mman.h>
#include <linux/stddef.h>
#include <xf86drm.h>
@ -48,7 +47,7 @@
*
* if true, return the device object else NULL.
*/
struct exynos_device * exynos_device_create(int fd)
drm_public struct exynos_device * exynos_device_create(int fd)
{
struct exynos_device *dev;
@ -69,7 +68,7 @@ struct exynos_device * exynos_device_create(int fd)
*
* @dev: exynos drm device object.
*/
void exynos_device_destroy(struct exynos_device *dev)
drm_public void exynos_device_destroy(struct exynos_device *dev)
{
free(dev);
}
@ -87,8 +86,8 @@ void exynos_device_destroy(struct exynos_device *dev)
*
* if true, return a exynos buffer object else NULL.
*/
struct exynos_bo * exynos_bo_create(struct exynos_device *dev,
size_t size, uint32_t flags)
drm_public struct exynos_bo * exynos_bo_create(struct exynos_device *dev,
size_t size, uint32_t flags)
{
struct exynos_bo *bo;
struct drm_exynos_gem_create req = {
@ -141,8 +140,8 @@ fail:
*
* if true, return 0 else negative.
*/
int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle,
size_t *size, uint32_t *flags)
drm_public int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle,
size_t *size, uint32_t *flags)
{
int ret;
struct drm_exynos_gem_info req = {
@ -167,7 +166,7 @@ int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle,
*
* @bo: a exynos buffer object to be destroyed.
*/
void exynos_bo_destroy(struct exynos_bo *bo)
drm_public void exynos_bo_destroy(struct exynos_bo *bo)
{
if (!bo)
return;
@ -176,11 +175,7 @@ void exynos_bo_destroy(struct exynos_bo *bo)
munmap(bo->vaddr, bo->size);
if (bo->handle) {
struct drm_gem_close req = {
.handle = bo->handle,
};
drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
drmCloseBufferHandle(bo->dev->fd, bo->handle);
}
free(bo);
@ -199,7 +194,7 @@ void exynos_bo_destroy(struct exynos_bo *bo)
* if true, return a exynos buffer object else NULL.
*
*/
struct exynos_bo *
drm_public struct exynos_bo *
exynos_bo_from_name(struct exynos_device *dev, uint32_t name)
{
struct exynos_bo *bo;
@ -242,7 +237,7 @@ err_free_bo:
*
* if true, return 0 else negative.
*/
int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name)
drm_public int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@ -265,7 +260,7 @@ int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name)
return 0;
}
uint32_t exynos_bo_handle(struct exynos_bo *bo)
drm_public uint32_t exynos_bo_handle(struct exynos_bo *bo)
{
return bo->handle;
}
@ -276,9 +271,9 @@ uint32_t exynos_bo_handle(struct exynos_bo *bo)
* @bo: a exynos buffer object including a gem object handle to be mmapped
* to user space.
*
* if true, user pointer mmaped else NULL.
* if true, user pointer mmapped else NULL.
*/
void *exynos_bo_map(struct exynos_bo *bo)
drm_public void *exynos_bo_map(struct exynos_bo *bo)
{
if (!bo->vaddr) {
struct exynos_device *dev = bo->dev;
@ -315,7 +310,7 @@ void *exynos_bo_map(struct exynos_bo *bo)
*
* @return: 0 on success, -1 on error, and errno will be set
*/
int
drm_public int
exynos_prime_handle_to_fd(struct exynos_device *dev, uint32_t handle, int *fd)
{
return drmPrimeHandleToFD(dev->fd, handle, 0, fd);
@ -330,7 +325,7 @@ exynos_prime_handle_to_fd(struct exynos_device *dev, uint32_t handle, int *fd)
*
* @return: 0 on success, -1 on error, and errno will be set
*/
int
drm_public int
exynos_prime_fd_to_handle(struct exynos_device *dev, int fd, uint32_t *handle)
{
return drmPrimeFDToHandle(dev->fd, fd, handle);
@ -353,7 +348,7 @@ exynos_prime_fd_to_handle(struct exynos_device *dev, int fd, uint32_t *handle)
*
* if true, return 0 else negative.
*/
int
drm_public int
exynos_vidi_connection(struct exynos_device *dev, uint32_t connect,
uint32_t ext, void *edid)
{
@ -394,7 +389,7 @@ exynos_handle_vendor(int fd, struct drm_event *e, void *ctx)
}
}
int
drm_public int
exynos_handle_event(struct exynos_device *dev, struct exynos_event_context *ctx)
{
char buffer[1024];

View file

@ -64,7 +64,7 @@ struct drm_exynos_gem_info {
/**
* A structure for user connection request of virtual display.
*
* @connection: indicate whether doing connetion or not by user.
* @connection: indicate whether doing connection or not by user.
* @extensions: if this value is 1 then the vidi driver would need additional
* 128bytes edid data.
* @edid: the edid data pointer from user side.

View file

@ -46,7 +46,7 @@ struct exynos_device {
* @handle: a gem handle to gem object created.
* @flags: indicate memory allocation and cache attribute types.
* @size: size to the buffer created.
* @vaddr: user space address to a gem buffer mmaped.
* @vaddr: user space address to a gem buffer mmapped.
* @name: a gem global handle from flink request.
*/
struct exynos_bo {

View file

@ -30,7 +30,6 @@
#include <assert.h>
#include <sys/mman.h>
#include <linux/stddef.h>
#include <xf86drm.h>
@ -356,7 +355,7 @@ static int g2d_flush(struct g2d_context *ctx)
*
* fd: a file descriptor to an opened drm device.
*/
struct g2d_context *g2d_init(int fd)
drm_public struct g2d_context *g2d_init(int fd)
{
struct drm_exynos_g2d_get_ver ver;
struct g2d_context *ctx;
@ -384,7 +383,7 @@ struct g2d_context *g2d_init(int fd)
return ctx;
}
void g2d_fini(struct g2d_context *ctx)
drm_public void g2d_fini(struct g2d_context *ctx)
{
free(ctx);
}
@ -400,7 +399,7 @@ void g2d_fini(struct g2d_context *ctx)
* @ctx: a pointer to g2d_context structure.
* @userdata: a pointer to the user data
*/
void g2d_config_event(struct g2d_context *ctx, void *userdata)
drm_public void g2d_config_event(struct g2d_context *ctx, void *userdata)
{
ctx->event_userdata = userdata;
}
@ -410,7 +409,7 @@ void g2d_config_event(struct g2d_context *ctx, void *userdata)
*
* @ctx: a pointer to g2d_context structure.
*/
int g2d_exec(struct g2d_context *ctx)
drm_public int g2d_exec(struct g2d_context *ctx)
{
struct drm_exynos_g2d_exec exec;
int ret;
@ -442,7 +441,7 @@ int g2d_exec(struct g2d_context *ctx)
* @w: width value to buffer filled with given color data.
* @h: height value to buffer filled with given color data.
*/
int
drm_public int
g2d_solid_fill(struct g2d_context *ctx, struct g2d_image *img,
unsigned int x, unsigned int y, unsigned int w,
unsigned int h)
@ -495,7 +494,7 @@ g2d_solid_fill(struct g2d_context *ctx, struct g2d_image *img,
* @w: width value to source and destination buffers.
* @h: height value to source and destination buffers.
*/
int
drm_public int
g2d_copy(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x, unsigned int src_y,
unsigned int dst_x, unsigned dst_y, unsigned int w,
@ -578,7 +577,7 @@ g2d_copy(struct g2d_context *ctx, struct g2d_image *src,
* @w: width of rectangle to move.
* @h: height of rectangle to move.
*/
int
drm_public int
g2d_move(struct g2d_context *ctx, struct g2d_image *img,
unsigned int src_x, unsigned int src_y,
unsigned int dst_x, unsigned dst_y, unsigned int w,
@ -676,7 +675,7 @@ g2d_move(struct g2d_context *ctx, struct g2d_image *img,
* @negative: indicate that it uses color negative to source and
* destination buffers.
*/
int
drm_public int
g2d_copy_with_scale(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x,
unsigned int src_y, unsigned int src_w,
@ -785,7 +784,7 @@ g2d_copy_with_scale(struct g2d_context *ctx, struct g2d_image *src,
* @h: height value to source and destination buffer.
* @op: blend operation type.
*/
int
drm_public int
g2d_blend(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x,
unsigned int src_y, unsigned int dst_x, unsigned int dst_y,
@ -902,7 +901,7 @@ g2d_blend(struct g2d_context *ctx, struct g2d_image *src,
* @dst_h: height value to destination buffer.
* @op: blend operation type.
*/
int
drm_public int
g2d_scale_and_blend(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x, unsigned int src_y,
unsigned int src_w, unsigned int src_h, unsigned int dst_x,

View file

@ -18,14 +18,15 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
libdrm_exynos = shared_library(
libdrm_exynos = library(
'drm_exynos',
[files('exynos_drm.c', 'exynos_fimg2d.c'), config_file],
c_args : warn_c_args,
c_args : libdrm_c_args,
gnu_symbol_visibility : 'hidden',
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs],
version : '1.0.0',
dependencies : [dep_threads],
version : '1.@0@.0'.format(patch_ver),
install : true,
)
@ -37,18 +38,22 @@ ext_libdrm_exynos = declare_dependency(
include_directories : [inc_drm, include_directories('.')],
)
meson.override_dependency('libdrm_exynos', ext_libdrm_exynos)
pkg.generate(
libdrm_exynos,
name : 'libdrm_exynos',
libraries : libdrm_exynos,
subdirs : ['.', 'libdrm', 'exynos'],
version : '0.7',
requires_private : 'libdrm',
description : 'Userspace interface to exynos kernel DRM services',
)
test(
'exynos-symbol-check',
prog_bash,
env : env_test,
args : [files('exynos-symbol-check'), libdrm_exynos]
'exynos-symbols-check',
symbols_check,
args : [
'--lib', libdrm_exynos,
'--symbols-file', files('exynos-symbols.txt'),
'--nm', prog_nm.full_path(),
],
)

View file

@ -1,14 +0,0 @@
LOCAL_PATH := $(call my-dir)
include $(CLEAR_VARS)
# Import variables LIBDRM_FREEDRENO_FILES, LIBDRM_FREEDRENO_H_FILES
include $(LOCAL_PATH)/Makefile.sources
LOCAL_MODULE := libdrm_freedreno
LOCAL_SHARED_LIBRARIES := libdrm
LOCAL_SRC_FILES := $(LIBDRM_FREEDRENO_FILES)
include $(LIBDRM_COMMON_MK)
include $(BUILD_SHARED_LIBRARY)

View file

@ -1,31 +0,0 @@
AUTOMAKE_OPTIONS=subdir-objects
include Makefile.sources
AM_CFLAGS = \
$(WARN_CFLAGS) \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
$(VALGRIND_CFLAGS) \
-I$(top_srcdir)/include/drm
libdrm_freedreno_la_LTLIBRARIES = libdrm_freedreno.la
libdrm_freedreno_ladir = $(libdir)
libdrm_freedreno_la_LDFLAGS = -version-number 1:0:0 -no-undefined
libdrm_freedreno_la_LIBADD = \
../libdrm.la \
@PTHREADSTUBS_LIBS@ \
@CLOCK_LIB@
libdrm_freedreno_la_SOURCES = $(LIBDRM_FREEDRENO_FILES)
if HAVE_FREEDRENO_KGSL
libdrm_freedreno_la_SOURCES += $(LIBDRM_FREEDRENO_KGSL_FILES)
endif
libdrm_freedrenocommonincludedir = ${includedir}/freedreno
libdrm_freedrenocommoninclude_HEADERS = $(LIBDRM_FREEDRENO_H_FILES)
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_freedreno.pc
TESTS = freedreno-symbol-check
EXTRA_DIST = $(TESTS)

View file

@ -1,26 +0,0 @@
LIBDRM_FREEDRENO_FILES := \
freedreno_device.c \
freedreno_pipe.c \
freedreno_priv.h \
freedreno_ringbuffer.c \
freedreno_bo.c \
freedreno_bo_cache.c \
msm/msm_bo.c \
msm/msm_device.c \
msm/msm_drm.h \
msm/msm_pipe.c \
msm/msm_priv.h \
msm/msm_ringbuffer.c
LIBDRM_FREEDRENO_KGSL_FILES := \
kgsl/kgsl_bo.c \
kgsl/kgsl_device.c \
kgsl/kgsl_drm.h \
kgsl/kgsl_pipe.c \
kgsl/kgsl_priv.h \
kgsl/kgsl_ringbuffer.c \
kgsl/msm_kgsl.h
LIBDRM_FREEDRENO_H_FILES := \
freedreno_drmif.h \
freedreno_ringbuffer.h

View file

@ -1,15 +1,3 @@
#!/bin/bash
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_FREEDRENO_H_FILES
FUNCS=$($NM -D --format=bsd --defined-only ${1-.libs/libdrm_freedreno.so} | awk '{print $3}'| while read func; do
( grep -q "^$func$" || echo $func ) <<EOF
__bss_start
_edata
_end
_fini
_init
fd_bo_cpu_fini
fd_bo_cpu_prep
fd_bo_del
@ -41,26 +29,17 @@ fd_pipe_wait
fd_pipe_wait_timeout
fd_ringbuffer_cmd_count
fd_ringbuffer_del
fd_ringbuffer_emit_reloc_ring
fd_ringbuffer_emit_reloc_ring_full
fd_ringbuffer_flush
fd_ringbuffer_grow
fd_ringbuffer_new
fd_ringbuffer_new_flags
fd_ringbuffer_new_object
fd_ringbuffer_ref
fd_ringbuffer_reloc
fd_ringbuffer_reloc2
fd_ringbuffer_reset
fd_ringbuffer_set_parent
fd_ringbuffer_size
fd_ringbuffer_timestamp
fd_ringmarker_del
fd_ringmarker_dwords
fd_ringmarker_flush
fd_ringbuffer_flush2
fd_ringmarker_mark
fd_ringmarker_new
EOF
done)
test ! -n "$FUNCS" || echo $FUNCS
test ! -n "$FUNCS"

View file

@ -62,10 +62,7 @@ static struct fd_bo * bo_from_handle(struct fd_device *dev,
bo = dev->funcs->bo_from_handle(dev, size, handle);
if (!bo) {
struct drm_gem_close req = {
.handle = handle,
};
drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
drmCloseBufferHandle(dev->fd, handle);
return NULL;
}
bo->dev = fd_device_ref(dev);
@ -78,14 +75,15 @@ static struct fd_bo * bo_from_handle(struct fd_device *dev,
return bo;
}
struct fd_bo *
fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
static struct fd_bo *
bo_new(struct fd_device *dev, uint32_t size, uint32_t flags,
struct fd_bo_cache *cache)
{
struct fd_bo *bo = NULL;
uint32_t handle;
int ret;
bo = fd_bo_cache_alloc(&dev->bo_cache, &size, flags);
bo = fd_bo_cache_alloc(cache, &size, flags);
if (bo)
return bo;
@ -95,7 +93,6 @@ fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
pthread_mutex_lock(&table_lock);
bo = bo_from_handle(dev, size, handle);
bo->bo_reuse = TRUE;
pthread_mutex_unlock(&table_lock);
VG_BO_ALLOC(bo);
@ -103,7 +100,30 @@ fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
return bo;
}
struct fd_bo *
drm_public struct fd_bo *
fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
{
struct fd_bo *bo = bo_new(dev, size, flags, &dev->bo_cache);
if (bo)
bo->bo_reuse = BO_CACHE;
return bo;
}
/* internal function to allocate bo's that use the ringbuffer cache
* instead of the normal bo_cache. The purpose is, because cmdstream
* bo's get vmap'd on the kernel side, and that is expensive, we want
* to re-use cmdstream bo's for cmdstream and not unrelated purposes.
*/
drm_private struct fd_bo *
fd_bo_new_ring(struct fd_device *dev, uint32_t size, uint32_t flags)
{
struct fd_bo *bo = bo_new(dev, size, flags, &dev->ring_cache);
if (bo)
bo->bo_reuse = RING_CACHE;
return bo;
}
drm_public struct fd_bo *
fd_bo_from_handle(struct fd_device *dev, uint32_t handle, uint32_t size)
{
struct fd_bo *bo = NULL;
@ -124,7 +144,7 @@ out_unlock:
return bo;
}
struct fd_bo *
drm_public struct fd_bo *
fd_bo_from_dmabuf(struct fd_device *dev, int fd)
{
int ret, size;
@ -156,7 +176,7 @@ out_unlock:
return bo;
}
struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
drm_public struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
{
struct drm_gem_open req = {
.name = name,
@ -191,23 +211,23 @@ out_unlock:
return bo;
}
uint64_t fd_bo_get_iova(struct fd_bo *bo)
drm_public uint64_t fd_bo_get_iova(struct fd_bo *bo)
{
return bo->funcs->iova(bo);
}
void fd_bo_put_iova(struct fd_bo *bo)
drm_public void fd_bo_put_iova(struct fd_bo *bo)
{
/* currently a no-op */
}
struct fd_bo * fd_bo_ref(struct fd_bo *bo)
drm_public struct fd_bo * fd_bo_ref(struct fd_bo *bo)
{
atomic_inc(&bo->refcnt);
return bo;
}
void fd_bo_del(struct fd_bo *bo)
drm_public void fd_bo_del(struct fd_bo *bo)
{
struct fd_device *dev = bo->dev;
@ -216,7 +236,9 @@ void fd_bo_del(struct fd_bo *bo)
pthread_mutex_lock(&table_lock);
if (bo->bo_reuse && (fd_bo_cache_free(&dev->bo_cache, bo) == 0))
if ((bo->bo_reuse == BO_CACHE) && (fd_bo_cache_free(&dev->bo_cache, bo) == 0))
goto out;
if ((bo->bo_reuse == RING_CACHE) && (fd_bo_cache_free(&dev->ring_cache, bo) == 0))
goto out;
bo_del(bo);
@ -238,19 +260,16 @@ drm_private void bo_del(struct fd_bo *bo)
*/
if (bo->handle) {
struct drm_gem_close req = {
.handle = bo->handle,
};
drmHashDelete(bo->dev->handle_table, bo->handle);
if (bo->name)
drmHashDelete(bo->dev->name_table, bo->name);
drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
drmCloseBufferHandle(bo->dev->fd, bo->handle);
}
bo->funcs->destroy(bo);
}
int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
drm_public int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@ -266,7 +285,7 @@ int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
pthread_mutex_lock(&table_lock);
set_name(bo, req.name);
pthread_mutex_unlock(&table_lock);
bo->bo_reuse = FALSE;
bo->bo_reuse = NO_CACHE;
}
*name = bo->name;
@ -274,12 +293,12 @@ int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
return 0;
}
uint32_t fd_bo_handle(struct fd_bo *bo)
drm_public uint32_t fd_bo_handle(struct fd_bo *bo)
{
return bo->handle;
}
int fd_bo_dmabuf(struct fd_bo *bo)
drm_public int fd_bo_dmabuf(struct fd_bo *bo)
{
int ret, prime_fd;
@ -290,17 +309,17 @@ int fd_bo_dmabuf(struct fd_bo *bo)
return ret;
}
bo->bo_reuse = FALSE;
bo->bo_reuse = NO_CACHE;
return prime_fd;
}
uint32_t fd_bo_size(struct fd_bo *bo)
drm_public uint32_t fd_bo_size(struct fd_bo *bo)
{
return bo->size;
}
void * fd_bo_map(struct fd_bo *bo)
drm_public void * fd_bo_map(struct fd_bo *bo)
{
if (!bo->map) {
uint64_t offset;
@ -322,18 +341,18 @@ void * fd_bo_map(struct fd_bo *bo)
}
/* a bit odd to take the pipe as an arg, but it's a, umm, quirk of kgsl.. */
int fd_bo_cpu_prep(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op)
drm_public int fd_bo_cpu_prep(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op)
{
return bo->funcs->cpu_prep(bo, pipe, op);
}
void fd_bo_cpu_fini(struct fd_bo *bo)
drm_public void fd_bo_cpu_fini(struct fd_bo *bo)
{
bo->funcs->cpu_fini(bo);
}
#if !HAVE_FREEDRENO_KGSL
struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
drm_public struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
{
return NULL;
}

View file

@ -49,7 +49,7 @@ add_bucket(struct fd_bo_cache *cache, int size)
* fill in for a bit smoother size curve..
*/
drm_private void
fd_bo_cache_init(struct fd_bo_cache *cache, int course)
fd_bo_cache_init(struct fd_bo_cache *cache, int coarse)
{
unsigned long size, cache_max_size = 64 * 1024 * 1024;
@ -63,13 +63,13 @@ fd_bo_cache_init(struct fd_bo_cache *cache, int course)
*/
add_bucket(cache, 4096);
add_bucket(cache, 4096 * 2);
if (!course)
if (!coarse)
add_bucket(cache, 4096 * 3);
/* Initialize the linked lists for BO reuse cache. */
for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
add_bucket(cache, size);
if (!course) {
if (!coarse) {
add_bucket(cache, size + size * 1 / 4);
add_bucket(cache, size + size * 2 / 4);
add_bucket(cache, size + size * 3 / 4);

View file

@ -38,7 +38,7 @@ static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER;
struct fd_device * kgsl_device_new(int fd);
struct fd_device * msm_device_new(int fd);
struct fd_device * fd_device_new(int fd)
drm_public struct fd_device * fd_device_new(int fd)
{
struct fd_device *dev;
drmVersionPtr version;
@ -82,6 +82,7 @@ out:
dev->handle_table = drmHashCreate();
dev->name_table = drmHashCreate();
fd_bo_cache_init(&dev->bo_cache, FALSE);
fd_bo_cache_init(&dev->ring_cache, TRUE);
return dev;
}
@ -89,7 +90,7 @@ out:
/* like fd_device_new() but creates it's own private dup() of the fd
* which is close()d when the device is finalized.
*/
struct fd_device * fd_device_new_dup(int fd)
drm_public struct fd_device * fd_device_new_dup(int fd)
{
int dup_fd = dup(fd);
struct fd_device *dev = fd_device_new(dup_fd);
@ -100,7 +101,7 @@ struct fd_device * fd_device_new_dup(int fd)
return dev;
}
struct fd_device * fd_device_ref(struct fd_device *dev)
drm_public struct fd_device * fd_device_ref(struct fd_device *dev)
{
atomic_inc(&dev->refcnt);
return dev;
@ -124,7 +125,7 @@ drm_private void fd_device_del_locked(struct fd_device *dev)
fd_device_del_impl(dev);
}
void fd_device_del(struct fd_device *dev)
drm_public void fd_device_del(struct fd_device *dev)
{
if (!atomic_dec_and_test(&dev->refcnt))
return;
@ -133,12 +134,12 @@ void fd_device_del(struct fd_device *dev)
pthread_mutex_unlock(&table_lock);
}
int fd_device_fd(struct fd_device *dev)
drm_public int fd_device_fd(struct fd_device *dev)
{
return dev->fd;
}
enum fd_version fd_device_version(struct fd_device *dev)
drm_public enum fd_version fd_device_version(struct fd_device *dev)
{
return dev->version;
}

View file

@ -33,7 +33,7 @@
* priority of zero is highest priority, and higher numeric values are
* lower priorities
*/
struct fd_pipe *
drm_public struct fd_pipe *
fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio)
{
struct fd_pipe *pipe;
@ -65,37 +65,37 @@ fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio)
return pipe;
}
struct fd_pipe *
drm_public struct fd_pipe *
fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id)
{
return fd_pipe_new2(dev, id, 1);
}
struct fd_pipe * fd_pipe_ref(struct fd_pipe *pipe)
drm_public struct fd_pipe * fd_pipe_ref(struct fd_pipe *pipe)
{
atomic_inc(&pipe->refcnt);
return pipe;
}
void fd_pipe_del(struct fd_pipe *pipe)
drm_public void fd_pipe_del(struct fd_pipe *pipe)
{
if (!atomic_dec_and_test(&pipe->refcnt))
return;
pipe->funcs->destroy(pipe);
}
int fd_pipe_get_param(struct fd_pipe *pipe,
drm_public int fd_pipe_get_param(struct fd_pipe *pipe,
enum fd_param_id param, uint64_t *value)
{
return pipe->funcs->get_param(pipe, param, value);
}
int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp)
drm_public int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp)
{
return fd_pipe_wait_timeout(pipe, timestamp, ~0);
}
int fd_pipe_wait_timeout(struct fd_pipe *pipe, uint32_t timestamp,
drm_public int fd_pipe_wait_timeout(struct fd_pipe *pipe, uint32_t timestamp,
uint64_t timeout)
{
return pipe->funcs->wait(pipe, timestamp, timeout);

View file

@ -98,6 +98,7 @@ struct fd_device {
const struct fd_device_funcs *funcs;
struct fd_bo_cache bo_cache;
struct fd_bo_cache ring_cache;
int closefd; /* call close(fd) upon destruction */
@ -114,10 +115,6 @@ drm_private int fd_bo_cache_free(struct fd_bo_cache *cache, struct fd_bo *bo);
/* for where @table_lock is already held: */
drm_private void fd_device_del_locked(struct fd_device *dev);
enum fd_ringbuffer_flags {
FD_RINGBUFFER_OBJECT = 0x1,
};
struct fd_pipe_funcs {
struct fd_ringbuffer * (*ringbuffer_new)(struct fd_pipe *pipe, uint32_t size,
enum fd_ringbuffer_flags flags);
@ -134,11 +131,6 @@ struct fd_pipe {
const struct fd_pipe_funcs *funcs;
};
struct fd_ringmarker {
struct fd_ringbuffer *ring;
uint32_t *cur;
};
struct fd_ringbuffer_funcs {
void * (*hostptr)(struct fd_ringbuffer *ring);
int (*flush)(struct fd_ringbuffer *ring, uint32_t *last_start,
@ -148,8 +140,7 @@ struct fd_ringbuffer_funcs {
void (*emit_reloc)(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc);
uint32_t (*emit_reloc_ring)(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx,
uint32_t submit_offset, uint32_t size);
struct fd_ringbuffer *target, uint32_t cmd_idx);
uint32_t (*cmd_count)(struct fd_ringbuffer *ring);
void (*destroy)(struct fd_ringbuffer *ring);
};
@ -172,11 +163,19 @@ struct fd_bo {
atomic_t refcnt;
const struct fd_bo_funcs *funcs;
int bo_reuse;
enum {
NO_CACHE = 0,
BO_CACHE = 1,
RING_CACHE = 2,
} bo_reuse;
struct list_head list; /* bucket-list entry */
time_t free_time; /* time when added to bucket-list */
};
drm_private struct fd_bo *fd_bo_new_ring(struct fd_device *dev,
uint32_t size, uint32_t flags);
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define enable_debug 0 /* TODO make dynamic */

View file

@ -32,12 +32,19 @@
#include "freedreno_priv.h"
#include "freedreno_ringbuffer.h"
static struct fd_ringbuffer *
ringbuffer_new(struct fd_pipe *pipe, uint32_t size,
drm_public struct fd_ringbuffer *
fd_ringbuffer_new_flags(struct fd_pipe *pipe, uint32_t size,
enum fd_ringbuffer_flags flags)
{
struct fd_ringbuffer *ring;
/* we can't really support "growable" rb's in general for
* stateobj's since we need a single gpu addr (ie. can't
* do the trick of a chain of IB packets):
*/
if (flags & FD_RINGBUFFER_OBJECT)
assert(size);
ring = pipe->funcs->ringbuffer_new(pipe, size, flags);
if (!ring)
return NULL;
@ -52,35 +59,40 @@ ringbuffer_new(struct fd_pipe *pipe, uint32_t size,
return ring;
}
struct fd_ringbuffer *
drm_public struct fd_ringbuffer *
fd_ringbuffer_new(struct fd_pipe *pipe, uint32_t size)
{
return ringbuffer_new(pipe, size, 0);
return fd_ringbuffer_new_flags(pipe, size, 0);
}
struct fd_ringbuffer *
drm_public struct fd_ringbuffer *
fd_ringbuffer_new_object(struct fd_pipe *pipe, uint32_t size)
{
/* we can't really support "growable" rb's in general for
* stateobj's since we need a single gpu addr (ie. can't
* do the trick of a chain of IB packets):
*/
assert(size);
return ringbuffer_new(pipe, size, FD_RINGBUFFER_OBJECT);
return fd_ringbuffer_new_flags(pipe, size, FD_RINGBUFFER_OBJECT);
}
void fd_ringbuffer_del(struct fd_ringbuffer *ring)
drm_public void fd_ringbuffer_del(struct fd_ringbuffer *ring)
{
if (!(ring->flags & FD_RINGBUFFER_OBJECT))
fd_ringbuffer_reset(ring);
if (!atomic_dec_and_test(&ring->refcnt))
return;
fd_ringbuffer_reset(ring);
ring->funcs->destroy(ring);
}
drm_public struct fd_ringbuffer *
fd_ringbuffer_ref(struct fd_ringbuffer *ring)
{
STATIC_ASSERT(sizeof(ring->refcnt) <= sizeof(ring->__pad));
atomic_inc(&ring->refcnt);
return ring;
}
/* ringbuffers which are IB targets should set the toplevel rb (ie.
* the IB source) as it's parent before emitting reloc's, to ensure
* the bookkeeping works out properly.
*/
void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
drm_public void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
struct fd_ringbuffer *parent)
{
/* state objects should not be parented! */
@ -88,7 +100,7 @@ void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
ring->parent = parent;
}
void fd_ringbuffer_reset(struct fd_ringbuffer *ring)
drm_public void fd_ringbuffer_reset(struct fd_ringbuffer *ring)
{
uint32_t *start = ring->start;
if (ring->pipe->id == FD_PIPE_2D)
@ -98,18 +110,18 @@ void fd_ringbuffer_reset(struct fd_ringbuffer *ring)
ring->funcs->reset(ring);
}
int fd_ringbuffer_flush(struct fd_ringbuffer *ring)
drm_public int fd_ringbuffer_flush(struct fd_ringbuffer *ring)
{
return ring->funcs->flush(ring, ring->last_start, -1, NULL);
}
int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd,
drm_public int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd,
int *out_fence_fd)
{
return ring->funcs->flush(ring, ring->last_start, in_fence_fd, out_fence_fd);
}
void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords)
drm_public void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords)
{
assert(ring->funcs->grow); /* unsupported on kgsl */
@ -125,55 +137,39 @@ void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords)
ring->cur = ring->last_start = ring->start;
}
uint32_t fd_ringbuffer_timestamp(struct fd_ringbuffer *ring)
drm_public uint32_t fd_ringbuffer_timestamp(struct fd_ringbuffer *ring)
{
return ring->last_timestamp;
}
void fd_ringbuffer_reloc(struct fd_ringbuffer *ring,
drm_public void fd_ringbuffer_reloc(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc)
{
assert(ring->pipe->gpu_id < 500);
ring->funcs->emit_reloc(ring, reloc);
}
void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring,
drm_public void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc)
{
ring->funcs->emit_reloc(ring, reloc);
}
void fd_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
struct fd_ringmarker *target, struct fd_ringmarker *end)
{
uint32_t submit_offset, size;
/* This function is deprecated and not supported on 64b devices: */
assert(ring->pipe->gpu_id < 500);
assert(target->ring == end->ring);
submit_offset = offset_bytes(target->cur, target->ring->start);
size = offset_bytes(end->cur, target->cur);
ring->funcs->emit_reloc_ring(ring, target->ring, 0, submit_offset, size);
}
uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring)
drm_public uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring)
{
if (!ring->funcs->cmd_count)
return 1;
return ring->funcs->cmd_count(ring);
}
uint32_t
drm_public uint32_t
fd_ringbuffer_emit_reloc_ring_full(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx)
{
uint32_t size = offset_bytes(target->cur, target->start);
return ring->funcs->emit_reloc_ring(ring, target, cmd_idx, 0, size);
return ring->funcs->emit_reloc_ring(ring, target, cmd_idx);
}
uint32_t
drm_public uint32_t
fd_ringbuffer_size(struct fd_ringbuffer *ring)
{
/* only really needed for stateobj ringbuffers, and won't really
@ -184,45 +180,3 @@ fd_ringbuffer_size(struct fd_ringbuffer *ring)
return offset_bytes(ring->cur, ring->start);
}
/*
* Deprecated ringmarker API:
*/
struct fd_ringmarker * fd_ringmarker_new(struct fd_ringbuffer *ring)
{
struct fd_ringmarker *marker = NULL;
marker = calloc(1, sizeof(*marker));
if (!marker) {
ERROR_MSG("allocation failed");
return NULL;
}
marker->ring = ring;
marker->cur = marker->ring->cur;
return marker;
}
void fd_ringmarker_del(struct fd_ringmarker *marker)
{
free(marker);
}
void fd_ringmarker_mark(struct fd_ringmarker *marker)
{
marker->cur = marker->ring->cur;
}
uint32_t fd_ringmarker_dwords(struct fd_ringmarker *start,
struct fd_ringmarker *end)
{
return end->cur - start->cur;
}
int fd_ringmarker_flush(struct fd_ringmarker *marker)
{
struct fd_ringbuffer *ring = marker->ring;
return ring->funcs->flush(ring, marker->cur, -1, NULL);
}

View file

@ -37,7 +37,29 @@
*/
struct fd_ringbuffer_funcs;
struct fd_ringmarker;
enum fd_ringbuffer_flags {
/* Ringbuffer is a "state object", which is potentially reused
* many times, rather than being used in one-shot mode linked
* to a parent ringbuffer.
*/
FD_RINGBUFFER_OBJECT = 0x1,
/* Hint that the stateobj will be used for streaming state
* that is used once or a few times and then discarded.
*
* For sub-allocation, non streaming stateobj's should be
* sub-allocated from a page size buffer, so one long lived
* state obj doesn't prevent other pages from being freed.
* (Ie. it would be no worse than allocating a page sized
* bo for each small non-streaming stateobj).
*
* But streaming stateobj's could be sub-allocated from a
* larger buffer to reduce the alloc/del overhead.
*/
FD_RINGBUFFER_STREAMING = 0x2,
};
struct fd_ringbuffer {
int size;
@ -52,17 +74,35 @@ struct fd_ringbuffer {
*/
void *user;
uint32_t flags;
enum fd_ringbuffer_flags flags;
/* This is a bit gross, but we can't use atomic_t in exported
* headers. OTOH, we don't need the refcnt to be publicly
* visible. The only reason that this struct is exported is
* because fd_ringbuffer_emit needs to be something that can
* be inlined for performance reasons.
*/
union {
#ifdef HAS_ATOMIC_OPS
atomic_t refcnt;
#endif
uint64_t __pad;
};
};
struct fd_ringbuffer * fd_ringbuffer_new(struct fd_pipe *pipe,
uint32_t size);
will_be_deprecated
struct fd_ringbuffer * fd_ringbuffer_new_object(struct fd_pipe *pipe,
uint32_t size);
struct fd_ringbuffer * fd_ringbuffer_new_flags(struct fd_pipe *pipe,
uint32_t size, enum fd_ringbuffer_flags flags);
struct fd_ringbuffer *fd_ringbuffer_ref(struct fd_ringbuffer *ring);
void fd_ringbuffer_del(struct fd_ringbuffer *ring);
void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
struct fd_ringbuffer *parent);
will_be_deprecated
void fd_ringbuffer_reset(struct fd_ringbuffer *ring);
int fd_ringbuffer_flush(struct fd_ringbuffer *ring);
/* in_fence_fd: -1 for no in-fence, else fence fd
@ -94,18 +134,9 @@ struct fd_reloc {
void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring, const struct fd_reloc *reloc);
will_be_deprecated void fd_ringbuffer_reloc(struct fd_ringbuffer *ring, const struct fd_reloc *reloc);
will_be_deprecated void fd_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
struct fd_ringmarker *target, struct fd_ringmarker *end);
uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring);
uint32_t fd_ringbuffer_emit_reloc_ring_full(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx);
uint32_t fd_ringbuffer_size(struct fd_ringbuffer *ring);
will_be_deprecated struct fd_ringmarker * fd_ringmarker_new(struct fd_ringbuffer *ring);
will_be_deprecated void fd_ringmarker_del(struct fd_ringmarker *marker);
will_be_deprecated void fd_ringmarker_mark(struct fd_ringmarker *marker);
will_be_deprecated uint32_t fd_ringmarker_dwords(struct fd_ringmarker *start,
struct fd_ringmarker *end);
will_be_deprecated int fd_ringmarker_flush(struct fd_ringmarker *marker);
#endif /* FREEDRENO_RINGBUFFER_H_ */

View file

@ -1,4 +1,4 @@
This is a historical discription of what is now the kgsl backend
This is a historical description of what is now the kgsl backend
in libdrm freedreno (before the upstream drm/msm driver). Note
that the kgsl backend requires the "kgsl-drm" shim driver, which
usually is in disrepair (QCOM does not build it for android), and

View file

@ -28,8 +28,6 @@
#include "kgsl_priv.h"
#include <linux/fb.h>
static int set_memtype(struct fd_device *dev, uint32_t handle, uint32_t flags)
{
struct drm_kgsl_gem_memtype req = {
@ -177,7 +175,7 @@ drm_private struct fd_bo * kgsl_bo_from_handle(struct fd_device *dev,
return bo;
}
struct fd_bo *
drm_public struct fd_bo *
fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
{
struct fd_bo *bo;

View file

@ -28,6 +28,7 @@
#include <assert.h>
#include "xf86atomic.h"
#include "freedreno_ringbuffer.h"
#include "kgsl_priv.h"
@ -174,13 +175,12 @@ static void kgsl_ringbuffer_emit_reloc(struct fd_ringbuffer *ring,
}
static uint32_t kgsl_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx,
uint32_t submit_offset, uint32_t size)
struct fd_ringbuffer *target, uint32_t cmd_idx)
{
struct kgsl_ringbuffer *target_ring = to_kgsl_ringbuffer(target);
assert(cmd_idx == 0);
(*ring->cur++) = target_ring->bo->gpuaddr + submit_offset;
return size;
(*ring->cur++) = target_ring->bo->gpuaddr;
return offset_bytes(target->cur, target->start);
}
static void kgsl_ringbuffer_destroy(struct fd_ringbuffer *ring)
@ -216,6 +216,8 @@ drm_private struct fd_ringbuffer * kgsl_ringbuffer_new(struct fd_pipe *pipe,
}
ring = &kgsl_ring->base;
atomic_set(&ring->refcnt, 1);
ring->funcs = &funcs;
ring->size = size;

View file

@ -39,14 +39,14 @@ if with_freedreno_kgsl
)
endif
libdrm_freedreno = shared_library(
libdrm_freedreno = library(
'drm_freedreno',
[files_freedreno, config_file],
c_args : warn_c_args,
c_args : libdrm_c_args,
include_directories : [inc_root, inc_drm],
dependencies : [dep_valgrind, dep_pthread_stubs, dep_rt, dep_atomic_ops],
dependencies : [dep_valgrind, dep_threads, dep_rt, dep_atomic_ops],
link_with : libdrm,
version : '1.0.0',
version : '1.@0@.0'.format(patch_ver),
install : true,
)
@ -55,23 +55,26 @@ ext_libdrm_freedreno = declare_dependency(
include_directories : [inc_drm, include_directories('.')],
)
meson.override_dependency('libdrm_freedreno', ext_libdrm_freedreno)
install_headers(
'freedreno_drmif.h', 'freedreno_ringbuffer.h',
subdir : 'freedreno'
)
pkg.generate(
libdrm_freedreno,
name : 'libdrm_freedreno',
libraries : libdrm_freedreno,
subdirs : ['.', 'libdrm', 'freedreno'],
version : meson.project_version(),
requires_private : 'libdrm',
description : 'Userspace interface to freedreno kernel DRM services',
)
test(
'freedreno-symbol-check',
prog_bash,
env : env_test,
args : [files('freedreno-symbol-check'), libdrm_freedreno]
'freedreno-symbols-check',
symbols_check,
args : [
'--lib', libdrm_freedreno,
'--symbols-file', files('freedreno-symbols.txt'),
'--nm', prog_nm.full_path(),
],
)

View file

@ -35,7 +35,6 @@
static void msm_device_destroy(struct fd_device *dev)
{
struct msm_device *msm_dev = to_msm_device(dev);
fd_bo_cache_cleanup(&msm_dev->ring_cache, 0);
free(msm_dev);
}
@ -58,8 +57,6 @@ drm_private struct fd_device * msm_device_new(int fd)
dev = &msm_dev->base;
dev->funcs = &funcs;
fd_bo_cache_init(&msm_dev->ring_cache, TRUE);
dev->bo_size = sizeof(struct msm_bo);
return dev;

View file

@ -138,6 +138,12 @@ static void msm_pipe_destroy(struct fd_pipe *pipe)
{
struct msm_pipe *msm_pipe = to_msm_pipe(pipe);
close_submitqueue(pipe, msm_pipe->queue_id);
if (msm_pipe->suballoc_ring) {
fd_ringbuffer_del(msm_pipe->suballoc_ring);
msm_pipe->suballoc_ring = NULL;
}
free(msm_pipe);
}

View file

@ -57,6 +57,17 @@ struct msm_pipe {
uint32_t gmem;
uint32_t chip_id;
uint32_t queue_id;
/* Allow for sub-allocation of stateobj ring buffers (ie. sharing
* the same underlying bo)..
*
* This takes advantage of each context having it's own fd_pipe,
* so we don't have to worry about access from multiple threads.
*
* We also rely on previous stateobj having been fully constructed
* so we can reclaim extra space at it's end.
*/
struct fd_ringbuffer *suballoc_ring;
};
static inline struct msm_pipe * to_msm_pipe(struct fd_pipe *x)

View file

@ -29,6 +29,7 @@
#include <assert.h>
#include <inttypes.h>
#include "xf86atomic.h"
#include "freedreno_ringbuffer.h"
#include "msm_priv.h"
@ -45,13 +46,14 @@ struct msm_cmd {
DECLARE_ARRAY(struct drm_msm_gem_submit_reloc, relocs);
uint32_t size;
/* has cmd already been added to parent rb's submit.cmds table? */
int is_appended_to_submit;
};
struct msm_ringbuffer {
struct fd_ringbuffer base;
atomic_t refcnt;
/* submit ioctl related tables:
* Note that bos and cmds are tracked by the parent ringbuffer, since
* that is global to the submit ioctl call. The reloc's table is tracked
@ -72,7 +74,7 @@ struct msm_ringbuffer {
/* should have matching entries in submit.cmds: */
DECLARE_ARRAY(struct msm_cmd *, cmds);
/* List of physical cmdstream buffers (msm_cmd) assocated with this
/* List of physical cmdstream buffers (msm_cmd) associated with this
* logical fd_ringbuffer.
*
* Note that this is different from msm_ringbuffer::cmds (which
@ -86,10 +88,24 @@ struct msm_ringbuffer {
int is_growable;
unsigned cmd_count;
unsigned offset; /* for sub-allocated stateobj rb's */
unsigned seqno;
/* maps fd_bo to idx: */
void *bo_table;
/* maps msm_cmd to drm_msm_gem_submit_cmd in parent rb. Each rb has a
* list of msm_cmd's which correspond to each chunk of cmdstream in
* a 'growable' rb. For each of those we need to create one
* drm_msm_gem_submit_cmd in the parent rb which collects the state
* for the submit ioctl. Because we can have multiple IB's to the same
* target rb (for example, or same stateobj emit multiple times), and
* because in theory we can have multiple different rb's that have a
* reference to a given target, we need a hashtable to track this per
* rb.
*/
void *cmd_table;
};
static inline struct msm_ringbuffer * to_msm_ringbuffer(struct fd_ringbuffer *x)
@ -97,57 +113,28 @@ static inline struct msm_ringbuffer * to_msm_ringbuffer(struct fd_ringbuffer *x)
return (struct msm_ringbuffer *)x;
}
static void msm_ringbuffer_unref(struct fd_ringbuffer *ring);
static void msm_ringbuffer_ref(struct fd_ringbuffer *ring);
#define INIT_SIZE 0x1000
static pthread_mutex_t idx_lock = PTHREAD_MUTEX_INITIALIZER;
drm_private extern pthread_mutex_t table_lock;
static void ring_bo_del(struct fd_device *dev, struct fd_bo *bo)
static struct msm_cmd *current_cmd(struct fd_ringbuffer *ring)
{
int ret;
pthread_mutex_lock(&table_lock);
ret = fd_bo_cache_free(&to_msm_device(dev)->ring_cache, bo);
pthread_mutex_unlock(&table_lock);
if (ret == 0)
return;
fd_bo_del(bo);
}
static struct fd_bo * ring_bo_new(struct fd_device *dev, uint32_t size)
{
struct fd_bo *bo;
bo = fd_bo_cache_alloc(&to_msm_device(dev)->ring_cache, &size, 0);
if (bo)
return bo;
bo = fd_bo_new(dev, size, 0);
if (!bo)
return NULL;
/* keep ringbuffer bo's out of the normal bo cache: */
bo->bo_reuse = FALSE;
return bo;
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
assert(!LIST_IS_EMPTY(&msm_ring->cmd_list));
return LIST_LAST_ENTRY(&msm_ring->cmd_list, struct msm_cmd, list);
}
static void ring_cmd_del(struct msm_cmd *cmd)
{
if (cmd->ring_bo)
ring_bo_del(cmd->ring->pipe->dev, cmd->ring_bo);
fd_bo_del(cmd->ring_bo);
list_del(&cmd->list);
to_msm_ringbuffer(cmd->ring)->cmd_count--;
free(cmd->relocs);
free(cmd);
}
static struct msm_cmd * ring_cmd_new(struct fd_ringbuffer *ring, uint32_t size)
static struct msm_cmd * ring_cmd_new(struct fd_ringbuffer *ring, uint32_t size,
enum fd_ringbuffer_flags flags)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
struct msm_cmd *cmd = calloc(1, sizeof(*cmd));
@ -156,7 +143,48 @@ static struct msm_cmd * ring_cmd_new(struct fd_ringbuffer *ring, uint32_t size)
return NULL;
cmd->ring = ring;
cmd->ring_bo = ring_bo_new(ring->pipe->dev, size);
/* TODO separate suballoc buffer for small non-streaming state, using
* smaller page-sized backing bo's.
*/
if (flags & FD_RINGBUFFER_STREAMING) {
struct msm_pipe *msm_pipe = to_msm_pipe(ring->pipe);
unsigned suballoc_offset = 0;
struct fd_bo *suballoc_bo = NULL;
if (msm_pipe->suballoc_ring) {
struct msm_ringbuffer *suballoc_ring = to_msm_ringbuffer(msm_pipe->suballoc_ring);
assert(msm_pipe->suballoc_ring->flags & FD_RINGBUFFER_OBJECT);
assert(suballoc_ring->cmd_count == 1);
suballoc_bo = current_cmd(msm_pipe->suballoc_ring)->ring_bo;
suballoc_offset = fd_ringbuffer_size(msm_pipe->suballoc_ring) +
suballoc_ring->offset;
suballoc_offset = ALIGN(suballoc_offset, 0x10);
if ((size + suballoc_offset) > suballoc_bo->size) {
suballoc_bo = NULL;
}
}
if (!suballoc_bo) {
cmd->ring_bo = fd_bo_new_ring(ring->pipe->dev, 0x8000, 0);
msm_ring->offset = 0;
} else {
cmd->ring_bo = fd_bo_ref(suballoc_bo);
msm_ring->offset = suballoc_offset;
}
if (msm_pipe->suballoc_ring)
fd_ringbuffer_del(msm_pipe->suballoc_ring);
msm_pipe->suballoc_ring = fd_ringbuffer_ref(ring);
} else {
cmd->ring_bo = fd_bo_new_ring(ring->pipe->dev, size, 0);
}
if (!cmd->ring_bo)
goto fail;
@ -170,13 +198,6 @@ fail:
return NULL;
}
static struct msm_cmd *current_cmd(struct fd_ringbuffer *ring)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
assert(!LIST_IS_EMPTY(&msm_ring->cmd_list));
return LIST_LAST_ENTRY(&msm_ring->cmd_list, struct msm_cmd, list);
}
static uint32_t append_bo(struct fd_ringbuffer *ring, struct fd_bo *bo)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
@ -228,31 +249,43 @@ static uint32_t bo2idx(struct fd_ringbuffer *ring, struct fd_bo *bo, uint32_t fl
return idx;
}
static int check_cmd_bo(struct fd_ringbuffer *ring,
struct drm_msm_gem_submit_cmd *cmd, struct fd_bo *bo)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
return msm_ring->submit.bos[cmd->submit_idx].handle == bo->handle;
}
/* Ensure that submit has corresponding entry in cmds table for the
* target cmdstream buffer:
*
* Returns TRUE if new cmd added (else FALSE if it was already in
* the cmds table)
*/
static void get_cmd(struct fd_ringbuffer *ring, struct msm_cmd *target_cmd,
static int get_cmd(struct fd_ringbuffer *ring, struct msm_cmd *target_cmd,
uint32_t submit_offset, uint32_t size, uint32_t type)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
struct drm_msm_gem_submit_cmd *cmd;
uint32_t i;
void *val;
/* figure out if we already have a cmd buf: */
for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
if (!msm_ring->cmd_table)
msm_ring->cmd_table = drmHashCreate();
/* figure out if we already have a cmd buf.. short-circuit hash
* lookup if:
* - target cmd has never been added to submit.cmds
* - target cmd is not a streaming stateobj (which unlike longer
* lived CSO stateobj, is not expected to be reused with multiple
* submits)
*/
if (target_cmd->is_appended_to_submit &&
!(target_cmd->ring->flags & FD_RINGBUFFER_STREAMING) &&
!drmHashLookup(msm_ring->cmd_table, (unsigned long)target_cmd, &val)) {
i = VOID2U64(val);
cmd = &msm_ring->submit.cmds[i];
if ((cmd->submit_offset == submit_offset) &&
(cmd->size == size) &&
(cmd->type == type) &&
check_cmd_bo(ring, cmd, target_cmd->ring_bo))
return;
assert(cmd->submit_offset == submit_offset);
assert(cmd->size == size);
assert(cmd->type == type);
assert(msm_ring->submit.bos[cmd->submit_idx].handle ==
target_cmd->ring_bo->handle);
return FALSE;
}
/* create cmd buf if not: */
@ -266,27 +299,23 @@ static void get_cmd(struct fd_ringbuffer *ring, struct msm_cmd *target_cmd,
cmd->size = size;
cmd->pad = 0;
target_cmd->is_appended_to_submit = TRUE;
if (!(target_cmd->ring->flags & FD_RINGBUFFER_STREAMING)) {
drmHashInsert(msm_ring->cmd_table, (unsigned long)target_cmd,
U642VOID(i));
}
target_cmd->size = size;
return TRUE;
}
static void * msm_ringbuffer_hostptr(struct fd_ringbuffer *ring)
{
return fd_bo_map(current_cmd(ring)->ring_bo);
}
static uint32_t find_next_reloc_idx(struct msm_cmd *msm_cmd,
uint32_t start, uint32_t offset)
{
uint32_t i;
/* a binary search would be more clever.. */
for (i = start; i < msm_cmd->nr_relocs; i++) {
struct drm_msm_gem_submit_reloc *reloc = &msm_cmd->relocs[i];
if (reloc->submit_offset >= offset)
return i;
}
return i;
struct msm_cmd *cmd = current_cmd(ring);
uint8_t *base = fd_bo_map(cmd->ring_bo);
return base + to_msm_ringbuffer(ring)->offset;
}
static void delete_cmds(struct msm_ringbuffer *msm_ring)
@ -305,16 +334,20 @@ static void flush_reset(struct fd_ringbuffer *ring)
for (i = 0; i < msm_ring->nr_bos; i++) {
struct msm_bo *msm_bo = to_msm_bo(msm_ring->bos[i]);
if (!msm_bo)
continue;
msm_bo->current_ring_seqno = 0;
fd_bo_del(&msm_bo->base);
}
/* for each of the cmd buffers, clear their reloc's: */
for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
struct msm_cmd *target_cmd = msm_ring->cmds[i];
if (target_cmd->ring->flags & FD_RINGBUFFER_OBJECT)
for (i = 0; i < msm_ring->nr_cmds; i++) {
struct msm_cmd *msm_cmd = msm_ring->cmds[i];
if (msm_cmd->ring == ring)
continue;
target_cmd->nr_relocs = 0;
if (msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT)
fd_ringbuffer_del(msm_cmd->ring);
}
msm_ring->submit.nr_cmds = 0;
@ -327,6 +360,11 @@ static void flush_reset(struct fd_ringbuffer *ring)
msm_ring->bo_table = NULL;
}
if (msm_ring->cmd_table) {
drmHashDestroy(msm_ring->cmd_table);
msm_ring->cmd_table = NULL;
}
if (msm_ring->is_growable) {
delete_cmds(msm_ring);
} else {
@ -398,6 +436,24 @@ handle_stateobj_relocs(struct fd_ringbuffer *parent, struct fd_ringbuffer *state
relocs[i].reloc_idx = bo2idx(parent, bo, flags);
}
/* stateobj rb's could have reloc's to other stateobj rb's which didn't
* get propagated to the parent rb at _emit_reloc_ring() time (because
* the parent wasn't known then), so fix that up now:
*/
for (i = 0; i < msm_ring->nr_cmds; i++) {
struct msm_cmd *msm_cmd = msm_ring->cmds[i];
struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
if (msm_ring->cmds[i]->ring == stateobj)
continue;
assert(msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT);
if (get_cmd(parent, msm_cmd, cmd->submit_offset, cmd->size, cmd->type)) {
fd_ringbuffer_ref(msm_cmd->ring);
}
}
return relocs;
}
@ -405,9 +461,10 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start
int in_fence_fd, int *out_fence_fd)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
struct msm_pipe *msm_pipe = to_msm_pipe(ring->pipe);
struct drm_msm_gem_submit req = {
.flags = to_msm_pipe(ring->pipe)->pipe,
.queueid = to_msm_pipe(ring->pipe)->queue_id,
.flags = msm_pipe->pipe,
.queueid = msm_pipe->queue_id,
};
uint32_t i;
int ret;
@ -427,12 +484,10 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start
/* for each of the cmd's fix up their reloc's: */
for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
struct msm_cmd *msm_cmd = msm_ring->cmds[i];
uint32_t a = find_next_reloc_idx(msm_cmd, 0, cmd->submit_offset);
uint32_t b = find_next_reloc_idx(msm_cmd, a, cmd->submit_offset + cmd->size);
struct drm_msm_gem_submit_reloc *relocs = &msm_cmd->relocs[a];
unsigned nr_relocs = (b > a) ? b - a : 0;
struct drm_msm_gem_submit_reloc *relocs = msm_cmd->relocs;
struct drm_msm_gem_submit_cmd *cmd;
unsigned nr_relocs = msm_cmd->nr_relocs;
/* for reusable stateobjs, the reloc table has reloc_idx that
* points into it's own private bos table, rather than the global
@ -445,6 +500,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start
relocs, nr_relocs);
}
cmd = &msm_ring->submit.cmds[i];
cmd->relocs = VOID2U64(relocs);
cmd->nr_relocs = nr_relocs;
}
@ -479,7 +535,6 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start
struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
struct msm_cmd *msm_cmd = msm_ring->cmds[i];
if (msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT) {
msm_ringbuffer_unref(msm_cmd->ring);
free(U642VOID(cmd->relocs));
}
}
@ -493,7 +548,7 @@ static void msm_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t size)
{
assert(to_msm_ringbuffer(ring)->is_growable);
finalize_current_cmd(ring, ring->last_start);
ring_cmd_new(ring, size);
ring_cmd_new(ring, size, 0);
}
static void msm_ringbuffer_reset(struct fd_ringbuffer *ring)
@ -517,7 +572,8 @@ static void msm_ringbuffer_emit_reloc(struct fd_ringbuffer *ring,
reloc->reloc_offset = r->offset;
reloc->or = r->or;
reloc->shift = r->shift;
reloc->submit_offset = offset_bytes(ring->cur, ring->start);
reloc->submit_offset = offset_bytes(ring->cur, ring->start) +
to_msm_ringbuffer(ring)->offset;
addr = msm_bo->presumed;
if (reloc->shift < 0)
@ -542,7 +598,8 @@ static void msm_ringbuffer_emit_reloc(struct fd_ringbuffer *ring,
reloc_hi->reloc_offset = r->offset;
reloc_hi->or = r->orhi;
reloc_hi->shift = r->shift - 32;
reloc_hi->submit_offset = offset_bytes(ring->cur, ring->start);
reloc_hi->submit_offset = offset_bytes(ring->cur, ring->start) +
to_msm_ringbuffer(ring)->offset;
addr = msm_bo->presumed >> 32;
if (reloc_hi->shift < 0)
@ -554,13 +611,16 @@ static void msm_ringbuffer_emit_reloc(struct fd_ringbuffer *ring,
}
static uint32_t msm_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx,
uint32_t submit_offset, uint32_t size)
struct fd_ringbuffer *target, uint32_t cmd_idx)
{
struct msm_cmd *cmd = NULL;
struct msm_ringbuffer *msm_target = to_msm_ringbuffer(target);
uint32_t idx = 0;
int added_cmd = FALSE;
uint32_t size;
uint32_t submit_offset = msm_target->offset;
LIST_FOR_EACH_ENTRY(cmd, &to_msm_ringbuffer(target)->cmd_list, list) {
LIST_FOR_EACH_ENTRY(cmd, &msm_target->cmd_list, list) {
if (idx == cmd_idx)
break;
idx++;
@ -568,7 +628,7 @@ static uint32_t msm_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
assert(cmd && (idx == cmd_idx));
if (idx < (to_msm_ringbuffer(target)->cmd_count - 1)) {
if (idx < (msm_target->cmd_count - 1)) {
/* All but the last cmd buffer is fully "baked" (ie. already has
* done get_cmd() to add it to the cmds table). But in this case,
* the size we get is invalid (since it is calculated from the
@ -577,7 +637,9 @@ static uint32_t msm_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
size = cmd->size;
} else {
struct fd_ringbuffer *parent = ring->parent ? ring->parent : ring;
get_cmd(parent, cmd, submit_offset, size, MSM_SUBMIT_CMD_IB_TARGET_BUF);
size = offset_bytes(target->cur, target->start);
added_cmd = get_cmd(parent, cmd, submit_offset, size,
MSM_SUBMIT_CMD_IB_TARGET_BUF);
}
msm_ringbuffer_emit_reloc(ring, &(struct fd_reloc){
@ -590,8 +652,8 @@ static uint32_t msm_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
* being flushed), mesa can't really guarantee that a stateobj isn't
* destroyed after emitted but before flush, so we must hold a ref:
*/
if (target->flags & FD_RINGBUFFER_OBJECT) {
msm_ringbuffer_ref(target);
if (added_cmd && (target->flags & FD_RINGBUFFER_OBJECT)) {
fd_ringbuffer_ref(target);
}
return size;
@ -602,13 +664,10 @@ static uint32_t msm_ringbuffer_cmd_count(struct fd_ringbuffer *ring)
return to_msm_ringbuffer(ring)->cmd_count;
}
static void msm_ringbuffer_unref(struct fd_ringbuffer *ring)
static void msm_ringbuffer_destroy(struct fd_ringbuffer *ring)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
if (!atomic_dec_and_test(&msm_ring->refcnt))
return;
flush_reset(ring);
delete_cmds(msm_ring);
@ -619,12 +678,6 @@ static void msm_ringbuffer_unref(struct fd_ringbuffer *ring)
free(msm_ring);
}
static void msm_ringbuffer_ref(struct fd_ringbuffer *ring)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
atomic_inc(&msm_ring->refcnt);
}
static const struct fd_ringbuffer_funcs funcs = {
.hostptr = msm_ringbuffer_hostptr,
.flush = msm_ringbuffer_flush,
@ -633,7 +686,7 @@ static const struct fd_ringbuffer_funcs funcs = {
.emit_reloc = msm_ringbuffer_emit_reloc,
.emit_reloc_ring = msm_ringbuffer_emit_reloc_ring,
.cmd_count = msm_ringbuffer_cmd_count,
.destroy = msm_ringbuffer_unref,
.destroy = msm_ringbuffer_destroy,
};
drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe,
@ -656,14 +709,15 @@ drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe,
list_inithead(&msm_ring->cmd_list);
msm_ring->seqno = ++to_msm_device(pipe->dev)->ring_cnt;
atomic_set(&msm_ring->refcnt, 1);
ring = &msm_ring->base;
atomic_set(&ring->refcnt, 1);
ring->funcs = &funcs;
ring->size = size;
ring->pipe = pipe; /* needed in ring_cmd_new() */
ring_cmd_new(ring, size);
ring_cmd_new(ring, size, flags);
return ring;
}

84
gen_table_fourcc.py Normal file
View file

@ -0,0 +1,84 @@
#!/usr/bin/env python3
# Copyright 2021 Collabora, Ltd.
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files (the
# "Software"), to deal in the Software without restriction, including
# without limitation the rights to use, copy, modify, merge, publish,
# distribute, sublicense, and/or sell copies of the Software, and to
# permit persons to whom the Software is furnished to do so, subject to
# the following conditions:
#
# The above copyright notice and this permission notice (including the
# next paragraph) shall be included in all copies or substantial
# portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
# Helper script that reads drm_fourcc.h and writes a static table with the
# simpler format token modifiers
import sys
import re
filename = sys.argv[1]
towrite = sys.argv[2]
fm_re = {
'intel': r'^#define I915_FORMAT_MOD_(\w+)',
'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)'
}
def print_fm_intel(f, f_mod):
f.write(' {{ DRM_MODIFIER_INTEL({}, {}) }},\n'.format(f_mod, f_mod))
# generic write func
def print_fm(f, vendor, mod, f_name):
f.write(' {{ DRM_MODIFIER({}, {}, {}) }},\n'.format(vendor, mod, f_name))
with open(filename, "r") as f:
data = f.read()
for k, v in fm_re.items():
fm_re[k] = re.findall(v, data, flags=re.M)
with open(towrite, "w") as f:
f.write('''\
/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify
that script instead of adding here entries manually! */
static const struct drmFormatModifierInfo drm_format_modifier_table[] = {
''')
f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID) },\n')
f.write(' { DRM_MODIFIER_LINEAR(NONE, LINEAR) },\n')
for entry in fm_re['intel']:
print_fm_intel(f, entry)
for entry in fm_re['others']:
(vendor, mod) = entry.split('_', 1)
if vendor == 'ARM' and (mod == 'TYPE_AFBC' or mod == 'TYPE_MISC' or mod == 'TYPE_AFRC'):
continue
print_fm(f, vendor, mod, mod)
f.write('''\
};
''')
f.write('''\
static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = {
''')
for entry in fm_re['vendors']:
f.write(" {{ DRM_FORMAT_MOD_VENDOR_{}, \"{}\" }},\n".format(entry, entry))
f.write('''\
};
''')

View file

@ -71,7 +71,7 @@ Note: One should not do _any_ changes to the files apart from the steps below.
In order to update the files do the following:
- Switch to a Linux kernel tree/branch which is not rebased.
For example: airlied/drm-next
For example: drm-next (https://gitlab.freedesktop.org/drm/kernel/)
- Install the headers via `make headers_install' to a separate location.
- Copy the drm header[s] + git add + git commit.
- Note: Your commit message must include:
@ -122,11 +122,6 @@ omap_drm.h (living in $TOP/omap)
- License mismatch, missing DRM_IOCTL_OMAP_GEM_NEW and related struct
Status: ?
msm_drm.h (located in $TOP/freedreno/msm/)
- License mismatch, missing MSM_PIPE_*, MSM_SUBMIT_*. Renamed
drm_msm_gem_submit::flags, missing drm_msm_gem_submit::fence_fd.
Status: ?
exynos_drm.h (living in $TOP/exynos)
- License mismatch, now using fixed size ints (but not everywhere). Lots of
new stuff.

View file

@ -54,6 +54,9 @@ extern "C" {
#define DRM_AMDGPU_VM 0x13
#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
#define DRM_AMDGPU_SCHED 0x15
#define DRM_AMDGPU_USERQ 0x16
#define DRM_AMDGPU_USERQ_SIGNAL 0x17
#define DRM_AMDGPU_USERQ_WAIT 0x18
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@ -71,13 +74,50 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
/**
* DOC: memory domains
*
* %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
* Memory in this pool could be swapped out to disk if there is pressure.
*
* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
* pages of system memory, allows GPU access system memory in a linearized
* fashion.
*
* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
* carved out by the BIOS.
*
* %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
* across shader threads.
*
* %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
* execution of all the waves on a device.
*
* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
* for appending data.
*
* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
* signalling user mode queues.
*/
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
AMDGPU_GEM_DOMAIN_GTT | \
AMDGPU_GEM_DOMAIN_VRAM | \
AMDGPU_GEM_DOMAIN_GDS | \
AMDGPU_GEM_DOMAIN_GWS | \
AMDGPU_GEM_DOMAIN_OA | \
AMDGPU_GEM_DOMAIN_DOORBELL)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@ -87,14 +127,56 @@ extern "C" {
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
/* Flag that create shadow bo(GTT) while allocating vram bo */
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
/* Flag that BO sharing will be explicitly synchronized */
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
/* Flag that indicates allocating MQD gart on GFX9, where the mtype
* for the second page onward should be set to NC. It should never
* be used by user space applications.
*/
#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
/* Flag that BO may contain sensitive data that must be wiped before
* releasing the memory
*/
#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
/* Flag that BO will be encrypted and that the TMZ bit should be
* set in the PTEs when mapping this buffer via GPUVM or
* accessing it with various hw blocks
*/
#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
/* Flag that BO will be used only in preemptible context, which does
* not require GTT memory accounting
*/
#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
/* Flag that BO can be discarded under memory pressure without keeping the
* content.
*/
#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
/* Flag that BO is shared coherently between multiple devices or CPU threads.
* May depend on GPU instructions to flush caches to system scope explicitly.
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
/* Flag that BO should not be cached by GPU. Coherent without having to flush
* GPU caches explicitly
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
/* Flag that BO should be coherent across devices when using device-level
* atomics. May depend on GPU instructions to flush caches to device scope
* explicitly, promoting them to system scope automatically.
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@ -161,6 +243,8 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_FREE_CTX 2
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0
@ -171,28 +255,45 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
/* indicate gpu reset occured after ctx created */
/* indicate gpu reset occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
/* indicate vram lost occured after ctx created */
/* indicate vram lost occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
/* indicate some errors are detected by RAS */
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* indicate that the reset hasn't completed yet */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
#define AMDGPU_CTX_PRIORITY_LOW -512
#define AMDGPU_CTX_PRIORITY_NORMAL 0
/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
/*
* When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
* CAP_SYS_NICE or DRM_MASTER
*/
#define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
/* select a stable profiling pstate for perfmon tools */
#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
/** For future use, no flags defined so far */
/** Flags */
__u32 flags;
__u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */
__s32 priority;
};
@ -210,6 +311,11 @@ union drm_amdgpu_ctx_out {
/** Reset status since the last call of the ioctl. */
__u32 reset_status;
} state;
struct {
__u32 flags;
__u32 _pad;
} pstate;
};
union drm_amdgpu_ctx {
@ -217,6 +323,261 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
/* user queue IOCTL operations */
#define AMDGPU_USERQ_OP_CREATE 1
#define AMDGPU_USERQ_OP_FREE 2
/* queue priority levels */
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
/* for queues that need access to protected content */
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
/*
* This structure is a container to pass input configuration
* info for all supported userqueue related operations.
* For operation AMDGPU_USERQ_OP_CREATE: user is expected
* to set all fields, excep the parameter 'queue_id'.
* For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
* to be set is 'queue_id', eveything else is ignored.
*/
struct drm_amdgpu_userq_in {
/** AMDGPU_USERQ_OP_* */
__u32 op;
/** Queue id passed for operation USERQ_OP_FREE */
__u32 queue_id;
/** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
__u32 ip_type;
/**
* @doorbell_handle: the handle of doorbell GEM object
* associated to this userqueue client.
*/
__u32 doorbell_handle;
/**
* @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
* Kernel will generate absolute doorbell offset using doorbell_handle
* and doorbell_offset in the doorbell bo.
*/
__u32 doorbell_offset;
/**
* @flags: flags used for queue parameters
*/
__u32 flags;
/**
* @queue_va: Virtual address of the GPU memory which holds the queue
* object. The queue holds the workload packets.
*/
__u64 queue_va;
/**
* @queue_size: Size of the queue in bytes, this needs to be 256-byte
* aligned.
*/
__u64 queue_size;
/**
* @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
* This object must be at least 8 byte in size and aligned to 8-byte offset.
*/
__u64 rptr_va;
/**
* @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
* This object must be at least 8 byte in size and aligned to 8-byte offset.
*
* Queue, RPTR and WPTR can come from the same object, as long as the size
* and alignment related requirements are met.
*/
__u64 wptr_va;
/**
* @mqd: MQD (memory queue descriptor) is a set of parameters which allow
* the GPU to uniquely define and identify a usermode queue.
*
* MQD data can be of different size for different GPU IP/engine and
* their respective versions/revisions, so this points to a __u64 *
* which holds IP specific MQD of this usermode queue.
*/
__u64 mqd;
/**
* @size: size of MQD data in bytes, it must match the MQD structure
* size of the respective engine/revision defined in UAPI for ex, for
* gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
*/
__u64 mqd_size;
};
/* The structure to carry output of userqueue ops */
struct drm_amdgpu_userq_out {
/**
* For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
* queue ID to represent the newly created userqueue in the system, otherwise
* it should be ignored.
*/
__u32 queue_id;
__u32 _pad;
};
union drm_amdgpu_userq {
struct drm_amdgpu_userq_in in;
struct drm_amdgpu_userq_out out;
};
/* GFX V11 IP specific MQD parameters */
struct drm_amdgpu_userq_mqd_gfx11 {
/**
* @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
* Use AMDGPU_INFO_IOCTL to find the exact size of the object.
*/
__u64 shadow_va;
/**
* @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
* Use AMDGPU_INFO_IOCTL to find the exact size of the object.
*/
__u64 csa_va;
};
/* GFX V11 SDMA IP specific MQD parameters */
struct drm_amdgpu_userq_mqd_sdma_gfx11 {
/**
* @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
* This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
* to get the size.
*/
__u64 csa_va;
};
/* GFX V11 Compute IP specific MQD parameters */
struct drm_amdgpu_userq_mqd_compute_gfx11 {
/**
* @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
* This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
* to get the size.
*/
__u64 eop_va;
};
/* userq signal/wait ioctl */
struct drm_amdgpu_userq_signal {
/**
* @queue_id: Queue handle used by the userq fence creation function
* to retrieve the WPTR.
*/
__u32 queue_id;
__u32 pad;
/**
* @syncobj_handles: The list of syncobj handles submitted by the user queue
* job to be signaled.
*/
__u64 syncobj_handles;
/**
* @num_syncobj_handles: A count that represents the number of syncobj handles in
* @syncobj_handles.
*/
__u64 num_syncobj_handles;
/**
* @bo_read_handles: The list of BO handles that the submitted user queue job
* is using for read only. This will update BO fences in the kernel.
*/
__u64 bo_read_handles;
/**
* @bo_write_handles: The list of BO handles that the submitted user queue job
* is using for write only. This will update BO fences in the kernel.
*/
__u64 bo_write_handles;
/**
* @num_bo_read_handles: A count that represents the number of read BO handles in
* @bo_read_handles.
*/
__u32 num_bo_read_handles;
/**
* @num_bo_write_handles: A count that represents the number of write BO handles in
* @bo_write_handles.
*/
__u32 num_bo_write_handles;
};
struct drm_amdgpu_userq_fence_info {
/**
* @va: A gpu address allocated for each queue which stores the
* read pointer (RPTR) value.
*/
__u64 va;
/**
* @value: A 64 bit value represents the write pointer (WPTR) of the
* queue commands which compared with the RPTR value to signal the
* fences.
*/
__u64 value;
};
struct drm_amdgpu_userq_wait {
/**
* @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the
* wait queue and maintain the fence driver references in it.
*/
__u32 waitq_id;
__u32 pad;
/**
* @syncobj_handles: The list of syncobj handles submitted by the user queue
* job to get the va/value pairs.
*/
__u64 syncobj_handles;
/**
* @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
* the user queue job to get the va/value pairs at given @syncobj_timeline_points.
*/
__u64 syncobj_timeline_handles;
/**
* @syncobj_timeline_points: The list of timeline syncobj points submitted by the
* user queue job for the corresponding @syncobj_timeline_handles.
*/
__u64 syncobj_timeline_points;
/**
* @bo_read_handles: The list of read BO handles submitted by the user queue
* job to get the va/value pairs.
*/
__u64 bo_read_handles;
/**
* @bo_write_handles: The list of write BO handles submitted by the user queue
* job to get the va/value pairs.
*/
__u64 bo_write_handles;
/**
* @num_syncobj_timeline_handles: A count that represents the number of timeline
* syncobj handles in @syncobj_timeline_handles.
*/
__u16 num_syncobj_timeline_handles;
/**
* @num_fences: This field can be used both as input and output. As input it defines
* the maximum number of fences that can be returned and as output it will specify
* how many fences were actually returned from the ioctl.
*/
__u16 num_fences;
/**
* @num_syncobj_handles: A count that represents the number of syncobj handles in
* @syncobj_handles.
*/
__u32 num_syncobj_handles;
/**
* @num_bo_read_handles: A count that represents the number of read BO handles in
* @bo_read_handles.
*/
__u32 num_bo_read_handles;
/**
* @num_bo_write_handles: A count that represents the number of write BO handles in
* @bo_write_handles.
*/
__u32 num_bo_write_handles;
/**
* @out_fences: The field is a return value from the ioctl containing the list of
* address/value pairs to wait for.
*/
__u64 out_fences;
};
/* vm ioctl */
#define AMDGPU_VM_OP_RESERVE_VMID 1
#define AMDGPU_VM_OP_UNRESERVE_VMID 2
@ -239,13 +600,15 @@ union drm_amdgpu_vm {
/* sched ioctl */
#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
/** AMDGPU_CTX_PRIORITY_* */
__s32 priority;
__u32 flags;
__u32 ctx_id;
};
union drm_amdgpu_sched {
@ -290,9 +653,30 @@ struct drm_amdgpu_gem_userptr {
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
/* GFX9 and later: */
/* GFX9 - GFX11: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
#define AMDGPU_TILING_SCANOUT_SHIFT 63
#define AMDGPU_TILING_SCANOUT_MASK 0x1
/* GFX12 and later: */
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
/* These are DCC recompression setting for memory management: */
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
@ -440,14 +824,18 @@ struct drm_amdgpu_gem_op {
#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
/* Use NC MTYPE instead of default MTYPE */
/* Use Non Coherent MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_NC (1 << 5)
/* Use WC MTYPE instead of default MTYPE */
/* Use Write Combine MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_WC (2 << 5)
/* Use CC MTYPE instead of default MTYPE */
/* Use Cache Coherent MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_CC (3 << 5)
/* Use UC MTYPE instead of default MTYPE */
/* Use UnCached MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_UC (4 << 5)
/* Use Read Write MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_RW (5 << 5)
/* don't allocate MALL */
#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
struct drm_amdgpu_gem_va {
/** GEM object handle */
@ -463,6 +851,19 @@ struct drm_amdgpu_gem_va {
__u64 offset_in_bo;
/** Specify mapping size. Must be correctly aligned. */
__u64 map_size;
/**
* vm_timeline_point is a sequence number used to add new timeline point.
*/
__u64 vm_timeline_point;
/**
* The vm page table update fence is installed in given vm_timeline_syncobj_out
* at vm_timeline_point.
*/
__u32 vm_timeline_syncobj_out;
/** the number of syncobj handles in @input_fence_syncobj_handles */
__u32 num_syncobj_handles;
/** Array of sync object handle to wait for given input fences */
__u64 input_fence_syncobj_handles;
};
#define AMDGPU_HW_IP_GFX 0
@ -472,8 +873,14 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
/*
* From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
* both encoding and decoding jobs.
*/
#define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_NUM 8
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_VPE 9
#define AMDGPU_HW_IP_NUM 10
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
@ -482,6 +889,11 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@ -495,7 +907,7 @@ struct drm_amdgpu_cs_in {
/** Handle of resource list associated with CS */
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u32 flags;
/** this points to __u64 * which point to cs chunks */
__u64 chunks;
};
@ -520,6 +932,23 @@ union drm_amdgpu_cs {
/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
/* The IB fence should do the L2 writeback but not invalidate any shader
* caches (L2/vL1/sL1/I$). */
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
* This will reset wave ID counters for the IB.
*/
#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
/* Flag the IB as secure (TMZ)
*/
#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
/* Tell KMD to flush and invalidate caches
*/
#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@ -553,6 +982,12 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
struct drm_amdgpu_cs_chunk_syncobj {
__u32 handle;
__u32 flags;
__u64 point;
};
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
@ -575,12 +1010,33 @@ struct drm_amdgpu_cs_chunk_data {
};
};
/**
#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
__u64 shadow_va;
__u64 csa_va;
__u64 gds_va;
__u64 flags;
};
/*
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
*
*/
#define AMDGPU_IDS_FLAGS_FUSION 0x1
#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
#define AMDGPU_IDS_FLAGS_TMZ 0x4
#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
/*
* Query h/w info: Flag identifying VF/PF/PT mode
*
*/
#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300
#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8
#define AMDGPU_IDS_FLAGS_MODE_PF 0x0
#define AMDGPU_IDS_FLAGS_MODE_VF 0x1
#define AMDGPU_IDS_FLAGS_MODE_PT 0x2
/* indicate if acceleration can be working */
#define AMDGPU_INFO_ACCEL_WORKING 0x00
@ -620,6 +1076,34 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_ASD 0x0d
/* Subquery id: Query VCN firmware version */
#define AMDGPU_INFO_FW_VCN 0x0e
/* Subquery id: Query GFX RLC SRLC firmware version */
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
/* Subquery id: Query GFX RLC SRLG firmware version */
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
/* Subquery id: Query GFX RLC SRLS firmware version */
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
/* Subquery id: Query DMCU firmware version */
#define AMDGPU_INFO_FW_DMCU 0x12
#define AMDGPU_INFO_FW_TA 0x13
/* Subquery id: Query DMCUB firmware version */
#define AMDGPU_INFO_FW_DMCUB 0x14
/* Subquery id: Query TOC firmware version */
#define AMDGPU_INFO_FW_TOC 0x15
/* Subquery id: Query CAP firmware version */
#define AMDGPU_INFO_FW_CAP 0x16
/* Subquery id: Query GFX RLCP firmware version */
#define AMDGPU_INFO_FW_GFX_RLCP 0x17
/* Subquery id: Query GFX RLCV firmware version */
#define AMDGPU_INFO_FW_GFX_RLCV 0x18
/* Subquery id: Query MES_KIQ firmware version */
#define AMDGPU_INFO_FW_MES_KIQ 0x19
/* Subquery id: Query MES firmware version */
#define AMDGPU_INFO_FW_MES 0x1a
/* Subquery id: Query IMU firmware version */
#define AMDGPU_INFO_FW_IMU 0x1b
/* Subquery id: Query VPE firmware version */
#define AMDGPU_INFO_FW_VPE 0x1c
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
/* the used VRAM size */
@ -648,6 +1132,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_VBIOS_SIZE 0x1
/* Subquery id: Query vbios image */
#define AMDGPU_INFO_VBIOS_IMAGE 0x2
/* Subquery id: Query vbios info */
#define AMDGPU_INFO_VBIOS_INFO 0x3
/* Query UVD handles */
#define AMDGPU_INFO_NUM_HANDLES 0x1C
/* Query sensor related information */
@ -670,9 +1156,57 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
/* Subquery id: Query GPU stable pstate memory clock */
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
/* Subquery id: Query GPU peak pstate shader clock */
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
/* Subquery id: Query GPU peak pstate memory clock */
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
/* Subquery id: Query input GPU power */
#define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
/* query ras mask of enabled features*/
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
/* RAS MASK: UMC (VRAM) */
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
/* RAS MASK: SDMA */
#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
/* RAS MASK: GFX */
#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
/* RAS MASK: MMHUB */
#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
/* RAS MASK: ATHUB */
#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
/* RAS MASK: PCIE */
#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
/* RAS MASK: HDP */
#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
/* RAS MASK: XGMI */
#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
/* RAS MASK: DF */
#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
/* RAS MASK: SMN */
#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
/* RAS MASK: SEM */
#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
/* RAS MASK: MP0 */
#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
/* RAS MASK: MP1 */
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
/* RAS MASK: FUSE */
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS 0x21
/* Subquery id: Decode */
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
/* Subquery id: Encode */
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
/* Query the max number of IBs per gang per submission */
#define AMDGPU_INFO_MAX_IBS 0x22
/* query last page fault info */
#define AMDGPU_INFO_GPUVM_FAULT 0x23
/* query FW object size and alignment */
#define AMDGPU_INFO_UQ_FW_AREAS 0x24
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@ -740,6 +1274,10 @@ struct drm_amdgpu_info {
struct {
__u32 type;
} sensor_info;
struct {
__u32 type;
} video_cap;
};
};
@ -800,6 +1338,15 @@ struct drm_amdgpu_info_firmware {
__u32 feature;
};
struct drm_amdgpu_info_vbios {
__u8 name[64];
__u8 vbios_pn[64];
__u32 version;
__u32 pad;
__u8 vbios_ver_str[32];
__u8 date[32];
};
#define AMDGPU_VRAM_TYPE_UNKNOWN 0
#define AMDGPU_VRAM_TYPE_GDDR1 1
#define AMDGPU_VRAM_TYPE_DDR2 2
@ -809,6 +1356,10 @@ struct drm_amdgpu_info_firmware {
#define AMDGPU_VRAM_TYPE_HBM 6
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9
#define AMDGPU_VRAM_TYPE_DDR5 10
#define AMDGPU_VRAM_TYPE_LPDDR4 11
#define AMDGPU_VRAM_TYPE_LPDDR5 12
struct drm_amdgpu_info_device {
/** PCI Device ID */
@ -834,7 +1385,8 @@ struct drm_amdgpu_info_device {
__u32 enabled_rb_pipes_mask;
__u32 num_rb_pipes;
__u32 num_hw_gfx_contexts;
__u32 _pad;
/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
__u32 pcie_gen;
__u64 ids_flags;
/** Starting virtual address for UMDs. */
__u64 virtual_address_offset;
@ -881,13 +1433,41 @@ struct drm_amdgpu_info_device {
__u32 gs_prim_buffer_depth;
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
__u32 pcie_num_lanes;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
/** Starting high virtual address for UMDs. */
__u64 high_va_offset;
/** The maximum high virtual address */
__u64 high_va_max;
/* gfx10 pa_sc_tile_steering_override */
__u32 pa_sc_tile_steering_override;
/* disabled TCCs */
__u64 tcc_disabled_mask;
__u64 min_engine_clock;
__u64 min_memory_clock;
/* The following fields are only set on gfx11+, older chips set 0. */
__u32 tcp_cache_size; /* AKA GL0, VMEM cache */
__u32 num_sqc_per_wgp;
__u32 sqc_data_cache_size; /* AKA SMEM cache */
__u32 sqc_inst_cache_size;
__u32 gl1c_cache_size;
__u32 gl2c_cache_size;
__u64 mall_size; /* AKA infinity cache */
/* high 32 bits of the rb pipes mask */
__u32 enabled_rb_pipes_mask_hi;
/* shadow area size for gfx11 */
__u32 shadow_size;
/* shadow area base virtual alignment for gfx11 */
__u32 shadow_alignment;
/* context save area size for gfx11 */
__u32 csa_size;
/* context save area base virtual alignment for gfx11 */
__u32 csa_alignment;
/* Userq IP mask (1 << AMDGPU_HW_IP_*) */
__u32 userq_ip_mask;
__u32 pad;
};
struct drm_amdgpu_info_hw_ip {
@ -902,7 +1482,29 @@ struct drm_amdgpu_info_hw_ip {
__u32 ib_size_alignment;
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
__u32 available_rings;
__u32 _pad;
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
};
/* GFX metadata BO sizes and alignment info (in bytes) */
struct drm_amdgpu_info_uq_fw_areas_gfx {
/* shadow area size */
__u32 shadow_size;
/* shadow area base virtual mem alignment */
__u32 shadow_alignment;
/* context save area size */
__u32 csa_size;
/* context save area base virtual mem alignment */
__u32 csa_alignment;
};
/* IP specific metadata related information used in the
* subquery AMDGPU_INFO_UQ_FW_AREAS
*/
struct drm_amdgpu_info_uq_fw_areas {
union {
struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
};
};
struct drm_amdgpu_info_num_handles {
@ -930,6 +1532,44 @@ struct drm_amdgpu_info_vce_clock_table {
__u32 pad;
};
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
struct drm_amdgpu_info_video_codec_info {
__u32 valid;
__u32 max_width;
__u32 max_height;
__u32 max_pixels_per_frame;
__u32 max_level;
__u32 pad;
};
struct drm_amdgpu_info_video_caps {
struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
};
#define AMDGPU_VMHUB_TYPE_MASK 0xff
#define AMDGPU_VMHUB_TYPE_SHIFT 0
#define AMDGPU_VMHUB_TYPE_GFX 0
#define AMDGPU_VMHUB_TYPE_MM0 1
#define AMDGPU_VMHUB_TYPE_MM1 2
#define AMDGPU_VMHUB_IDX_MASK 0xff00
#define AMDGPU_VMHUB_IDX_SHIFT 8
struct drm_amdgpu_info_gpuvm_fault {
__u64 addr;
__u32 status;
__u32 vmhub;
};
/*
* Supported GPU families
*/
@ -941,6 +1581,15 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
#if defined(__cplusplus)
}

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

View file

@ -25,7 +25,6 @@
#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__
#include <stddef.h>
#include "drm.h"
#if defined(__cplusplus)
@ -202,10 +201,12 @@ struct drm_msm_gem_submit_bo {
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
#define MSM_SUBMIT_FLAGS ( \
MSM_SUBMIT_NO_IMPLICIT | \
MSM_SUBMIT_FENCE_FD_IN | \
MSM_SUBMIT_FENCE_FD_OUT | \
MSM_SUBMIT_SUDO | \
0)
/* Each cmdstream submit consists of a table of buffers involved, and

View file

@ -73,15 +73,11 @@ struct drm_nouveau_gpuobj_free {
uint32_t handle;
};
/* FIXME : maybe unify {GET,SET}PARAMs */
#define NOUVEAU_GETPARAM_PCI_VENDOR 3
#define NOUVEAU_GETPARAM_PCI_DEVICE 4
#define NOUVEAU_GETPARAM_BUS_TYPE 5
#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
#define NOUVEAU_GETPARAM_FB_SIZE 8
#define NOUVEAU_GETPARAM_AGP_SIZE 9
#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
@ -175,12 +171,12 @@ struct drm_nouveau_gem_pushbuf {
__u64 push;
__u32 suffix0;
__u32 suffix1;
#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
__u64 vram_available;
__u64 gart_available;
};
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep {
__u32 handle;
@ -191,29 +187,68 @@ struct drm_nouveau_gem_cpu_fini {
__u32 handle;
};
enum nouveau_bus_type {
NV_AGP = 0,
NV_PCI = 1,
NV_PCIE = 2,
};
struct drm_nouveau_sarea {
};
#define DRM_NOUVEAU_GETPARAM 0x00
#define DRM_NOUVEAU_SETPARAM 0x01
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
#define DRM_NOUVEAU_NVIF 0x07
#define DRM_NOUVEAU_SVM_INIT 0x08
#define DRM_NOUVEAU_SVM_BIND 0x09
#define DRM_NOUVEAU_GEM_NEW 0x40
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_INFO 0x44
struct drm_nouveau_svm_init {
__u64 unmanaged_addr;
__u64 unmanaged_size;
};
struct drm_nouveau_svm_bind {
__u64 header;
__u64 va_start;
__u64 va_end;
__u64 npages;
__u64 stride;
__u64 result;
__u64 reserved0;
__u64 reserved1;
};
#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
#define NOUVEAU_SVM_BIND_TARGET_BITS 32
#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
/*
* Below is use to validate ioctl argument, userspace can also use it to make
* sure that no bit are set beyond known fields for a given kernel version.
*/
#define NOUVEAU_SVM_BIND_VALID_BITS 48
#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
/*
* NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
* result: number of page successfuly migrate to the target memory.
*/
#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
/*
* NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
*/
#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
#if defined(__cplusplus)
}
#endif

View file

@ -24,7 +24,6 @@
#ifndef QXL_DRM_H
#define QXL_DRM_H
#include <stddef.h>
#include "drm.h"
#if defined(__cplusplus)
@ -89,7 +88,6 @@ struct drm_qxl_command {
__u32 pad;
};
/* XXX: call it drm_qxl_commands? */
struct drm_qxl_execbuffer {
__u32 flags; /* for future use */
__u32 commands_num;

File diff suppressed because it is too large Load diff

View file

@ -183,10 +183,17 @@ struct drm_vc4_submit_cl {
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
/* Unused field to align this struct on 64 bits. Must be set to 0.
* If one ever needs to add an u32 field to this struct, this field
* can be used.
/* Syncobj handle to wait on. If set, processing of this render job
* will not start until the syncobj is signaled. 0 means ignore.
*/
__u32 in_sync;
/* Syncobj handle to export fence to. If set, the fence in the syncobj
* will be replaced with a fence that signals upon completion of this
* render job. 0 means ignore.
*/
__u32 out_sync;
__u32 pad2;
};

View file

@ -46,6 +46,17 @@ extern "C" {
#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
#define DRM_VIRTGPU_WAIT 0x08
#define DRM_VIRTGPU_GET_CAPS 0x09
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
#define VIRTGPU_EXECBUF_RING_IDX 0x04
#define VIRTGPU_EXECBUF_FLAGS (\
VIRTGPU_EXECBUF_FENCE_FD_IN |\
VIRTGPU_EXECBUF_FENCE_FD_OUT |\
VIRTGPU_EXECBUF_RING_IDX |\
0)
struct drm_virtgpu_map {
__u64 offset; /* use for mmap system call */
@ -53,17 +64,40 @@ struct drm_virtgpu_map {
__u32 pad;
};
#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
0)
struct drm_virtgpu_execbuffer_syncobj {
__u32 handle;
__u32 flags;
__u64 point;
};
/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
struct drm_virtgpu_execbuffer {
__u32 flags; /* for future use */
__u32 flags;
__u32 size;
__u64 command; /* void* */
__u64 bo_handles;
__u32 num_bo_handles;
__u32 pad;
__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
__u32 num_in_syncobjs;
__u32 num_out_syncobjs;
__u64 in_syncobjs;
__u64 out_syncobjs;
};
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
struct drm_virtgpu_getparam {
__u64 param;
@ -93,7 +127,7 @@ struct drm_virtgpu_resource_info {
__u32 bo_handle;
__u32 res_handle;
__u32 size;
__u32 stride;
__u32 blob_mem;
};
struct drm_virtgpu_3d_box {
@ -110,6 +144,8 @@ struct drm_virtgpu_3d_transfer_to_host {
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
struct drm_virtgpu_3d_transfer_from_host {
@ -117,6 +153,8 @@ struct drm_virtgpu_3d_transfer_from_host {
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
@ -125,6 +163,12 @@ struct drm_virtgpu_3d_wait {
__u32 flags;
};
#define VIRTGPU_DRM_CAPSET_VIRGL 1
#define VIRTGPU_DRM_CAPSET_VIRGL2 2
#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_DRM_CAPSET_VENUS 4
#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_DRM_CAPSET_DRM 6
struct drm_virtgpu_get_caps {
__u32 cap_set_id;
__u32 cap_set_ver;
@ -133,11 +177,60 @@ struct drm_virtgpu_get_caps {
__u32 pad;
};
struct drm_virtgpu_resource_create_blob {
#define VIRTGPU_BLOB_MEM_GUEST 0x0001
#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
/* zero is invalid blob_mem */
__u32 blob_mem;
__u32 blob_flags;
__u32 bo_handle;
__u32 res_handle;
__u64 size;
/*
* for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
* VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
*/
__u32 pad;
__u32 cmd_size;
__u64 cmd;
__u64 blob_id;
};
#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004
struct drm_virtgpu_context_set_param {
__u64 param;
__u64 value;
};
struct drm_virtgpu_context_init {
__u32 num_params;
__u32 pad;
/* pointer to drm_virtgpu_context_set_param array */
__u64 ctx_set_params;
};
/*
* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
* effect. The event size is sizeof(drm_event), since there is no additional
* payload.
*/
#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
#define DRM_IOCTL_VIRTGPU_MAP \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
struct drm_virtgpu_execbuffer)
#define DRM_IOCTL_VIRTGPU_GETPARAM \
@ -168,6 +261,14 @@ struct drm_virtgpu_get_caps {
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
struct drm_virtgpu_get_caps)
#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
struct drm_virtgpu_resource_create_blob)
#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
struct drm_virtgpu_context_init)
#if defined(__cplusplus)
}
#endif

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