fdo-mirrors/mesa-drm
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/drm.git synced 2026-05-05 08:58:02 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions

drm/amdgpu: add new AMDGPU_INFO subquery for userqueue metadata

Browse source 
This patch:
- adds a new subquery (AMDGPU_INFO_UQ_FW_AREAS) in AMDGPU_INFO_IOCTL
  to get the size and alignment of shadow and csa objects from the
  kernel. This information is required for a userqueue consumer (like
  MESA/libdrm) to create the userqueue metadata objects properly.
- also adds supporting metadata structures and a high level wrapper
  function (amdgpu_query_uq_metadata_info) to the query, to make it
  easy to use.

The corresponding kernel changes for this UAPI extension can be found
in amd-gfx mailing list, link:
https://patchwork.freedesktop.org/patch/621390/?series=139715&rev=2

This patch adds support only for the GFX IP, and the other engines may
be supported in subsequent development.

V2: fix the build error due to exporting of helper function
V3: make an entry for amdgpu_query_uq_metadata_info in
    amdgpu-symbols.txt
V4: Rename the subquery to AMDGPU_INFO_UQ_FW_AREAS (Marek, Pierre-Eric)
V5: Addressed review comments (Pierre-Eric):
    - Fix the API comment to match the new IOCTL name
    - remove the unused uq_metadata parameter

Cc: Marek Olsak <marek.olsak@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Arvind Yadav <arvind.yadav@amd.com>
Reviewed-by: Marek Olsak <marek.olsak@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
This commit is contained in:
Shashank Sharma 2024-11-05 12:08:44 +01:00 • committed by Shashank Sharma
parent d387ec976f
commit 5d7d7c4318
4 changed files with 63 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
amdgpu/amdgpu-symbols.txt
View file

@ -70,6 +70,7 @@ amdgpu_query_hw_ip_count
amdgpu_query_hw_ip_info
amdgpu_query_info
amdgpu_query_sensor_info
amdgpu_query_uq_fw_area_info
amdgpu_query_video_caps_info
amdgpu_read_mm_registers
amdgpu_va_manager_alloc

21
amdgpu/amdgpu.h
View file

@ -42,6 +42,7 @@ extern "C" {
#endif
struct drm_amdgpu_info_hw_ip;
struct drm_amdgpu_info_uq_fw_areas;
struct drm_amdgpu_bo_list_entry;
/*--------------------------------------------------------------------------*/
@ -1172,6 +1173,26 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info);
/**
* Query FW area related information.
*
* The return size is query-specific and depends on the "type" parameter.
* No more than "size" bytes is returned.
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param type - \c [in] AMDGPU_HW_IP_*
* \param ip_instance - \c [in] HW IP index.
* \param info - \c [out] The pointer to return value
*
* \return 0 on success\n
* <0 - Negative POSIX error code
*
*/
int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev,
unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_uq_fw_areas *info);
/**
* Query heap information
*

18
amdgpu/amdgpu_gpu_info.c
View file

@ -137,6 +137,24 @@ drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev,
return 0;
}
drm_public int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev,
unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_uq_fw_areas *info)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)info;
request.return_size = sizeof(*info);
request.query = AMDGPU_INFO_UQ_FW_AREAS;
request.query_hw_ip.type = type;
request.query_hw_ip.ip_instance = ip_instance;
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
}
drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
{
int r, i;

23
include/drm/amdgpu_drm.h
View file

@ -931,6 +931,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_MAX_IBS 0x22
/* query last page fault info */
#define AMDGPU_INFO_GPUVM_FAULT 0x23
/* query FW object size and alignment */
#define AMDGPU_INFO_UQ_FW_AREAS 0x24
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@ -1207,6 +1209,27 @@ struct drm_amdgpu_info_hw_ip {
__u32 ip_discovery_version;
};
/* GFX metadata BO sizes and alignment info (in bytes) */
struct drm_amdgpu_info_uq_fw_areas_gfx {
/* shadow area size */
__u32 shadow_size;
/* shadow area base virtual mem alignment */
__u32 shadow_alignment;
/* context save area size */
__u32 csa_size;
/* context save area base virtual mem alignment */
__u32 csa_alignment;
};
/* IP specific metadata related information used in the
* subquery AMDGPU_INFO_UQ_FW_AREAS
*/
struct drm_amdgpu_info_uq_fw_areas {
union {
struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
};
};
struct drm_amdgpu_info_num_handles {
/** Max handles as supported by firmware for UVD */
__u32 uvd_max_handles;