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Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next. Generated using make headers_install. Generated from drm-next branch commit 04c8970771b4f1f39bb8453a2eeb188c4d5edbd6 Signed-off-by: Simon Ser <contact@emersion.fr>
This commit is contained in:
Simon Ser
parent
fa6f0fbad7
commit
3ba6183b79
3 changed files with 173 additions and 3 deletions
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@ -899,13 +899,17 @@ struct drm_syncobj_destroy {
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};
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#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
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#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_TIMELINE (1 << 1)
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#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
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#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_TIMELINE (1 << 1)
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struct drm_syncobj_handle {
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__u32 handle;
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__u32 flags;
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__s32 fd;
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__u32 pad;
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__u64 point;
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};
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struct drm_syncobj_transfer {
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@ -1018,6 +1022,13 @@ struct drm_crtc_queue_sequence {
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__u64 user_data; /* user data passed to event */
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};
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#define DRM_CLIENT_NAME_MAX_LEN 64
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struct drm_set_client_name {
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__u64 name_len;
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__u64 name;
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};
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#if defined(__cplusplus)
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}
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#endif
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@ -1282,6 +1293,16 @@ extern "C" {
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*/
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#define DRM_IOCTL_MODE_CLOSEFB DRM_IOWR(0xD0, struct drm_mode_closefb)
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/**
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* DRM_IOCTL_SET_CLIENT_NAME - Attach a name to a drm_file
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*
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* Having a name allows for easier tracking and debugging.
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* The length of the name (without null ending char) must be
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* <= DRM_CLIENT_NAME_MAX_LEN.
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* The call will fail if the name contains whitespaces or non-printable chars.
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*/
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#define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name)
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/*
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* Device specific ioctls should only be in their respective headers
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* The device specific ioctl range is from 0x40 to 0x9f.
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@ -377,6 +377,42 @@ extern "C" {
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*/
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#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
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/*
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* 3 plane YCbCr LSB aligned
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* In order to use these formats in a similar fashion to MSB aligned ones
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* implementation can multiply the values by 2^6=64. For that reason the padding
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* must only contain zeros.
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* index 0 = Y plane, [15:0] z:Y [6:10] little endian
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* index 1 = Cr plane, [15:0] z:Cr [6:10] little endian
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* index 2 = Cb plane, [15:0] z:Cb [6:10] little endian
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*/
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#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
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/*
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* 3 plane YCbCr LSB aligned
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* In order to use these formats in a similar fashion to MSB aligned ones
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* implementation can multiply the values by 2^4=16. For that reason the padding
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* must only contain zeros.
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* index 0 = Y plane, [15:0] z:Y [4:12] little endian
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* index 1 = Cr plane, [15:0] z:Cr [4:12] little endian
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* index 2 = Cb plane, [15:0] z:Cb [4:12] little endian
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*/
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#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0 = Y plane, [15:0] Y little endian
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* index 1 = Cr plane, [15:0] Cr little endian
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* index 2 = Cb plane, [15:0] Cb little endian
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*/
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#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@ -421,6 +457,8 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
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#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b
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#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c
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/* add more to the end as needed */
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@ -702,6 +740,31 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
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/*
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* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
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* on integrated graphics
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all compressible GEM objects.
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*/
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#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
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/*
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* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
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* on discrete graphics
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*
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* The main surface is Tile 4 and at plane index 0. For semi-planar formats
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* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
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* 0 and 1, respectively. The CCS for all planes are stored outside of the
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* GEM object in a reserved memory area dedicated for the storage of the
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* CCS data for all compressible GEM objects. The GEM object must be stored in
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* contiguous memory with a size aligned to 64KB
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*/
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#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -1428,6 +1491,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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*/
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#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
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/* MediaTek modifiers
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* Bits Parameter Notes
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* ----- ------------------------ ---------------------------------------------
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* 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*
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* 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*
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* 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*
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*
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*/
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#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags)
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/*
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* MediaTek Tiled Modifier
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* The lowest 8 bits of the modifier is used to specify the tiling
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* layout. Only the 16L_32S tiling is used for now, but we define an
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* "untiled" version and leave room for future expansion.
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*/
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#define MTK_FMT_MOD_TILE_MASK 0xf
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#define MTK_FMT_MOD_TILE_NONE 0x0
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#define MTK_FMT_MOD_TILE_16L32S 0x1
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/*
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* Bits 8-15 specify compression options
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*/
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#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)
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#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)
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#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)
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/*
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* Bits 16-23 specify how the bits of 10 bit formats are
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* stored out in memory
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*/
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#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)
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#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)
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#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)
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#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)
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/* alias for the most common tiling format */
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#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)
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/*
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* Apple GPU-tiled layouts.
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*
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* Apple GPUs support nonlinear tilings with optional lossless compression.
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*
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* GPU-tiled images are divided into 16KiB tiles:
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*
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* Bytes per pixel Tile size
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* --------------- ---------
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* 1 128x128
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* 2 128x64
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* 4 64x64
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* 8 64x32
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* 16 32x32
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*
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* Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
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*
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* Compressed images pad the body to 128-bytes and are immediately followed by a
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* metadata section. The metadata section rounds the image dimensions to
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* powers-of-two and contains 8 bytes for each 16x16 compression subtile.
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* Subtiles are interleaved (Morton order).
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*
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* All images are 128-byte aligned.
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*
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* These layouts fundamentally do not have meaningful strides. No matter how we
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* specify strides for these layouts, userspace unaware of Apple image layouts
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* will be unable to use correctly the specified stride for any purpose.
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* Userspace aware of the image layouts do not use strides. The most "correct"
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* convention would be setting the image stride to 0. Unfortunately, some
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* software assumes the stride is at least (width * bytes per pixel). We
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* therefore require that stride equals (width * bytes per pixel). Since the
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* stride is arbitrary here, we pick the simplest convention.
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*
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* Although containing two sections, compressed image layouts are treated in
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* software as a single plane. This is modelled after AFBC, a similar
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* scheme. Attempting to separate the sections to be "explicit" in DRM would
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* only generate more confusion, as software does not treat the image this way.
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*
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* For detailed information on the hardware image layouts, see
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* https://docs.mesa3d.org/drivers/asahi.html#image-layouts
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*/
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#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
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#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
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/*
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* AMD modifiers
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*
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@ -1491,6 +1638,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
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*/
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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@ -1506,6 +1654,8 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* 6 - 64KB_3D
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* 7 - 256KB_3D
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*/
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#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
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#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
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#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
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#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
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@ -1540,9 +1690,6 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
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#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
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#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
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/*
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* DCC supports embedding some clear colors directly in the DCC surface.
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* However, on older GPUs the rendering HW ignores the embedded clear color
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@ -859,6 +859,8 @@ struct drm_color_lut {
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/**
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* struct drm_plane_size_hint - Plane size hints
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* @width: The width of the plane in pixel
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* @height: The height of the plane in pixel
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*
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* The plane SIZE_HINTS property blob contains an
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* array of struct drm_plane_size_hint.
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