Daniel Schürmann d8481fd7cc aco/lower_to_hw: Fix SGPR Operand RegClasses of subdword copies ... Extracting from an SGPR could cause a wrong RegClass on the operand which could later lead to selecting VOPD instructions which falsely operate on the corresponding VGPR. Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39107>		2026-01-05 14:53:58 +00:00
..
addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	radv/ci: document recent flakes	2026-01-03 16:27:56 +00:00
common	ac/rgp: enable the new derived SPM chunk for performance counters on GFX12	2026-01-05 10:02:07 +00:00
compiler	aco/lower_to_hw: Fix SGPR Operand RegClasses of subdword copies	2026-01-05 14:53:58 +00:00
drm-shim	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: add FL capabilitie and lut container size	2025-09-22 10:37:22 +00:00
vulkan	radv: Mitigate GFX6-7 SMEM bug for robust OOB access	2026-01-02 23:42:16 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00