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radv: Mitigate GFX6-7 SMEM bug for robust OOB access
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Implement a mitigation for VM faults caused by SMEM reading
out of bounds when using robust buffer access.

- Pad uniform and storage buffer allocations with a readonly VM page
- Clamp SMEM offsets that can potentially read past the next page

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38769>
This commit is contained in:
Timur Kristóf 2025-12-19 13:23:20 -06:00 • committed by Marge Bot
parent f866bed0db
commit c05d276473
2 changed files with 7 additions and 1 deletions
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6
src/amd/vulkan/radv_buffer.c
View file

@ -265,6 +265,12 @@ radv_bo_create(struct radv_device *device, struct vk_object_base *object, uint64
struct radeon_winsys *ws = device->ws;
VkResult result;
/* Pad the BO with an extra VM page to mitigate OOB access from SMEM instructions.
* This doesn't allocate extra memory, just writes an extra page table entry.
*/
if (pdev->cache_key.mitigate_smem_oob && !is_internal)
flags |= RADEON_FLAG_VM_PAD_1PAGE;
result = ws->buffer_create(ws, size, alignment, domain, flags, priority, address, out_bo);
if (result != VK_SUCCESS)
return result;

2
src/amd/vulkan/radv_pipeline.c
View file

@ -521,7 +521,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
NIR_PASS(_, stage->nir, nir_lower_int64);
if (pdev->cache_key.mitigate_smem_oob)
NIR_PASS(_, stage->nir, ac_nir_fixup_mem_access_gfx6, &stage->args.ac, 4096, true, false);
NIR_PASS(_, stage->nir, ac_nir_fixup_mem_access_gfx6, &stage->args.ac, 4096, true, true);
radv_optimize_nir_algebraic(
stage->nir, io_to_mem || lowered_ngg || stage->stage == MESA_SHADER_COMPUTE || stage->stage == MESA_SHADER_TASK,