Samuel Pitoiset 5709644f2c radv: optimize barriers when clearing HiZ on GFX12 ... HiZ must only be cleared when the full HiZ workaround is enabled. This means that the previous slow clear draw would disable HiZ because it hits the conditions (ie. depth/stencil enable and depth writes enabled). So, the draw and the dispatch can run in parallel by moving the barrier earlier. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39433>		2026-01-27 14:37:01 +00:00
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addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	ac/nir: fix computing cube derivatives when the major axis is negative	2026-01-21 07:12:34 +00:00
common	amd/common/virtio: use device fd to init sync provider	2026-01-27 08:24:35 +00:00
compiler	aco/optimizer: optimize pack(undef, f2f16_rtz(a)) for salu	2026-01-26 10:54:22 +00:00
drm-shim	amd/drm-shim: add vega20	2026-01-08 09:30:54 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: add FL capabilitie and lut container size	2025-09-22 10:37:22 +00:00
vulkan	radv: optimize barriers when clearing HiZ on GFX12	2026-01-27 14:37:01 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00