Georg Lehmann a6a6c2f691 aco/ra: convert bitwise instruction to gfx11+ 16bit on demand ... The 32bit versions are smaller, allow more optimizations and VOPD, so only use the 16bit opcodes if nessecary. Foz-DB Navi31: Totals from 84 (0.10% of 80237) affected shaders: Instrs: 176673 -> 176347 (-0.18%); split: -0.20%, +0.01% CodeSize: 970148 -> 969716 (-0.04%); split: -0.08%, +0.03% VGPRs: 5876 -> 5864 (-0.20%) Latency: 2805974 -> 2805674 (-0.01%); split: -0.02%, +0.01% InvThroughput: 769007 -> 768738 (-0.03%); split: -0.04%, +0.01% VClause: 2593 -> 2597 (+0.15%) Copies: 23749 -> 23487 (-1.10%); split: -1.11%, +0.00% VALU: 107124 -> 106862 (-0.24%); split: -0.25%, +0.00% Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35919>		2025-07-31 12:07:07 +00:00
..
addrlib	amd/addrlib: remove the DCC page fault workaround	2025-04-01 03:23:22 -04:00
ci	radv/ci: deduplicate GPU_VERSION in ci-tron jobs	2025-07-30 23:18:04 +00:00
common	nir: add nir_tex_instr::can_speculate	2025-07-24 18:41:38 +00:00
compiler	aco/ra: convert bitwise instruction to gfx11+ 16bit on demand	2025-07-31 12:07:07 +00:00
drm-shim	amd: Add user queue HQD count to hw_ip info	2025-07-08 10:17:51 +00:00
gmlib	amd/gmlib: remove the executable bit	2025-06-12 07:44:27 +00:00
lanczoslib	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00
llvm	ac/llvm: fix readlane with vectors	2025-07-24 06:31:17 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Fix cost profiling support	2025-07-29 09:17:25 +00:00
vulkan	radv/nir/lower_cmat: load gfx11 8bit ACC using the B layout to get aligned loads	2025-07-30 07:25:51 +00:00
meson.build	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00