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amd: Add user queue HQD count to hw_ip info

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Add a new field userq_num_hqds to drm_amdgpu_info_hw_ip to expose the
number of available hardware queue descriptors (HQDs) for user queues.
This allows userspace to query the maximum number of user queues that
can be created for a particular IP block.

the patch link in driver side:
https://lists.freedesktop.org/archives/amd-gfx/2025-June/126686.html

v2: we should also put userq_num_hqds into radeon_info and
print it where other fields are printed. (Marek Olšák)

v3: rename num_userqs to num_queue_slots
    and add print log in ac_print_gpu_info. (Marek Olšák)
v4: rename userq_num_hqds to userq_num_slots in hw_ip_info,
    and update the hw information (Marek Olšák)

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35850>
This commit is contained in:
jesse.zhang 2025-07-01 09:54:22 +08:00 • committed by Marge Bot
parent a39779e695
commit 56d758d321
5 changed files with 16 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
include/drm-uapi/amdgpu_drm.h
View file

@ -1489,6 +1489,8 @@ struct drm_amdgpu_info_hw_ip {
__u32 available_rings;
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
/* Userq available slots */
__u32 userq_num_slots;
};
/* GFX metadata BO sizes and alignment info (in bytes) */

9
src/amd/common/ac_gpu_info.c
View file

@ -214,6 +214,7 @@ struct drm_amdgpu_info_hw_ip {
uint32_t ib_size_alignment;
uint32_t available_rings;
uint32_t ip_discovery_version;
uint32_t userq_num_slots;
};
struct drm_amdgpu_info_uq_fw_areas_gfx {
@ -557,6 +558,8 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->ip[ip_type].num_queues = 1;
} else if (ip_info.available_rings) {
info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
} else if (ip_info.userq_num_slots) {
info->ip[ip_type].num_queue_slots = ip_info.userq_num_slots;
} else {
continue;
}
@ -1910,11 +1913,11 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq);
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; i++) {
if (info->ip[i].num_queues) {
fprintf(f, " IP %-7s %2u.%u \tqueues:%u \talign:%u \tpad_dw:0x%x\n",
if (info->ip[i].num_queues || info->ip[i].num_queue_slots) {
fprintf(f, " IP %-7s %2u.%u \tqueues:%u \tqueue_slots:%u \talign:%u \tpad_dw:0x%x\n",
ac_get_ip_type_string(info, i),
info->ip[i].ver_major, info->ip[i].ver_minor, info->ip[i].num_queues,
info->ip[i].ib_alignment, info->ip[i].ib_pad_dw_mask);
info->ip[i].num_queue_slots,info->ip[i].ib_alignment, info->ip[i].ib_pad_dw_mask);
}
}

1
src/amd/common/ac_gpu_info.h
View file

@ -26,6 +26,7 @@ struct amd_ip_info {
uint8_t ver_minor;
uint8_t ver_rev;
uint8_t num_queues;
uint8_t num_queue_slots;
uint8_t num_instances;
uint32_t ib_alignment;
uint32_t ib_pad_dw_mask;

6
src/amd/drm-shim/amdgpu_devices.c
View file

@ -1329,6 +1329,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0000,
.userq_num_slots = 2,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
@ -1338,6 +1339,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0000,
.userq_num_slots = 16,
},
.fw_gfx_me = {
.ver = 1486,
@ -1937,6 +1939,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0500,
.userq_num_slots = 2,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
@ -1946,6 +1949,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0500,
.userq_num_slots = 16,
},
.fw_gfx_me = {
.ver = 29,
@ -2066,6 +2070,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xc0001,
.userq_num_slots = 8,
},
.hw_ip_compute = {
.hw_ip_version_major = 12,
@ -2075,6 +2080,7 @@ const struct amdgpu_device amdgpu_devices[] = {
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xc0001,
.userq_num_slots = 8,
},
.fw_gfx_me = {
.ver = 2590,

1
src/amd/drm-shim/amdgpu_dump_states.c
View file

@ -379,6 +379,7 @@ amdgpu_dump_hw_ips(int fd)
printf(" .ib_size_alignment = %u,\n", info.ib_size_alignment);
printf(" .available_rings = 0x%x,\n", info.available_rings);
printf(" .ip_discovery_version = 0x%04x,\n", info.ip_discovery_version);
printf(" .userq_num_slots = 0x%x,\n", info.userq_num_slots);
printf("},\n");
}
}